1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0120 global__variables__bank2 equ 288 5 01f0 global__variables__bank3 equ 496 6 0065 global__bit__variables__bank0 equ 101 7 00a0 global__bit__variables__bank1 equ 160 8 0120 global__bit__variables__bank2 equ 288 9 01f0 global__bit__variables__bank3 equ 496 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 0003 rp0___byte equ 3 17 0005 rp0___bit equ 5 18 0003 rp1___byte equ 3 19 0006 rp1___bit equ 6 20 0003 irp___byte equ 3 21 0007 irp___bit equ 7 22 0085 trisa___register equ 0x85 23 0086 trisb___register equ 0x86 24 0004 fsr___register equ 4 25 000a pclath___register equ 10 26 org 0 27 start: 28 000 0000 nop 29 001 0000 nop 30 002 0000 nop 31 003 2805 goto skip___interrupt 32 interrupt___vector: 33 004 0009 retfie 34 skip___interrupt: 35 ; Initialize A/D system to allow digital I/O 36 005 3007 movlw 7 37 006 009f movwf 31 38 ; Switch from register bank 0 to register bank 1 (which contains 159) 39 007 1683 bsf rp0___byte,rp0___bit 40 ; Register bank is now 1 41 008 019f clrf 159 42 ; Initialize TRIS registers 43 009 30c0 movlw 192 44 00a 0085 movwf trisa___register 45 00b 30cf movlw 207 46 00c 0086 movwf trisb___register 47 00d 018a clrf pclath___register 48 ; Switch from register bank 1 to register bank 0 49 00e 1283 bcf rp0___byte,rp0___bit 50 ; Register bank is now 0 51 00f 2844 goto main 52 ; comment ############################################################################# 53 ; comment {} 54 ; comment {Copyright < c > 2002 by Wayne C . Gramlich .} 55 ; comment {All rights reserved .} 56 ; comment {} 57 ; comment {Permission to use , copy , modify , distribute , and sell this software} 58 ; comment {for any purpose is hereby granted without fee provided that the above} 59 ; comment {copyright notice and this permission are retained . The author makes} 60 ; comment {no representations about the suitability of this software for any purpose .} 61 ; comment {It is provided { as is } without express or implied warranty .} 62 ; comment {} 63 ; comment {This is code for the SonarDT1 RoboBrick at :} 64 ; comment {} 65 ; comment {http : / / web . gramlich . net / projects / robobricks / sonardt1 / index . html} 66 ; comment {} 67 ; comment {Some pin assignments :} 68 ; comment {} 69 ; comment {No Name Kind Description} 70 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 71 ; comment {1 RA2 / AN2 / VREF Digital Out LED D4} 72 ; comment {2 RA3 / AN3 / CMP1 Digital Out LED D3} 73 ; comment {3 RA4 / TOCKI / CMP2 Digital Out LED D2} 74 ; comment {4 RA5 / MCLR * / THV Digital Out LED D1} 75 ; comment {5 VSS Ground Ground} 76 ; comment {6 RB0 / INT No Connection} 77 ; comment {7 RB1 / RX / DT Digital In Serial In} 78 ; comment {8 RB2 / TX / CK Digital Out Serial Out} 79 ; comment {9 RB3 / CCP1 Digital In Echo Return} 80 ; comment {10 RB4 / PGM Digital Out Trigger} 81 ; comment {11 RB5 Digital Out Servo Out} 82 ; comment {12 RB6 / T1OSO / TICK1 No Connection} 83 ; comment {13 RB7 / T1OSI No Connection} 84 ; comment {14 VDD Power + 5 Volts} 85 ; comment {15 RA6 / OSC2 / CLKOUT No Connection} 86 ; comment {16 RA7 / OSC1 / CLKIN Digital In Oscillator In} 87 ; comment {17 RA0 / AN0 Digital Out LED D6} 88 ; comment {18 RA1 / AN1 Digital Out LED D5} 89 ; comment {} 90 ; comment ############################################################################# 91 ; processor pic16f628 cp = off cpd = off lvp = off bowden = off mclre = off pwrte = off wdte = off fosc = ec 92 ; 16139=0x3f0b 8199=0x2007 93 __config 16139 94 2007 configuration___address equ 8199 95 ; constant clock_rate 20000000 96 1312d00 clock_rate equ 20000000 97 ; comment {Some character constants :} 98 ; constant sp 32 99 0020 sp equ 32 100 ; constant cr 13 101 000d cr equ 13 102 ; constant lf 10 103 000a lf equ 10 104 ; comment {Some register definitions :} 105 0001 tmr0 equ 1 106 0003 status equ 3 107 ; bind c status @ 0 108 0003 c equ status+0 109 0003 c__byte equ status+0 110 0000 c__bit equ 0 111 ; bind z status @ 2 112 0003 z equ status+0 113 0003 z__byte equ status+0 114 0002 z__bit equ 2 115 000b intcon equ 11 116 ; bind gie intcon @ 7 117 000b gie equ intcon+0 118 000b gie__byte equ intcon+0 119 0007 gie__bit equ 7 120 ; bind t0ie intcon @ 5 121 000b t0ie equ intcon+0 122 000b t0ie__byte equ intcon+0 123 0005 t0ie__bit equ 5 124 ; bind inte intcon @ 4 125 000b inte equ intcon+0 126 000b inte__byte equ intcon+0 127 0004 inte__bit equ 4 128 ; bind rbie intcon @ 3 129 000b rbie equ intcon+0 130 000b rbie__byte equ intcon+0 131 0003 rbie__bit equ 3 132 ; bind t0if intcon @ 2 133 000b t0if equ intcon+0 134 000b t0if__byte equ intcon+0 135 0002 t0if__bit equ 2 136 ; bind intf intcon @ 1 137 000b intf equ intcon+0 138 000b intf__byte equ intcon+0 139 0001 intf__bit equ 1 140 ; bind rbif intcon @ 0 141 000b rbif equ intcon+0 142 000b rbif__byte equ intcon+0 143 0000 rbif__bit equ 0 144 000c pir1 equ 12 145 ; bind eeif pir1 @ 7 146 000c eeif equ pir1+0 147 000c eeif__byte equ pir1+0 148 0007 eeif__bit equ 7 149 ; bind cmif pir1 @ 6 150 000c cmif equ pir1+0 151 000c cmif__byte equ pir1+0 152 0006 cmif__bit equ 6 153 ; bind rcif pir1 @ 5 154 000c rcif equ pir1+0 155 000c rcif__byte equ pir1+0 156 0005 rcif__bit equ 5 157 ; bind txif pir1 @ 4 158 000c txif equ pir1+0 159 000c txif__byte equ pir1+0 160 0004 txif__bit equ 4 161 ; bind ccp1if pir1 @ 2 162 000c ccp1if equ pir1+0 163 000c ccp1if__byte equ pir1+0 164 0002 ccp1if__bit equ 2 165 ; bind tmr2if pir1 @ 1 166 000c tmr2if equ pir1+0 167 000c tmr2if__byte equ pir1+0 168 0001 tmr2if__bit equ 1 169 ; bind tmr1if pir1 @ 0 170 000c tmr1if equ pir1+0 171 000c tmr1if__byte equ pir1+0 172 0000 tmr1if__bit equ 0 173 000e tmr1l equ 14 174 000f tmr1h equ 15 175 0010 t1con equ 16 176 ; bind t1ckps1 t1con @ 5 177 0010 t1ckps1 equ t1con+0 178 0010 t1ckps1__byte equ t1con+0 179 0005 t1ckps1__bit equ 5 180 ; bind t1ckps0 t1con @ 4 181 0010 t1ckps0 equ t1con+0 182 0010 t1ckps0__byte equ t1con+0 183 0004 t1ckps0__bit equ 4 184 ; bind t1oscen t1con @ 3 185 0010 t1oscen equ t1con+0 186 0010 t1oscen__byte equ t1con+0 187 0003 t1oscen__bit equ 3 188 ; bind t1sync t1con @ 2 189 0010 t1sync equ t1con+0 190 0010 t1sync__byte equ t1con+0 191 0002 t1sync__bit equ 2 192 ; bind tmr1cs t1con @ 1 193 0010 tmr1cs equ t1con+0 194 0010 tmr1cs__byte equ t1con+0 195 0001 tmr1cs__bit equ 1 196 ; bind tmr1on t1con @ 0 197 0010 tmr1on equ t1con+0 198 0010 tmr1on__byte equ t1con+0 199 0000 tmr1on__bit equ 0 200 0011 tmr2 equ 17 201 0012 t2con equ 18 202 ; bind toutps3 t2con @ 6 203 0012 toutps3 equ t2con+0 204 0012 toutps3__byte equ t2con+0 205 0006 toutps3__bit equ 6 206 ; bind toutps2 t2con @ 5 207 0012 toutps2 equ t2con+0 208 0012 toutps2__byte equ t2con+0 209 0005 toutps2__bit equ 5 210 ; bind toutps1 t2con @ 4 211 0012 toutps1 equ t2con+0 212 0012 toutps1__byte equ t2con+0 213 0004 toutps1__bit equ 4 214 ; bind toutps0 t2con @ 3 215 0012 toutps0 equ t2con+0 216 0012 toutps0__byte equ t2con+0 217 0003 toutps0__bit equ 3 218 ; bind tmr2on t2con @ 2 219 0012 tmr2on equ t2con+0 220 0012 tmr2on__byte equ t2con+0 221 0002 tmr2on__bit equ 2 222 ; bind t2ckps1 t2con @ 1 223 0012 t2ckps1 equ t2con+0 224 0012 t2ckps1__byte equ t2con+0 225 0001 t2ckps1__bit equ 1 226 ; bind t2ckps0 t2con @ 0 227 0012 t2ckps0 equ t2con+0 228 0012 t2ckps0__byte equ t2con+0 229 0000 t2ckps0__bit equ 0 230 0015 ccpr1l equ 21 231 0016 ccpr1h equ 22 232 0017 ccp1con equ 23 233 ; bind ccp1x ccp1con @ 5 234 0017 ccp1x equ ccp1con+0 235 0017 ccp1x__byte equ ccp1con+0 236 0005 ccp1x__bit equ 5 237 ; bind ccp1y ccp1con @ 4 238 0017 ccp1y equ ccp1con+0 239 0017 ccp1y__byte equ ccp1con+0 240 0004 ccp1y__bit equ 4 241 ; bind ccp1m3 ccp1con @ 3 242 0017 ccp1m3 equ ccp1con+0 243 0017 ccp1m3__byte equ ccp1con+0 244 0003 ccp1m3__bit equ 3 245 ; bind ccp1m2 ccp1con @ 2 246 0017 ccp1m2 equ ccp1con+0 247 0017 ccp1m2__byte equ ccp1con+0 248 0002 ccp1m2__bit equ 2 249 ; bind ccp1m1 ccp1con @ 1 250 0017 ccp1m1 equ ccp1con+0 251 0017 ccp1m1__byte equ ccp1con+0 252 0001 ccp1m1__bit equ 1 253 ; bind ccp1m0 ccp1con @ 0 254 0017 ccp1m0 equ ccp1con+0 255 0017 ccp1m0__byte equ ccp1con+0 256 0000 ccp1m0__bit equ 0 257 0018 rcsta equ 24 258 ; bind spen rcsta @ 7 259 0018 spen equ rcsta+0 260 0018 spen__byte equ rcsta+0 261 0007 spen__bit equ 7 262 ; bind rx9 rcsta @ 6 263 0018 rx9 equ rcsta+0 264 0018 rx9__byte equ rcsta+0 265 0006 rx9__bit equ 6 266 ; bind sren rcsta @ 5 267 0018 sren equ rcsta+0 268 0018 sren__byte equ rcsta+0 269 0005 sren__bit equ 5 270 ; bind cren rcsta @ 4 271 0018 cren equ rcsta+0 272 0018 cren__byte equ rcsta+0 273 0004 cren__bit equ 4 274 ; bind aden rcsta @ 3 275 0018 aden equ rcsta+0 276 0018 aden__byte equ rcsta+0 277 0003 aden__bit equ 3 278 ; bind ferr rcsta @ 2 279 0018 ferr equ rcsta+0 280 0018 ferr__byte equ rcsta+0 281 0002 ferr__bit equ 2 282 ; bind oerr rcsta @ 1 283 0018 oerr equ rcsta+0 284 0018 oerr__byte equ rcsta+0 285 0001 oerr__bit equ 1 286 ; bind rx9d rcsta @ 0 287 0018 rx9d equ rcsta+0 288 0018 rx9d__byte equ rcsta+0 289 0000 rx9d__bit equ 0 290 0019 txreg equ 25 291 001a rcreg equ 26 292 ; comment {Comparator module control :} 293 001f cmcon equ 31 294 ; bind c2out cmcon @ 7 295 001f c2out equ cmcon+0 296 001f c2out__byte equ cmcon+0 297 0007 c2out__bit equ 7 298 ; bind c1out cmcon @ 6 299 001f c1out equ cmcon+0 300 001f c1out__byte equ cmcon+0 301 0006 c1out__bit equ 6 302 ; bind c2inv cmcon @ 5 303 001f c2inv equ cmcon+0 304 001f c2inv__byte equ cmcon+0 305 0005 c2inv__bit equ 5 306 ; bind c1inv cmcon @ 4 307 001f c1inv equ cmcon+0 308 001f c1inv__byte equ cmcon+0 309 0004 c1inv__bit equ 4 310 ; bind cis cmcon @ 3 311 001f cis equ cmcon+0 312 001f cis__byte equ cmcon+0 313 0003 cis__bit equ 3 314 ; bind cm2 cmcon @ 2 315 001f cm2 equ cmcon+0 316 001f cm2__byte equ cmcon+0 317 0002 cm2__bit equ 2 318 ; bind cm1 cmcon @ 1 319 001f cm1 equ cmcon+0 320 001f cm1__byte equ cmcon+0 321 0001 cm1__bit equ 1 322 ; bind cm0 cmcon @ 0 323 001f cm0 equ cmcon+0 324 001f cm0__byte equ cmcon+0 325 0000 cm0__bit equ 0 326 0081 option equ 129 327 ; bind t0cs option @ 5 328 0081 t0cs equ option+0 329 0081 t0cs__byte equ option+0 330 0005 t0cs__bit equ 5 331 ; bind t0se option @ 4 332 0081 t0se equ option+0 333 0081 t0se__byte equ option+0 334 0004 t0se__bit equ 4 335 ; bind psa option @ 3 336 0081 psa equ option+0 337 0081 psa__byte equ option+0 338 0003 psa__bit equ 3 339 ; bind ps2 option @ 2 340 0081 ps2 equ option+0 341 0081 ps2__byte equ option+0 342 0002 ps2__bit equ 2 343 ; bind ps1 option @ 1 344 0081 ps1 equ option+0 345 0081 ps1__byte equ option+0 346 0001 ps1__bit equ 1 347 ; bind ps0 option @ 0 348 0081 ps0 equ option+0 349 0081 ps0__byte equ option+0 350 0000 ps0__bit equ 0 351 008c pie1 equ 140 352 ; bind eeie pie1 @ 7 353 008c eeie equ pie1+0 354 008c eeie__byte equ pie1+0 355 0007 eeie__bit equ 7 356 ; bind cmie pie1 @ 6 357 008c cmie equ pie1+0 358 008c cmie__byte equ pie1+0 359 0006 cmie__bit equ 6 360 ; bind rcie pie1 @ 5 361 008c rcie equ pie1+0 362 008c rcie__byte equ pie1+0 363 0005 rcie__bit equ 5 364 ; bind txie pie1 @ 4 365 008c txie equ pie1+0 366 008c txie__byte equ pie1+0 367 0004 txie__bit equ 4 368 ; bind ccp1ie pie1 @ 2 369 008c ccp1ie equ pie1+0 370 008c ccp1ie__byte equ pie1+0 371 0002 ccp1ie__bit equ 2 372 ; bind tmr2ie pie1 @ 1 373 008c tmr2ie equ pie1+0 374 008c tmr2ie__byte equ pie1+0 375 0001 tmr2ie__bit equ 1 376 ; bind tmr1ie pie1 @ 0 377 008c tmr1ie equ pie1+0 378 008c tmr1ie__byte equ pie1+0 379 0000 tmr1ie__bit equ 0 380 0092 pr2 equ 146 381 0098 txsta equ 152 382 ; bind tx9 txsta @ 6 383 0098 tx9 equ txsta+0 384 0098 tx9__byte equ txsta+0 385 0006 tx9__bit equ 6 386 ; bind txen txsta @ 5 387 0098 txen equ txsta+0 388 0098 txen__byte equ txsta+0 389 0005 txen__bit equ 5 390 ; bind sync txsta @ 4 391 0098 sync equ txsta+0 392 0098 sync__byte equ txsta+0 393 0004 sync__bit equ 4 394 ; bind brgh txsta @ 2 395 0098 brgh equ txsta+0 396 0098 brgh__byte equ txsta+0 397 0002 brgh__bit equ 2 398 ; bind trmt txsta @ 1 399 0098 trmt equ txsta+0 400 0098 trmt__byte equ txsta+0 401 0001 trmt__bit equ 1 402 ; bind tx9d txsta @ 0 403 0098 tx9d equ txsta+0 404 0098 tx9d__byte equ txsta+0 405 0000 tx9d__bit equ 0 406 0099 spbrg equ 153 407 ; comment {Some port , bit , and pin definitions :} 408 ; comment {Port A pin assignments :} 409 ; comment {RA0 : LED D6} 410 ; comment {RA1 : LED D5} 411 ; comment {RA2 : LED D4} 412 ; comment {RA3 : LED D3} 413 ; comment {RA4 : LED D2} 414 ; comment {RA5 : LED D1} 415 ; comment {RA6 : No / Connection} 416 ; comment {RA7 : Oscillator In} 417 ; constant led6_bit 0 418 0000 led6_bit equ 0 419 ; constant led5_bit 1 420 0001 led5_bit equ 1 421 ; constant led4_bit 2 422 0002 led4_bit equ 2 423 ; constant led3_bit 3 424 0003 led3_bit equ 3 425 ; constant led2_bit 4 426 0004 led2_bit equ 4 427 ; constant led1_bit 5 428 0005 led1_bit equ 5 429 ; constant nc1_bit 6 430 0006 nc1_bit equ 6 431 ; constant osc_in_bit 7 432 0007 osc_in_bit equ 7 433 0005 porta equ 5 434 0005 led6__byte equ 5 435 0000 led6__bit equ 0 436 0005 led5__byte equ 5 437 0001 led5__bit equ 1 438 0005 led4__byte equ 5 439 0002 led4__bit equ 2 440 0005 led3__byte equ 5 441 0003 led3__bit equ 3 442 0005 led2__byte equ 5 443 0004 led2__bit equ 4 444 0005 led1__byte equ 5 445 0005 led1__bit equ 5 446 0005 nc1__byte equ 5 447 0006 nc1__bit equ 6 448 0005 osc_in__byte equ 5 449 0007 osc_in__bit equ 7 450 ; comment {Port B pin assignments :} 451 ; comment {RB0 : No Connection} 452 ; comment {RB1 : Serial Input < RX >} 453 ; comment {RB2 : Serial Output < TX >} 454 ; comment {RB3 : Echo Return} 455 ; comment {RB4 : Trigger} 456 ; comment {RB5 : Servo Out} 457 ; comment {RB6 : No_Connection} 458 ; comment {RB7 : No_Connection} 459 ; constant nc2_bit 0 460 0000 nc2_bit equ 0 461 ; constant rx_bit 1 462 0001 rx_bit equ 1 463 ; constant tx_bit 2 464 0002 tx_bit equ 2 465 ; constant echo_return_bit 3 466 0003 echo_return_bit equ 3 467 ; constant trigger_bit 4 468 0004 trigger_bit equ 4 469 ; constant servo_out_bit 5 470 0005 servo_out_bit equ 5 471 ; constant nc3_bit 6 472 0006 nc3_bit equ 6 473 ; constant nc4_bit 7 474 0007 nc4_bit equ 7 475 ; constant sweep_maximum 16 476 0010 sweep_maximum equ 16 477 0006 portb equ 6 478 0006 nc2__byte equ 6 479 0000 nc2__bit equ 0 480 ; comment {When using the USART , both the TX and RX pins must be set to input :} 481 0006 tx_pin__byte equ 6 482 0002 tx_pin__bit equ 2 483 0006 rx_pin__byte equ 6 484 0001 rx_pin__bit equ 1 485 0006 echo_return__byte equ 6 486 0003 echo_return__bit equ 3 487 0006 trigger__byte equ 6 488 0004 trigger__bit equ 4 489 0006 servo_out__byte equ 6 490 0005 servo_out__bit equ 5 491 0006 nc3__byte equ 6 492 0006 nc3__bit equ 6 493 0006 nc4__byte equ 6 494 0007 nc4__bit equ 7 495 0020 send_in_index equ global__variables__bank0+0 496 0021 send_out_index equ global__variables__bank0+1 497 ; constant send_buffer_size 10 498 000a send_buffer_size equ 10 499 0022 send_buffer equ global__variables__bank0+2 500 ; comment {This code basically has to do 3 things :} 501 ; comment {} 502 ; comment {1 > It has to keep listening for commands from the serial input .} 503 ; comment {2 > It has to be able to keep a servo pulse of length . 5 ms to 2 . 0 ms} 504 ; comment {coming out every 20 ms or so .} 505 ; comment {3 > It has to trigger an sonar pulse , and time the resultant period} 506 ; comment {until the echo is heard < 100 uSec to 36 mSec > .} 507 ; comment {} 508 ; comment {Timer 0 is hooked up to the clock / 4 and then run through the 256} 509 ; comment {prescaler . With the clock running at 20 MHz , divided by 4 and again} 510 ; comment {by 256 leaves a clock frequency of 19531 Hz . 20 ms is a refresh rate} 511 ; comment {of 50 Hz . So , 19531 / 50 is 390 . 62 , or 390 . 390 does not quite fit} 512 ; comment {into 8 - bit , so we divide it by 2 to get 195 . So , we wait for the} 513 ; comment {Timer 0 flag to count through 195 twice , before triggering servo} 514 ; comment {pulse .} 515 002c glitch equ global__variables__bank0+12 516 002d id_index equ global__variables__bank0+13 517 ; string_constants Start 518 string___fetch: 519 010 0082 movwf pcl___register 520 ; id = 1 , 0 , 29 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 8 , 0s'SonarDT1' , 15 , 0s'Gramlich&Benson' 521 0000 id___string equ 0 522 id: 523 011 0782 addwf pcl___register,f 524 ; Length = 49 525 012 3431 retlw 49 526 ; 1 527 013 3401 retlw 1 528 ; 0 529 014 3400 retlw 0 530 ; 29 531 015 341d retlw 29 532 ; 0 533 016 3400 retlw 0 534 ; 0 535 017 3400 retlw 0 536 ; 0 537 018 3400 retlw 0 538 ; 0 539 019 3400 retlw 0 540 ; 0 541 01a 3400 retlw 0 542 ; 0r'16' 543 01b 342e retlw 46 ; random number 544 01c 34b9 retlw 185 ; random number 545 01d 34cb retlw 203 ; random number 546 01e 343f retlw 63 ; random number 547 01f 341a retlw 26 ; random number 548 020 347e retlw 126 ; random number 549 021 3418 retlw 24 ; random number 550 022 3421 retlw 33 ; random number 551 023 3410 retlw 16 ; random number 552 024 341b retlw 27 ; random number 553 025 345e retlw 94 ; random number 554 026 3408 retlw 8 ; random number 555 027 34e8 retlw 232 ; random number 556 028 3463 retlw 99 ; random number 557 029 340b retlw 11 ; random number 558 02a 3432 retlw 50 ; random number 559 ; 8 560 02b 3408 retlw 8 561 ; `SonarDT1' 562 02c 3453 retlw 83 563 02d 346f retlw 111 564 02e 346e retlw 110 565 02f 3461 retlw 97 566 030 3472 retlw 114 567 031 3444 retlw 68 568 032 3454 retlw 84 569 033 3431 retlw 49 570 ; 15 571 034 340f retlw 15 572 ; `Gramlich&Benson' 573 035 3447 retlw 71 574 036 3472 retlw 114 575 037 3461 retlw 97 576 038 346d retlw 109 577 039 346c retlw 108 578 03a 3469 retlw 105 579 03b 3463 retlw 99 580 03c 3468 retlw 104 581 03d 3426 retlw 38 582 03e 3442 retlw 66 583 03f 3465 retlw 101 584 040 346e retlw 110 585 041 3473 retlw 115 586 042 346f retlw 111 587 043 346e retlw 110 588 ; string__constants End 589 590 ; procedure main start 591 main: 592 002e main__variables__base equ global__variables__bank0+14 593 002e main__bytes__base equ main__variables__base+0 594 0060 main__bits__base equ main__variables__base+50 595 0034 main__total__bytes equ 52 596 005f main__478byte1 equ main__bytes__base+49 597 005f main__600byte0 equ main__bytes__base+49 598 005f main__617byte1 equ main__bytes__base+49 599 005f main__358byte0 equ main__bytes__base+49 600 005f main__617byte2 equ main__bytes__base+49 601 005f main__333byte0 equ main__bytes__base+49 602 005f main__657byte1 equ main__bytes__base+49 603 005f main__487byte0 equ main__bytes__base+49 604 005f main__649byte1 equ main__bytes__base+49 605 005f main__398byte0 equ main__bytes__base+49 606 005f main__401byte0 equ main__bytes__base+49 607 005f main__474byte0 equ main__bytes__base+49 608 005f main__332byte0 equ main__bytes__base+49 609 ; arguments_none 610 002e main__command equ main__bytes__base+0 611 002f main__command1 equ main__bytes__base+1 612 0030 main__command2 equ main__bytes__base+2 613 0031 main__command_need equ main__bytes__base+3 614 0032 main__command_have equ main__bytes__base+4 615 0060 main__continuous equ main__bits__base+0 616 0060 main__continuous__byte equ main__bits__base+0 617 0000 main__continuous__bit equ 0 618 0033 main__counter equ main__bytes__base+5 619 0034 main__distance_high equ main__bytes__base+6 620 0035 main__distance_low equ main__bytes__base+7 621 0060 main__phase equ main__bits__base+0 622 0060 main__phase__byte equ main__bits__base+0 623 0002 main__phase__bit equ 2 624 0036 main__result equ main__bytes__base+8 625 0037 main__servo equ main__bytes__base+9 626 0060 main__servo_enable equ main__bits__base+0 627 0060 main__servo_enable__byte equ main__bits__base+0 628 0004 main__servo_enable__bit equ 4 629 0038 main__sweep_highs equ main__bytes__base+10 630 0048 main__sweep_lows equ main__bytes__base+26 631 0058 main__sweep_initial equ main__bytes__base+42 632 0059 main__sweep_increment equ main__bytes__base+43 633 005a main__sweep_count equ main__bytes__base+44 634 005b main__sweep_counter equ main__bytes__base+45 635 005c main__sweep_delay equ main__bytes__base+46 636 005d main__sweep_sleep equ main__bytes__base+47 637 005e main__sweep_index equ main__bytes__base+48 638 0060 main__sweep_enable equ main__bits__base+0 639 0060 main__sweep_enable__byte equ main__bits__base+0 640 0006 main__sweep_enable__bit equ 6 641 0061 main__sweep_direction equ main__bits__base+1 642 0061 main__sweep_direction__byte equ main__bits__base+1 643 0000 main__sweep_direction__bit equ 0 644 ; call initialize {{ }} 645 044 225b call initialize 646 ; Initialize ring buffer : 647 ; sweep_enable := 0 648 045 1360 bcf main__sweep_enable__byte,main__sweep_enable__bit 649 ; send_in_index := 0 650 046 01a0 clrf send_in_index 651 ; send_out_index := 0 652 047 01a1 clrf send_out_index 653 ; command_need := 1 654 048 3001 movlw 1 655 049 00b1 movwf main__command_need 656 ; command_have := 0 657 04a 01b2 clrf main__command_have 658 ; continuous := 1 659 04b 1460 bsf main__continuous__byte,main__continuous__bit 660 ; servo := 0x80 661 04c 3080 movlw 128 662 04d 00b7 movwf main__servo 663 ; servo_enable := 0 664 04e 1260 bcf main__servo_enable__byte,main__servo_enable__bit 665 ; glitch := 0 666 04f 01ac clrf glitch 667 ; id_index := 0 668 050 01ad clrf id_index 669 ; sweep_sleep := 0 670 051 01dd clrf main__sweep_sleep 671 ; sweep_direction := 1 672 052 1461 bsf main__sweep_direction__byte,main__sweep_direction__bit 673 ; sweep_index := 1 674 053 3001 movlw 1 675 054 00de movwf main__sweep_index 676 ; Main loop 677 ; loop_forever ... start 678 main__306loop__forever: 679 ; Deal with timer 0 : 680 ; if { t0if && servo_enable } start 681 ; expression=`t0if' exp_delay=0 true_delay=-1 false_delay=2 true_size=71 false_size=1 682 055 1d0b btfss t0if__byte,t0if__bit 683 056 28a0 goto and308__0false 684 ; expression=`servo_enable' exp_delay=0 true_delay=-1 false_delay=0 true_size=69 false_size=0 685 057 1e60 btfss main__servo_enable__byte,main__servo_enable__bit 686 058 28a0 goto label308__1end 687 and308__0true: 688 ; if { t0if && servo_enable } body start 689 ; t0if := 0 690 059 110b bcf t0if__byte,t0if__bit 691 ; counter := counter - 1 692 05a 03b3 decf main__counter,f 693 ; if { c } start 694 ; expression=`{ c }' exp_delay=0 true_delay=-1 false_delay=0 true_size=65 false_size=0 695 05b 1c03 btfss c__byte,c__bit 696 05c 28a0 goto label311__0end 697 ; if { c } body start 698 ; See discussion above to see where 195 comes from : 699 ; counter := 195 700 05d 30c3 movlw 195 701 05e 00b3 movwf main__counter 702 ; if { phase } start 703 ; expression=`{ phase }' exp_delay=0 true_delay=1 false_delay=-1 true_size=1 false_size=59 704 05f 1960 btfsc main__phase__byte,main__phase__bit 705 060 289f goto label314__0true 706 label314__0false: 707 ; else body start 708 ; phase := 1 709 061 1560 bsf main__phase__byte,main__phase__bit 710 ; Now it is time to squirt out a servo pulse : 711 ; servo_out := 1 712 062 1686 bsf servo_out__byte,servo_out__bit 713 ; Now use Timer2 to control pulse width : 714 ; pr2 := servo 715 063 0837 movf main__servo,w 716 ; Switch from register bank 0 to register bank 1 (which contains pr2) 717 064 1683 bsf rp0___byte,rp0___bit 718 ; Register bank is now 1 719 065 0092 movwf pr2 720 ; tmr2 := 0 721 ; Switch from register bank 1 to register bank 0 (which contains tmr2) 722 066 1283 bcf rp0___byte,rp0___bit 723 ; Register bank is now 0 724 067 0191 clrf tmr2 725 ; tmr2on := 1 726 068 1512 bsf tmr2on__byte,tmr2on__bit 727 ; Now do any sweep processing : 728 ; if { sweep_enable } start 729 ; expression=`{ sweep_enable }' exp_delay=0 true_delay=-1 false_delay=0 true_size=51 false_size=0 730 069 1f60 btfss main__sweep_enable__byte,main__sweep_enable__bit 731 06a 289e goto label328__0end 732 ; if { sweep_enable } body start 733 ; sweep_sleep := sweep_sleep - 1 734 06b 03dd decf main__sweep_sleep,f 735 ; if { z } start 736 ; expression=`{ z }' exp_delay=0 true_delay=-1 false_delay=0 true_size=48 false_size=0 737 06c 1d03 btfss z__byte,z__bit 738 06d 289e goto label330__0end 739 ; if { z } body start 740 ; sweep_sleep := sweep_delay 741 06e 085c movf main__sweep_delay,w 742 06f 00dd movwf main__sweep_sleep 743 ; sweep_highs ~~ {{ sweep_index }} := distance_high 744 070 0834 movf main__distance_high,w 745 071 00df movwf main__332byte0 746 072 3038 movlw LOW main__sweep_highs 747 073 075e addwf main__sweep_index,w 748 074 0084 movwf fsr___register 749 075 085f movf main__332byte0,w 750 076 1383 bcf irp___register,irp___bit 751 077 0080 movwf indf___register 752 ; sweep_lows ~~ {{ sweep_index }} := distance_low 753 078 0835 movf main__distance_low,w 754 079 00df movwf main__333byte0 755 07a 3048 movlw LOW main__sweep_lows 756 07b 075e addwf main__sweep_index,w 757 07c 0084 movwf fsr___register 758 07d 085f movf main__333byte0,w 759 07e 1383 bcf irp___register,irp___bit 760 07f 0080 movwf indf___register 761 ; See if we need to change sweep direction : 762 ; if { sweep_direction } start 763 ; expression=`{ sweep_direction }' exp_delay=0 true_delay=-1 false_delay=-1 true_size=8 false_size=7 764 080 1c61 btfss main__sweep_direction__byte,main__sweep_direction__bit 765 081 288b goto label336__0false 766 label336__0true: 767 ; if { sweep_direction } body start 768 ; Going up : 769 ; if { sweep_index + 1 >= sweep_count } start 770 082 0a5e incf main__sweep_index,w 771 083 025a subwf main__sweep_count,w 772 084 1903 btfsc z___byte,z___bit 773 085 1003 bcf c___byte,c___bit 774 ; expression=`{ sweep_index + 1 >= sweep_count }' exp_delay=4 true_delay=2 false_delay=0 true_size=2 false_size=0 775 086 1803 btfsc c___byte,c___bit 776 087 288a goto label338__0end 777 ; if { sweep_index + 1 >= sweep_count } body start 778 ; sweep_direction := 0 779 088 1061 bcf main__sweep_direction__byte,main__sweep_direction__bit 780 ; sweep_counter := sweep_counter + 1 781 089 0adb incf main__sweep_counter,f 782 ; if { sweep_index + 1 >= sweep_count } body end 783 label338__0end: 784 ; if exp=` sweep_index + 1 >= sweep_count ' empty false 785 ; Other expression=`{ sweep_index + 1 >= sweep_count }' delay=-1 786 ; if { sweep_index + 1 >= sweep_count } end 787 ; if { sweep_direction } body end 788 08a 2892 goto label336__0end 789 label336__0false: 790 ; else body start 791 ; Going down : 792 ; if { sweep_index = 0 } start 793 08b 085e movf main__sweep_index,w 794 ; expression=`{ sweep_index = 0 }' exp_delay=1 true_delay=4 false_delay=0 true_size=4 false_size=0 795 08c 1d03 btfss z___byte,z___bit 796 08d 2892 goto label344__0end 797 ; if { sweep_index = 0 } body start 798 ; sweep_direction := 1 799 08e 1461 bsf main__sweep_direction__byte,main__sweep_direction__bit 800 ; servo := sweep_initial 801 08f 0858 movf main__sweep_initial,w 802 090 00b7 movwf main__servo 803 ; sweep_counter := sweep_counter + 1 804 091 0adb incf main__sweep_counter,f 805 ; if { sweep_index = 0 } body end 806 label344__0end: 807 ; if exp=` sweep_index = 0 ' empty false 808 ; Other expression=`{ sweep_index = 0 }' delay=-1 809 ; if { sweep_index = 0 } end 810 ; else body end 811 ; if exp=`sweep_direction' generic 812 label336__0end: 813 ; Other expression=`{ sweep_direction }' delay=-1 814 ; if { sweep_direction } end 815 ; Update the sweep index and corresponding 816 ; servo position : 817 ; if { sweep_direction } start 818 ; expression=`{ sweep_direction }' exp_delay=0 true_delay=3 false_delay=6 true_size=3 false_size=6 819 092 1c61 btfss main__sweep_direction__byte,main__sweep_direction__bit 820 093 2898 goto label353__0false 821 label353__0true: 822 ; if { sweep_direction } body start 823 ; sweep_index := sweep_index + 1 824 094 0ade incf main__sweep_index,f 825 ; servo := servo + sweep_increment 826 095 0859 movf main__sweep_increment,w 827 096 07b7 addwf main__servo,f 828 ; if { sweep_direction } body end 829 097 289e goto label353__0end 830 label353__0false: 831 ; else body start 832 ; sweep_index := sweep_index - 1 833 098 03de decf main__sweep_index,f 834 ; servo := servo - sweep_increment 835 099 0837 movf main__servo,w 836 09a 00df movwf main__358byte0 837 09b 0859 movf main__sweep_increment,w 838 09c 025f subwf main__358byte0,w 839 09d 00b7 movwf main__servo 840 ; else body end 841 ; if exp=`sweep_direction' generic 842 label353__0end: 843 ; Other expression=`{ sweep_direction }' delay=-1 844 ; if { sweep_direction } end 845 ; if { z } body end 846 label330__0end: 847 ; if exp=`z' empty false 848 ; Other expression=`{ z }' delay=-1 849 ; if { z } end 850 ; if { sweep_enable } body end 851 label328__0end: 852 ; if exp=`sweep_enable' empty false 853 ; Other expression=`{ sweep_enable }' delay=-1 854 ; if { sweep_enable } end 855 ; else body end 856 09e 28a0 goto label314__0end 857 label314__0true: 858 ; if { phase } body start 859 ; phase := 0 860 09f 1160 bcf main__phase__byte,main__phase__bit 861 ; if { phase } body end 862 ; if exp=`phase' generic 863 label314__0end: 864 ; Other expression=`{ phase }' delay=-1 865 ; if { phase } end 866 ; if { c } body end 867 label311__0end: 868 ; if exp=`c' empty false 869 ; Other expression=`{ c }' delay=-1 870 ; if { c } end 871 ; if { t0if && servo_enable } body end 872 label308__1end: 873 ; if exp=`servo_enable' empty false 874 ; Other expression=`servo_enable' delay=-1 875 ; if exp=`t0if' false goto 876 ; Other expression=`t0if' delay=-1 877 and308__0false: 878 and308__0end: 879 ; if { t0if && servo_enable } end 880 ; Deal with turning off servo pulse : 881 ; if { tmr2if } start 882 ; expression=`{ tmr2if }' exp_delay=0 true_delay=3 false_delay=0 true_size=3 false_size=0 883 0a0 1c8c btfss tmr2if__byte,tmr2if__bit 884 0a1 28a5 goto label367__0end 885 ; if { tmr2if } body start 886 ; tmr2if := 0 887 0a2 108c bcf tmr2if__byte,tmr2if__bit 888 ; servo_out := 0 889 0a3 1286 bcf servo_out__byte,servo_out__bit 890 ; tmr2on := 0 891 0a4 1112 bcf tmr2on__byte,tmr2on__bit 892 ; if { tmr2if } body end 893 label367__0end: 894 ; if exp=`tmr2if' empty false 895 ; Other expression=`{ tmr2if }' delay=-1 896 ; if { tmr2if } end 897 ; See whether we can transmit a character : 898 ; if { send_in_index != send_out_index && txif } start 899 0a5 0820 movf send_in_index,w 900 0a6 0221 subwf send_out_index,w 901 ; expression=`send_in_index != send_out_index' exp_delay=2 true_delay=-1 false_delay=2 true_size=13 false_size=1 902 0a7 1903 btfsc z___byte,z___bit 903 0a8 28b6 goto and374__0false 904 ; expression=`txif' exp_delay=0 true_delay=11 false_delay=0 true_size=11 false_size=0 905 0a9 1e0c btfss txif__byte,txif__bit 906 0aa 28b6 goto label374__1end 907 and374__0true: 908 ; if { send_in_index != send_out_index && txif } body start 909 ; txreg := send_buffer ~~ {{ send_out_index }} 910 0ab 3022 movlw LOW send_buffer 911 0ac 0721 addwf send_out_index,w 912 0ad 0084 movwf fsr___register 913 0ae 1383 bcf irp___register,irp___bit 914 0af 0800 movf indf___register,w 915 0b0 0099 movwf txreg 916 ; send_out_index := send_out_index + 1 917 0b1 0aa1 incf send_out_index,f 918 ; if { send_out_index >= send_buffer_size } start 919 0b2 300a movlw 10 920 0b3 0221 subwf send_out_index,w 921 ; expression=`{ send_out_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 922 0b4 1803 btfsc c___byte,c___bit 923 ; if { send_out_index >= send_buffer_size } body start 924 ; send_out_index := 0 925 0b5 01a1 clrf send_out_index 926 ; if { send_out_index >= send_buffer_size } body end 927 ; if exp=` send_out_index >= send_buffer_size ' false skip delay=4 928 ; Other expression=`{ send_out_index >= send_buffer_size }' delay=4 929 ; if { send_out_index >= send_buffer_size } end 930 ; if { send_in_index != send_out_index && txif } body end 931 label374__1end: 932 ; if exp=`txif' empty false 933 ; Other expression=`txif' delay=-1 934 ; if exp=`send_in_index != send_out_index' false goto 935 ; Other expression=`send_in_index != send_out_index' delay=-1 936 and374__0false: 937 and374__0end: 938 ; if { send_in_index != send_out_index && txif } end 939 ; See whether we ' ve got a character : 940 ; if { rcif } start 941 ; expression=`{ rcif }' exp_delay=0 true_delay=178 false_delay=0 true_size=347 false_size=0 942 0b6 1e8c btfss rcif__byte,rcif__bit 943 0b7 2a0a goto label383__0end 944 ; if { rcif } body start 945 ; Read the command : 946 ; switch { command_have } 947 0b8 3000 movlw HIGH switch__385block_start 948 0b9 008a movwf pclath___register 949 0ba 0832 movf main__command_have,w 950 ; case 0 951 ; case 1 952 ; case 2 953 switch__385block_start: 954 0bb 0782 addwf pcl___register,f 955 0bc 28bf goto switch__385block386 956 0bd 28c2 goto switch__385block389 957 0be 28c5 goto switch__385block392 958 switch__385block_end: 959 ; switch_check 385 switch__385block_start switch__385block_end 960 switch__385block386: 961 ; command := rcreg 962 0bf 081a movf rcreg,w 963 0c0 00ae movwf main__command 964 0c1 28c7 goto switch__385end 965 switch__385block389: 966 ; command1 := rcreg 967 0c2 081a movf rcreg,w 968 0c3 00af movwf main__command1 969 0c4 28c7 goto switch__385end 970 switch__385block392: 971 ; command2 := rcreg 972 0c5 081a movf rcreg,w 973 0c6 00b0 movwf main__command2 974 switch__385end: 975 ; command_have := command_have + 1 976 0c7 0ab2 incf main__command_have,f 977 ; switch { command >> 6 } 978 0c8 3000 movlw HIGH switch__398block_start 979 0c9 008a movwf pclath___register 980 0ca 0e2e swapf main__command,w 981 0cb 00df movwf main__398byte0 982 0cc 0cdf rrf main__398byte0,f 983 0cd 0c5f rrf main__398byte0,w 984 0ce 3903 andlw 3 985 ; case 0 986 ; case 1 987 ; case 2 988 ; case 3 989 switch__398block_start: 990 0cf 0782 addwf pcl___register,f 991 0d0 28d4 goto switch__398block399 992 0d1 293c goto switch__398block485 993 0d2 29fc goto switch__398block612 994 0d3 29fd goto switch__398block615 995 switch__398block_end: 996 ; switch_check 398 switch__398block_start switch__398block_end 997 switch__398block399: 998 ; Do Nothing : 999 ; switch { {{ command >> 3 }} & 7 } 1000 0d4 3000 movlw HIGH switch__401block_start 1001 0d5 008a movwf pclath___register 1002 0d6 0c2e rrf main__command,w 1003 0d7 00df movwf main__401byte0 1004 0d8 0cdf rrf main__401byte0,f 1005 0d9 0c5f rrf main__401byte0,w 1006 0da 3907 andlw 7 1007 ; case 0 1008 ; case 1 1009 ; case 2 3 1010 ; case 4 5 1011 switch__401block_start: 1012 0db 0782 addwf pcl___register,f 1013 0dc 28e4 goto switch__401block402 1014 0dd 290c goto switch__401block442 1015 0de 292b goto switch__401block472 1016 0df 292b goto switch__401block472 1017 0e0 2933 goto switch__401block476 1018 0e1 2933 goto switch__401block476 1019 0e2 293b goto switch__401default480 1020 0e3 293b goto switch__401default480 1021 switch__401block_end: 1022 ; switch_check 401 switch__401block_start switch__401block_end 1023 switch__401block402: 1024 ; Command = 0000 0 xxx 1025 ; switch { command & 7 } 1026 0e4 3000 movlw HIGH switch__404block_start 1027 0e5 008a movwf pclath___register 1028 0e6 3007 movlw 7 1029 0e7 052e andwf main__command,w 1030 ; case 0 1031 ; case 1 1032 ; case 2 1033 ; case 3 1034 ; case 4 1035 ; case 5 1036 ; case 6 1037 ; case 7 1038 switch__404block_start: 1039 0e8 0782 addwf pcl___register,f 1040 0e9 28f1 goto switch__404block405 1041 0ea 28f5 goto switch__404block409 1042 0eb 28f9 goto switch__404block413 1043 0ec 2900 goto switch__404block418 1044 0ed 2902 goto switch__404block422 1045 0ee 2904 goto switch__404block426 1046 0ef 2906 goto switch__404block430 1047 0f0 2909 goto switch__404block435 1048 switch__404block_end: 1049 ; switch_check 404 switch__404block_start switch__404block_end 1050 switch__404block405: 1051 ; Read Distance Low < Command = 0000 0000 > : 1052 ; call send_byte {{ distance_low }} 1053 0f1 0835 movf main__distance_low,w 1054 0f2 00e3 movwf send_byte__character 1055 0f3 2296 call send_byte 1056 0f4 290b goto switch__404end 1057 switch__404block409: 1058 ; Read Distance High < Command = 0000 0001 > : 1059 ; call send_byte {{ distance_high }} 1060 0f5 0834 movf main__distance_high,w 1061 0f6 00e3 movwf send_byte__character 1062 0f7 2296 call send_byte 1063 0f8 290b goto switch__404end 1064 switch__404block413: 1065 ; Read Distance Low and High < Command = 0000 0010 > : 1066 ; call send_byte {{ distance_low }} 1067 0f9 0835 movf main__distance_low,w 1068 0fa 00e3 movwf send_byte__character 1069 0fb 2296 call send_byte 1070 ; call send_byte {{ distance_high }} 1071 0fc 0834 movf main__distance_high,w 1072 0fd 00e3 movwf send_byte__character 1073 0fe 2296 call send_byte 1074 0ff 290b goto switch__404end 1075 switch__404block418: 1076 ; Trigger Distance Measurement < Command 0000 0011 > : 1077 ; tmr1on := 1 1078 100 1410 bsf tmr1on__byte,tmr1on__bit 1079 101 290b goto switch__404end 1080 switch__404block422: 1081 ; Disable Servo < Command 0000 0100 > : 1082 ; servo_enable := 0 1083 102 1260 bcf main__servo_enable__byte,main__servo_enable__bit 1084 103 290b goto switch__404end 1085 switch__404block426: 1086 ; Enable Servo < Command 0000 0101 > : 1087 ; servo_enable := 1 1088 104 1660 bsf main__servo_enable__byte,main__servo_enable__bit 1089 105 290b goto switch__404end 1090 switch__404block430: 1091 ; Disable Continuous Measurement < Command 0000 0110 > : 1092 ; continuous := 0 1093 106 1060 bcf main__continuous__byte,main__continuous__bit 1094 ; tmr1on := 0 1095 107 1010 bcf tmr1on__byte,tmr1on__bit 1096 108 290b goto switch__404end 1097 switch__404block435: 1098 ; Enable Continuous Measurement < Command 0000 0111 > : 1099 ; continuous := 1 1100 109 1460 bsf main__continuous__byte,main__continuous__bit 1101 ; tmr1on := 1 1102 10a 1410 bsf tmr1on__byte,tmr1on__bit 1103 switch__404end: 1104 10b 293b goto switch__401end 1105 switch__401block442: 1106 ; switch { command & 7 } 1107 10c 3001 movlw HIGH switch__443block_start 1108 10d 008a movwf pclath___register 1109 10e 3007 movlw 7 1110 10f 052e andwf main__command,w 1111 ; case 0 1112 ; case 1 1113 ; case 2 1114 ; case 3 1115 switch__443block_start: 1116 110 0782 addwf pcl___register,f 1117 111 2919 goto switch__443block444 1118 112 291b goto switch__443block448 1119 113 291d goto switch__443block452 1120 114 2921 goto switch__443block456 1121 115 292a goto switch__443default467 1122 116 292a goto switch__443default467 1123 117 292a goto switch__443default467 1124 118 292a goto switch__443default467 1125 switch__443block_end: 1126 ; switch_check 443 switch__443block_start switch__443block_end 1127 switch__443block444: 1128 ; Increment Servo < Command 0000 1000 > : 1129 ; servo := servo + 1 1130 119 0ab7 incf main__servo,f 1131 11a 292a goto switch__443end 1132 switch__443block448: 1133 ; Decrement Servo < Command 0000 1001 > : 1134 ; servo := servo - 1 1135 11b 03b7 decf main__servo,f 1136 11c 292a goto switch__443end 1137 switch__443block452: 1138 ; Increment Servo < Command 0000 1010 > : 1139 ; call send_byte {{ servo }} 1140 11d 0837 movf main__servo,w 1141 11e 00e3 movwf send_byte__character 1142 11f 2296 call send_byte 1143 120 292a goto switch__443end 1144 switch__443block456: 1145 ; Decrement Servo < Command 0000 1011 > : 1146 ; result := 0 1147 121 01b6 clrf main__result 1148 ; if { servo_enable } start 1149 ; expression=`{ servo_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1150 122 1a60 btfsc main__servo_enable__byte,main__servo_enable__bit 1151 ; if { servo_enable } body start 1152 ; result @ 0 := 1 1153 ; Select result @ 0 1154 0036 main__result__460select0 equ main__result+0 1155 0036 main__result__460select0__byte equ main__result+0 1156 0000 main__result__460select0__bit equ 0 1157 123 1436 bsf main__result__460select0__byte,main__result__460select0__bit 1158 ; if { servo_enable } body end 1159 ; if exp=`servo_enable' false skip delay=2 1160 ; Other expression=`{ servo_enable }' delay=2 1161 ; if { servo_enable } end 1162 ; if { continuous } start 1163 ; expression=`{ continuous }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1164 124 1860 btfsc main__continuous__byte,main__continuous__bit 1165 ; if { continuous } body start 1166 ; result @ 1 := 1 1167 ; Select result @ 1 1168 0036 main__result__463select0 equ main__result+0 1169 0036 main__result__463select0__byte equ main__result+0 1170 0001 main__result__463select0__bit equ 1 1171 125 14b6 bsf main__result__463select0__byte,main__result__463select0__bit 1172 ; if { continuous } body end 1173 ; if exp=`continuous' false skip delay=2 1174 ; Other expression=`{ continuous }' delay=2 1175 ; if { continuous } end 1176 ; call send_byte {{ result }} 1177 126 0836 movf main__result,w 1178 127 00e3 movwf send_byte__character 1179 128 2296 call send_byte 1180 129 292a goto switch__443end 1181 switch__443default467: 1182 ; Do nothing 1183 switch__443end: 1184 12a 293b goto switch__401end 1185 switch__401block472: 1186 ; Set Servo Low < Command 0001 llll > : 1187 ; servo := servo & 0xf0 | command & 0xf 1188 12b 30f0 movlw 240 1189 12c 0537 andwf main__servo,w 1190 12d 00df movwf main__474byte0 1191 12e 300f movlw 15 1192 12f 052e andwf main__command,w 1193 130 045f iorwf main__474byte0,w 1194 131 00b7 movwf main__servo 1195 132 293b goto switch__401end 1196 switch__401block476: 1197 ; Set Servo High < Command 0010 hhhh > : 1198 ; servo := servo & 0xf | command << 4 1199 133 300f movlw 15 1200 134 0537 andwf main__servo,w 1201 135 00df movwf main__478byte1 1202 136 0e2e swapf main__command,w 1203 137 39f0 andlw 240 1204 138 045f iorwf main__478byte1,w 1205 139 00b7 movwf main__servo 1206 13a 293b goto switch__401end 1207 switch__401default480: 1208 ; Do Nothing : 1209 switch__401end: 1210 13b 2a0a goto switch__398end 1211 switch__398block485: 1212 ; Command = 01 xx xxxx : 1213 ; switch { {{ command >> 3 }} & 7 } 1214 13c 3001 movlw HIGH switch__487block_start 1215 13d 008a movwf pclath___register 1216 13e 0c2e rrf main__command,w 1217 13f 00df movwf main__487byte0 1218 140 0cdf rrf main__487byte0,f 1219 141 0c5f rrf main__487byte0,w 1220 142 3907 andlw 7 1221 ; case 0 1222 ; case 1 1223 ; case 2 3 1224 ; case 4 5 1225 ; case 6 1226 switch__487block_start: 1227 143 0782 addwf pcl___register,f 1228 144 294c goto switch__487block488 1229 145 299b goto switch__487block549 1230 146 29c4 goto switch__487block585 1231 147 29c4 goto switch__487block585 1232 148 29d6 goto switch__487block591 1233 149 29d6 goto switch__487block591 1234 14a 29e1 goto switch__487block596 1235 14b 29ef goto switch__487default603 1236 switch__487block_end: 1237 ; switch_check 487 switch__487block_start switch__487block_end 1238 switch__487block488: 1239 ; Command = 0100 0 xxx : 1240 ; switch { command & 7 } 1241 14c 3001 movlw HIGH switch__490block_start 1242 14d 008a movwf pclath___register 1243 14e 3007 movlw 7 1244 14f 052e andwf main__command,w 1245 ; case 0 1246 ; case 1 1247 ; case 2 1248 ; case 3 1249 ; case 4 1250 ; case 5 1251 ; case 6 7 1252 switch__490block_start: 1253 150 0782 addwf pcl___register,f 1254 151 2959 goto switch__490block491 1255 152 2962 goto switch__490block498 1256 153 296b goto switch__490block505 1257 154 297a goto switch__490block515 1258 155 2983 goto switch__490block522 1259 156 298c goto switch__490block529 1260 157 298d goto switch__490block532 1261 158 298d goto switch__490block532 1262 switch__490block_end: 1263 ; switch_check 490 switch__490block_start switch__490block_end 1264 switch__490block491: 1265 ; Set Sweep Initial Position < command 0100 0000 > : 1266 ; command_need := 2 1267 159 3002 movlw 2 1268 15a 00b1 movwf main__command_need 1269 ; if { command_have = command_need } start 1270 15b 0832 movf main__command_have,w 1271 15c 0231 subwf main__command_need,w 1272 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1273 15d 1d03 btfss z___byte,z___bit 1274 15e 2961 goto label494__0end 1275 ; if { command_have = command_need } body start 1276 ; sweep_initial := command1 1277 15f 082f movf main__command1,w 1278 160 00d8 movwf main__sweep_initial 1279 ; if { command_have = command_need } body end 1280 label494__0end: 1281 ; if exp=` command_have = command_need ' empty false 1282 ; Other expression=`{ command_have = command_need }' delay=-1 1283 ; if { command_have = command_need } end 1284 161 299a goto switch__490end 1285 switch__490block498: 1286 ; Set Sweep Increment < command 0100 0001 > : 1287 ; command_need := 2 1288 162 3002 movlw 2 1289 163 00b1 movwf main__command_need 1290 ; if { command_have = command_need } start 1291 164 0832 movf main__command_have,w 1292 165 0231 subwf main__command_need,w 1293 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1294 166 1d03 btfss z___byte,z___bit 1295 167 296a goto label501__0end 1296 ; if { command_have = command_need } body start 1297 ; sweep_increment := command1 1298 168 082f movf main__command1,w 1299 169 00d9 movwf main__sweep_increment 1300 ; if { command_have = command_need } body end 1301 label501__0end: 1302 ; if exp=` command_have = command_need ' empty false 1303 ; Other expression=`{ command_have = command_need }' delay=-1 1304 ; if { command_have = command_need } end 1305 16a 299a goto switch__490end 1306 switch__490block505: 1307 ; Set Sweep Count < command 0100 0010 > : 1308 ; command_need := 2 1309 16b 3002 movlw 2 1310 16c 00b1 movwf main__command_need 1311 ; if { command_have = command_need } start 1312 16d 0832 movf main__command_have,w 1313 16e 0231 subwf main__command_need,w 1314 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=-1 false_delay=0 true_size=8 false_size=0 1315 16f 1d03 btfss z___byte,z___bit 1316 170 2979 goto label508__0end 1317 ; if { command_have = command_need } body start 1318 ; sweep_count := command1 1319 171 082f movf main__command1,w 1320 172 00da movwf main__sweep_count 1321 ; if { sweep_count > 16 } start 1322 173 3011 movlw 17 1323 174 025a subwf main__sweep_count,w 1324 ; expression=`{ sweep_count > 16 }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1325 175 1c03 btfss c___byte,c___bit 1326 176 2979 goto label510__0end 1327 ; if { sweep_count > 16 } body start 1328 ; sweep_count := 16 1329 177 3010 movlw 16 1330 178 00da movwf main__sweep_count 1331 ; if { sweep_count > 16 } body end 1332 label510__0end: 1333 ; if exp=` sweep_count > 16 ' empty false 1334 ; Other expression=`{ sweep_count > 16 }' delay=-1 1335 ; if { sweep_count > 16 } end 1336 ; if { command_have = command_need } body end 1337 label508__0end: 1338 ; if exp=` command_have = command_need ' empty false 1339 ; Other expression=`{ command_have = command_need }' delay=-1 1340 ; if { command_have = command_need } end 1341 179 299a goto switch__490end 1342 switch__490block515: 1343 ; Set Sweep Delay < command 0100 0011 > : 1344 ; command_need := 2 1345 17a 3002 movlw 2 1346 17b 00b1 movwf main__command_need 1347 ; if { command_have = command_need } start 1348 17c 0832 movf main__command_have,w 1349 17d 0231 subwf main__command_need,w 1350 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1351 17e 1d03 btfss z___byte,z___bit 1352 17f 2982 goto label518__0end 1353 ; if { command_have = command_need } body start 1354 ; sweep_delay := command1 1355 180 082f movf main__command1,w 1356 181 00dc movwf main__sweep_delay 1357 ; if { command_have = command_need } body end 1358 label518__0end: 1359 ; if exp=` command_have = command_need ' empty false 1360 ; Other expression=`{ command_have = command_need }' delay=-1 1361 ; if { command_have = command_need } end 1362 182 299a goto switch__490end 1363 switch__490block522: 1364 ; Set Sweep Counter < command 0100 0100 > : 1365 ; command_need := 2 1366 183 3002 movlw 2 1367 184 00b1 movwf main__command_need 1368 ; if { command_have = command_need } start 1369 185 0832 movf main__command_have,w 1370 186 0231 subwf main__command_need,w 1371 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1372 187 1d03 btfss z___byte,z___bit 1373 188 298b goto label525__0end 1374 ; if { command_have = command_need } body start 1375 ; sweep_counter := command1 1376 189 082f movf main__command1,w 1377 18a 00db movwf main__sweep_counter 1378 ; if { command_have = command_need } body end 1379 label525__0end: 1380 ; if exp=` command_have = command_need ' empty false 1381 ; Other expression=`{ command_have = command_need }' delay=-1 1382 ; if { command_have = command_need } end 1383 18b 299a goto switch__490end 1384 switch__490block529: 1385 ; Do_nothing < command 0100 0101 > : 1386 18c 299a goto switch__490end 1387 switch__490block532: 1388 ; Set Sweep Enable < command 0100 011 s > : 1389 ; sweep_enable := 0 1390 18d 1360 bcf main__sweep_enable__byte,main__sweep_enable__bit 1391 ; if { command @ 0 } start 1392 ; Alias variable for select command @ 0 1393 002e main__command__535select0 equ main__command+0 1394 002e main__command__535select0__byte equ main__command+0 1395 0000 main__command__535select0__bit equ 0 1396 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=5 false_delay=2 true_size=5 false_size=2 1397 18e 182e btfsc main__command__535select0__byte,main__command__535select0__bit 1398 18f 2993 goto label535__1true 1399 label535__1false: 1400 ; else body start 1401 ; sweep_enable := 0 1402 190 1360 bcf main__sweep_enable__byte,main__sweep_enable__bit 1403 ; servo_enable := 0 1404 191 1260 bcf main__servo_enable__byte,main__servo_enable__bit 1405 ; servo := sweep_initial 1406 ; 2 instructions found for sharing 1407 192 2998 goto label535__1end 1408 label535__1true: 1409 ; if { command @ 0 } body start 1410 ; sweep_sleep := 15 1411 193 300f movlw 15 1412 194 00dd movwf main__sweep_sleep 1413 ; sweep_enable := 1 1414 195 1760 bsf main__sweep_enable__byte,main__sweep_enable__bit 1415 ; sweep_index := 0 1416 196 01de clrf main__sweep_index 1417 ; servo_enable := 1 1418 197 1660 bsf main__servo_enable__byte,main__servo_enable__bit 1419 ; servo := sweep_initial 1420 ; 2 instructions found for sharing 1421 ; if exp=` command @ 0 ' generic 1422 label535__1end: 1423 ; Other expression=`{ command @ 0 }' delay=-1 1424 ; 2 shared instructions follow 1425 198 0858 movf main__sweep_initial,w 1426 199 00b7 movwf main__servo 1427 ; if { command @ 0 } end 1428 switch__490end: 1429 19a 29fb goto switch__487end 1430 switch__487block549: 1431 ; Command = 0100 1 xxx : 1432 ; switch { command & 7 } 1433 19b 3001 movlw HIGH switch__551block_start 1434 19c 008a movwf pclath___register 1435 19d 3007 movlw 7 1436 19e 052e andwf main__command,w 1437 ; case 0 1438 ; case 1 1439 ; case 2 1440 ; case 3 1441 ; case 4 1442 ; case 5 1443 switch__551block_start: 1444 19f 0782 addwf pcl___register,f 1445 1a0 29a8 goto switch__551block552 1446 1a1 29ac goto switch__551block556 1447 1a2 29b0 goto switch__551block560 1448 1a3 29b4 goto switch__551block564 1449 1a4 29b8 goto switch__551block568 1450 1a5 29bc goto switch__551block572 1451 1a6 29c3 goto switch__551default580 1452 1a7 29c3 goto switch__551default580 1453 switch__551block_end: 1454 ; switch_check 551 switch__551block_start switch__551block_end 1455 switch__551block552: 1456 ; Read Sweep Initial Position < command 0100 1000 > : 1457 ; call send_byte {{ sweep_initial }} 1458 1a8 0858 movf main__sweep_initial,w 1459 1a9 00e3 movwf send_byte__character 1460 1aa 2296 call send_byte 1461 1ab 29c3 goto switch__551end 1462 switch__551block556: 1463 ; Read Sweep Increment < command 0100 1001 > : 1464 ; call send_byte {{ sweep_increment }} 1465 1ac 0859 movf main__sweep_increment,w 1466 1ad 00e3 movwf send_byte__character 1467 1ae 2296 call send_byte 1468 1af 29c3 goto switch__551end 1469 switch__551block560: 1470 ; Read Sweep Count < command 0100 1010 > : 1471 ; call send_byte {{ sweep_count }} 1472 1b0 085a movf main__sweep_count,w 1473 1b1 00e3 movwf send_byte__character 1474 1b2 2296 call send_byte 1475 1b3 29c3 goto switch__551end 1476 switch__551block564: 1477 ; Read Sweep Delay < command 0100 1011 > : 1478 ; call send_byte {{ sweep_delay }} 1479 1b4 085c movf main__sweep_delay,w 1480 1b5 00e3 movwf send_byte__character 1481 1b6 2296 call send_byte 1482 1b7 29c3 goto switch__551end 1483 switch__551block568: 1484 ; Read Sweep Counter < command 0100 0100 > : 1485 ; call send_byte {{ sweep_counter }} 1486 1b8 085b movf main__sweep_counter,w 1487 1b9 00e3 movwf send_byte__character 1488 1ba 2296 call send_byte 1489 1bb 29c3 goto switch__551end 1490 switch__551block572: 1491 ; Read Sweep Enable < command 0100 0101 > : 1492 ; result := 0 1493 1bc 01b6 clrf main__result 1494 ; if { sweep_enable } start 1495 ; expression=`{ sweep_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1496 1bd 1b60 btfsc main__sweep_enable__byte,main__sweep_enable__bit 1497 ; if { sweep_enable } body start 1498 ; result @ 0 := 1 1499 ; Select result @ 0 1500 0036 main__result__576select0 equ main__result+0 1501 0036 main__result__576select0__byte equ main__result+0 1502 0000 main__result__576select0__bit equ 0 1503 1be 1436 bsf main__result__576select0__byte,main__result__576select0__bit 1504 ; if { sweep_enable } body end 1505 ; if exp=`sweep_enable' false skip delay=2 1506 ; Other expression=`{ sweep_enable }' delay=2 1507 ; if { sweep_enable } end 1508 ; call send_byte {{ result }} 1509 1bf 0836 movf main__result,w 1510 1c0 00e3 movwf send_byte__character 1511 1c1 2296 call send_byte 1512 1c2 29c3 goto switch__551end 1513 switch__551default580: 1514 ; Do nothing . 1515 switch__551end: 1516 1c3 29fb goto switch__487end 1517 switch__487block585: 1518 ; Read Sweep Index High and Low < command 0101 iiii > : 1519 ; result := command & 0xf 1520 1c4 300f movlw 15 1521 1c5 052e andwf main__command,w 1522 1c6 00b6 movwf main__result 1523 ; call send_byte {{ sweep_highs ~~ {{ result }} }} 1524 1c7 3038 movlw LOW main__sweep_highs 1525 1c8 0736 addwf main__result,w 1526 1c9 0084 movwf fsr___register 1527 1ca 1383 bcf irp___register,irp___bit 1528 1cb 0800 movf indf___register,w 1529 1cc 00e3 movwf send_byte__character 1530 1cd 2296 call send_byte 1531 ; call send_byte {{ sweep_lows ~~ {{ result }} }} 1532 1ce 3048 movlw LOW main__sweep_lows 1533 1cf 0736 addwf main__result,w 1534 1d0 0084 movwf fsr___register 1535 1d1 1383 bcf irp___register,irp___bit 1536 1d2 0800 movf indf___register,w 1537 1d3 00e3 movwf send_byte__character 1538 1d4 2296 call send_byte 1539 1d5 29fb goto switch__487end 1540 switch__487block591: 1541 ; Read Sweep Index High Only < command 0101 iiii > : 1542 ; result := command & 0xf 1543 1d6 300f movlw 15 1544 1d7 052e andwf main__command,w 1545 1d8 00b6 movwf main__result 1546 ; call send_byte {{ sweep_highs ~~ {{ result }} }} 1547 1d9 3038 movlw LOW main__sweep_highs 1548 1da 0736 addwf main__result,w 1549 1db 0084 movwf fsr___register 1550 1dc 1383 bcf irp___register,irp___bit 1551 1dd 0800 movf indf___register,w 1552 1de 00e3 movwf send_byte__character 1553 1df 2296 call send_byte 1554 1e0 29fb goto switch__487end 1555 switch__487block596: 1556 ; Write into memory : 1557 ; command_need := 3 1558 1e1 3003 movlw 3 1559 1e2 00b1 movwf main__command_need 1560 ; if { command_need = command_have } start 1561 1e3 0232 subwf main__command_have,w 1562 ; expression=`{ command_need = command_have }' exp_delay=2 true_delay=8 false_delay=0 true_size=8 false_size=0 1563 1e4 1d03 btfss z___byte,z___bit 1564 1e5 29ee goto label599__0end 1565 ; if { command_need = command_have } body start 1566 ; sweep_highs ~~ {{ command1 }} := command2 1567 1e6 0830 movf main__command2,w 1568 1e7 00df movwf main__600byte0 1569 1e8 3038 movlw LOW main__sweep_highs 1570 1e9 072f addwf main__command1,w 1571 1ea 0084 movwf fsr___register 1572 1eb 085f movf main__600byte0,w 1573 1ec 1383 bcf irp___register,irp___bit 1574 1ed 0080 movwf indf___register 1575 ; if { command_need = command_have } body end 1576 label599__0end: 1577 ; if exp=` command_need = command_have ' empty false 1578 ; Other expression=`{ command_need = command_have }' delay=-1 1579 ; if { command_need = command_have } end 1580 1ee 29fb goto switch__487end 1581 switch__487default603: 1582 ; Do nothing : 1583 ; command_need := 2 1584 1ef 3002 movlw 2 1585 1f0 00b1 movwf main__command_need 1586 ; if { command_need = command_have } start 1587 1f1 0232 subwf main__command_have,w 1588 ; expression=`{ command_need = command_have }' exp_delay=2 true_delay=5 false_delay=0 true_size=7 false_size=0 1589 1f2 1d03 btfss z___byte,z___bit 1590 1f3 29fb goto label606__0end 1591 ; if { command_need = command_have } body start 1592 ; call send_byte {{ sweep_highs ~~ {{ command1 }} }} 1593 1f4 3038 movlw LOW main__sweep_highs 1594 1f5 072f addwf main__command1,w 1595 1f6 0084 movwf fsr___register 1596 1f7 1383 bcf irp___register,irp___bit 1597 1f8 0800 movf indf___register,w 1598 1f9 00e3 movwf send_byte__character 1599 1fa 2296 call send_byte 1600 ; if { command_need = command_have } body end 1601 label606__0end: 1602 ; if exp=` command_need = command_have ' empty false 1603 ; Other expression=`{ command_need = command_have }' delay=-1 1604 ; if { command_need = command_have } end 1605 switch__487end: 1606 1fb 2a0a goto switch__398end 1607 switch__398block612: 1608 ; Do Nothing : 1609 1fc 2a0a goto switch__398end 1610 switch__398block615: 1611 ; Do shared commands : 1612 ; if { command >> 3 & 7 = 7 } start 1613 1fd 0c2e rrf main__command,w 1614 1fe 00df movwf main__617byte2 1615 1ff 0cdf rrf main__617byte2,f 1616 200 0c5f rrf main__617byte2,w 1617 201 3907 andlw 7 1618 202 00df movwf main__617byte1 1619 203 3007 movlw 7 1620 204 025f subwf main__617byte1,w 1621 ; expression=`{ command >> 3 & 7 = 7 }' exp_delay=9 true_delay=1 false_delay=0 true_size=3 false_size=0 1622 205 1d03 btfss z___byte,z___bit 1623 206 2a0a goto label617__3end 1624 ; if { command >> 3 & 7 = 7 } body start 1625 ; call do_shared {{ command }} 1626 207 082e movf main__command,w 1627 208 00e2 movwf do_shared__command 1628 209 2232 call do_shared 1629 ; if { command >> 3 & 7 = 7 } body end 1630 label617__3end: 1631 ; if exp=` command >> 3 & 7 = 7 ' empty false 1632 ; Other expression=`{ command >> 3 & 7 = 7 }' delay=-1 1633 ; if { command >> 3 & 7 = 7 } end 1634 switch__398end: 1635 ; if { rcif } body end 1636 label383__0end: 1637 ; if exp=`rcif' empty false 1638 ; Other expression=`{ rcif }' delay=-1 1639 ; if { rcif } end 1640 ; Reset command reader : 1641 ; if { command_have = command_need } start 1642 20a 0832 movf main__command_have,w 1643 20b 0231 subwf main__command_need,w 1644 ; expression=`{ command_have = command_need }' exp_delay=2 true_delay=3 false_delay=0 true_size=3 false_size=0 1645 20c 1d03 btfss z___byte,z___bit 1646 20d 2a11 goto label625__0end 1647 ; if { command_have = command_need } body start 1648 ; command_need := 1 1649 20e 3001 movlw 1 1650 20f 00b1 movwf main__command_need 1651 ; command_have := 0 1652 210 01b2 clrf main__command_have 1653 ; if { command_have = command_need } body end 1654 label625__0end: 1655 ; if exp=` command_have = command_need ' empty false 1656 ; Other expression=`{ command_have = command_need }' delay=-1 1657 ; if { command_have = command_need } end 1658 ; Read the captured distance : 1659 ; if { ccp1if } start 1660 ; expression=`{ ccp1if }' exp_delay=0 true_delay=10 false_delay=0 true_size=10 false_size=0 1661 211 1d0c btfss ccp1if__byte,ccp1if__bit 1662 212 2a1d goto label631__0end 1663 ; if { ccp1if } body start 1664 ; ccp1if := 0 1665 213 110c bcf ccp1if__byte,ccp1if__bit 1666 ; distance_high := ccpr1h 1667 214 0816 movf ccpr1h,w 1668 215 00b4 movwf main__distance_high 1669 ; distance_low := ccpr1l 1670 216 0815 movf ccpr1l,w 1671 217 00b5 movwf main__distance_low 1672 ; Make distance visible in LED ' s : 1673 ; porta := 0xff ^ ccpr1h 1674 218 30ff movlw 255 1675 219 0616 xorwf ccpr1h,w 1676 21a 0085 movwf porta 1677 ; if { ! continuous } start 1678 ; expression=`continuous' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 1679 21b 1c60 btfss main__continuous__byte,main__continuous__bit 1680 ; if { ! continuous } body start 1681 ; tmr1on := 0 1682 21c 1010 bcf tmr1on__byte,tmr1on__bit 1683 ; if { ! continuous } body end 1684 ; if exp=`continuous' true skip delay=2 1685 ; Other expression=`continuous' delay=2 1686 ; if { ! continuous } end 1687 ; if { ccp1if } body end 1688 label631__0end: 1689 ; if exp=`ccp1if' empty false 1690 ; Other expression=`{ ccp1if }' delay=-1 1691 ; if { ccp1if } end 1692 ; See whether we need to generate another trigger pulse : 1693 ; if { tmr1if } start 1694 ; expression=`{ tmr1if }' exp_delay=0 true_delay=54 false_delay=0 true_size=18 false_size=0 1695 21d 1c0c btfss tmr1if__byte,tmr1if__bit 1696 21e 2a31 goto label645__0end 1697 ; if { tmr1if } body start 1698 ; Make sure trigger is low for at least 10 uSec : 1699 ; tmr1if := 0 1700 21f 100c bcf tmr1if__byte,tmr1if__bit 1701 ; delay 25 ... start 1702 ; optimize 0 1703 ; Uniform delay remaining = 25 Accumulated Delay = 0 1704 ; tmr1on := 0 1705 220 1010 bcf tmr1on__byte,tmr1on__bit 1706 ; Uniform delay remaining = 24 Accumulated Delay = 1 1707 ; tmr1l := 0 1708 221 018e clrf tmr1l 1709 ; Uniform delay remaining = 23 Accumulated Delay = 2 1710 ; tmr1h := 0 1711 222 018f clrf tmr1h 1712 ; Uniform delay remaining = 22 Accumulated Delay = 3 1713 ; Uniform delay remaining = 22 Accumulated Delay = 3 1714 ; Delay 22 cycles 1715 223 3007 movlw 7 1716 224 00df movwf main__649byte1 1717 main__649delay0: 1718 225 0bdf decfsz main__649byte1,f 1719 226 2a25 goto main__649delay0 1720 ; optimize 1 1721 ; delay 25 ... end 1722 ; Fire trigger for 10 uSec : 1723 ; trigger := 1 1724 227 1606 bsf trigger__byte,trigger__bit 1725 ; delay 25 ... start 1726 ; optimize 0 1727 ; Uniform delay remaining = 25 Accumulated Delay = 0 1728 ; ccp1if := 0 1729 228 110c bcf ccp1if__byte,ccp1if__bit 1730 ; Uniform delay remaining = 24 Accumulated Delay = 1 1731 ; Uniform delay remaining = 24 Accumulated Delay = 1 1732 ; Delay 24 cycles 1733 229 3007 movlw 7 1734 22a 00df movwf main__657byte1 1735 main__657delay0: 1736 22b 0bdf decfsz main__657byte1,f 1737 22c 2a2b goto main__657delay0 1738 22d 0000 nop 1739 22e 0000 nop 1740 ; optimize 1 1741 ; delay 25 ... end 1742 ; Turn the timer on when trigger goes low : 1743 ; trigger := 0 1744 22f 1206 bcf trigger__byte,trigger__bit 1745 ; tmr1on := 1 1746 230 1410 bsf tmr1on__byte,tmr1on__bit 1747 ; if { tmr1if } body end 1748 label645__0end: 1749 ; if exp=`tmr1if' empty false 1750 ; Other expression=`{ tmr1if }' delay=-1 1751 ; if { tmr1if } end 1752 231 2855 goto main__306loop__forever 1753 ; loop_forever ... end 1754 ; procedure main end 1755 1756 ; procedure do_shared start 1757 do_shared: 1758 0062 do_shared__variables__base equ global__variables__bank0+66 1759 0062 do_shared__bytes__base equ do_shared__variables__base+0 1760 0063 do_shared__bits__base equ do_shared__variables__base+1 1761 0001 do_shared__total__bytes equ 1 1762 0062 do_shared__command equ do_shared__bytes__base+0 1763 ; Command 1111 1 xxx : 1764 ; switch { command & 7 } 1765 232 3002 movlw HIGH switch__674block_start 1766 233 008a movwf pclath___register 1767 234 3007 movlw 7 1768 235 0562 andwf do_shared__command,w 1769 ; case 0 1770 ; case 1 1771 ; case 2 1772 ; case 3 1773 ; case 4 1774 ; case 5 1775 ; case 6 1776 ; case 7 1777 switch__674block_start: 1778 236 0782 addwf pcl___register,f 1779 237 2a3f goto switch__674block675 1780 238 2a40 goto switch__674block678 1781 239 2a41 goto switch__674block681 1782 23a 2a44 goto switch__674block685 1783 23b 2a47 goto switch__674block689 1784 23c 2a52 goto switch__674block697 1785 23d 2a54 goto switch__674block701 1786 23e 2a59 goto switch__674block706 1787 switch__674block_end: 1788 ; switch_check 674 switch__674block_start switch__674block_end 1789 switch__674block675: 1790 ; Clock Decrement < Command 1111 1 xxx > : 1791 23f 2a5a goto switch__674end 1792 switch__674block678: 1793 ; Clock Increment < Command 1111 1 xxx > : 1794 240 2a5a goto switch__674end 1795 switch__674block681: 1796 ; Clock Read < Command 1111 1 xxx > : 1797 ; call send_byte {{ 0 }} 1798 241 01e3 clrf send_byte__character 1799 242 2296 call send_byte 1800 243 2a5a goto switch__674end 1801 switch__674block685: 1802 ; Clock Pulse < Command 1111 1 xxx > : 1803 ; call send_byte {{ 0 }} 1804 244 01e3 clrf send_byte__character 1805 245 2296 call send_byte 1806 246 2a5a goto switch__674end 1807 switch__674block689: 1808 ; Id Next < Command 1111 1 xxx > : 1809 ; call send_byte {{ id ~~ {{ id_index }} }} 1810 247 0a2d incf id_index,w 1811 248 018a clrf pclath___register 1812 249 2011 call id 1813 24a 00e3 movwf send_byte__character 1814 24b 2296 call send_byte 1815 ; id_index := id_index + 1 1816 24c 0aad incf id_index,f 1817 ; if { id_index >= id . size } start 1818 24d 3031 movlw 49 1819 24e 022d subwf id_index,w 1820 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1821 24f 1803 btfsc c___byte,c___bit 1822 ; if { id_index >= id . size } body start 1823 ; id_index := 0 1824 250 01ad clrf id_index 1825 ; if { id_index >= id . size } body end 1826 ; if exp=` id_index >= id . size ' false skip delay=4 1827 ; Other expression=`{ id_index >= id . size }' delay=4 1828 ; if { id_index >= id . size } end 1829 251 2a5a goto switch__674end 1830 switch__674block697: 1831 ; Id Reset < Command 1111 1 xxx > : 1832 ; id_index := 0 1833 252 01ad clrf id_index 1834 253 2a5a goto switch__674end 1835 switch__674block701: 1836 ; Glitch Read < Command 1111 1110 > : 1837 ; call send_byte {{ glitch }} 1838 254 082c movf glitch,w 1839 255 00e3 movwf send_byte__character 1840 256 2296 call send_byte 1841 ; glitch := 0 1842 257 01ac clrf glitch 1843 258 2a5a goto switch__674end 1844 switch__674block706: 1845 ; Glitch < Command 1111 1111 > : 1846 ; glitch := glitch + 1 1847 259 0aac incf glitch,f 1848 switch__674end: 1849 ; procedure do_shared end 1850 25a 3400 retlw 0 1851 1852 ; procedure initialize start 1853 initialize: 1854 0063 initialize__variables__base equ global__variables__bank0+67 1855 0063 initialize__bytes__base equ initialize__variables__base+0 1856 0063 initialize__bits__base equ initialize__variables__base+0 1857 0000 initialize__total__bytes equ 0 1858 ; arguments_none 1859 ; Get all interrupts turned off : 1860 ; intcon := 0 1861 25b 018b clrf intcon 1862 ; pie1 := 0 1863 ; Switch from register bank 0 to register bank 1 (which contains pie1) 1864 25c 1683 bsf rp0___byte,rp0___bit 1865 ; Register bank is now 1 1866 25d 018c clrf pie1 1867 ; pir1 := 0 1868 ; Switch from register bank 1 to register bank 0 (which contains pir1) 1869 25e 1283 bcf rp0___byte,rp0___bit 1870 ; Register bank is now 0 1871 25f 018c clrf pir1 1872 ; Initialize UART : 1873 ; Prescaler = low : 1874 ; brgh := 0 1875 ; Switch from register bank 0 to register bank 1 (which contains brgh__byte) 1876 260 1683 bsf rp0___byte,rp0___bit 1877 ; Register bank is now 1 1878 261 1118 bcf brgh__byte,brgh__bit 1879 ; Baud rate = 2400 baud : 1880 ; spbrg := 129 1881 262 3081 movlw 129 1882 263 0099 movwf spbrg 1883 ; Asynchronous mode : 1884 ; sync := 0 1885 264 1218 bcf sync__byte,sync__bit 1886 ; 8 - bit mode : 1887 ; tx9 := 0 1888 265 1318 bcf tx9__byte,tx9__bit 1889 ; Serial Port Enable : 1890 ; spen := 1 1891 ; Switch from register bank 1 to register bank 0 (which contains spen__byte) 1892 266 1283 bcf rp0___byte,rp0___bit 1893 ; Register bank is now 0 1894 267 1798 bsf spen__byte,spen__bit 1895 ; Keep interrupts off : 1896 ; txie := 0 1897 ; Switch from register bank 0 to register bank 1 (which contains txie__byte) 1898 268 1683 bsf rp0___byte,rp0___bit 1899 ; Register bank is now 1 1900 269 120c bcf txie__byte,txie__bit 1901 ; Clear out an previous character . 1902 ; txif := 0 1903 ; Switch from register bank 1 to register bank 0 (which contains txif__byte) 1904 26a 1283 bcf rp0___byte,rp0___bit 1905 ; Register bank is now 0 1906 26b 120c bcf txif__byte,txif__bit 1907 ; Enable the transmitter : 1908 ; txen := 1 1909 ; Switch from register bank 0 to register bank 1 (which contains txen__byte) 1910 26c 1683 bsf rp0___byte,rp0___bit 1911 ; Register bank is now 1 1912 26d 1698 bsf txen__byte,txen__bit 1913 ; Enable the receiver : 1914 ; Keep inerrupts off : 1915 ; rcie := 0 1916 26e 128c bcf rcie__byte,rcie__bit 1917 ; Enable continuous reception : 1918 ; cren := 1 1919 ; Switch from register bank 1 to register bank 0 (which contains cren__byte) 1920 26f 1283 bcf rp0___byte,rp0___bit 1921 ; Register bank is now 0 1922 270 1618 bsf cren__byte,cren__bit 1923 ; Enable single receptions : 1924 ; sren := 1 1925 271 1698 bsf sren__byte,sren__bit 1926 ; Disable address 1927 ; aden := 0 1928 272 1198 bcf aden__byte,aden__bit 1929 ; Initialize the timer 0 module : 1930 ; t0cs := 0 1931 ; Switch from register bank 0 to register bank 1 (which contains t0cs__byte) 1932 273 1683 bsf rp0___byte,rp0___bit 1933 ; Register bank is now 1 1934 274 1281 bcf t0cs__byte,t0cs__bit 1935 ; psa := 0 1936 275 1181 bcf psa__byte,psa__bit 1937 ; ps2 := 1 1938 276 1501 bsf ps2__byte,ps2__bit 1939 ; ps1 := 1 1940 277 1481 bsf ps1__byte,ps1__bit 1941 ; ps0 := 1 1942 278 1401 bsf ps0__byte,ps0__bit 1943 ; Initialize the timer 1 module : 1944 ; Prescale = 1 : 2 1945 ; t1ckps1 := 0 1946 ; Switch from register bank 1 to register bank 0 (which contains t1ckps1__byte) 1947 279 1283 bcf rp0___byte,rp0___bit 1948 ; Register bank is now 0 1949 27a 1290 bcf t1ckps1__byte,t1ckps1__bit 1950 ; t1ckps0 := 1 1951 27b 1610 bsf t1ckps0__byte,t1ckps0__bit 1952 ; Disable oscillator : 1953 ; t1oscen := 0 1954 27c 1190 bcf t1oscen__byte,t1oscen__bit 1955 ; T1SYNC not used when TMR1CS = 0 : 1956 ; t1sync := 0 1957 ; Internal clock : 1958 ; tmr1cs := 0 1959 27d 1090 bcf tmr1cs__byte,tmr1cs__bit 1960 ; Turn timer off : 1961 ; tmr1on := 1 1962 27e 1410 bsf tmr1on__byte,tmr1on__bit 1963 ; Clear interrupt flags : 1964 ; tmr1ie := 0 1965 ; Switch from register bank 0 to register bank 1 (which contains tmr1ie__byte) 1966 27f 1683 bsf rp0___byte,rp0___bit 1967 ; Register bank is now 1 1968 280 100c bcf tmr1ie__byte,tmr1ie__bit 1969 ; tmr1if := 0 1970 ; Switch from register bank 1 to register bank 0 (which contains tmr1if__byte) 1971 281 1283 bcf rp0___byte,rp0___bit 1972 ; Register bank is now 0 1973 282 100c bcf tmr1if__byte,tmr1if__bit 1974 ; Initialize the timer 2 module : 1975 ; tmr2ie := 0 1976 ; Switch from register bank 0 to register bank 1 (which contains tmr2ie__byte) 1977 283 1683 bsf rp0___byte,rp0___bit 1978 ; Register bank is now 1 1979 284 108c bcf tmr2ie__byte,tmr2ie__bit 1980 ; tmr2on := 0 1981 ; Switch from register bank 1 to register bank 0 (which contains tmr2on__byte) 1982 285 1283 bcf rp0___byte,rp0___bit 1983 ; Register bank is now 0 1984 286 1112 bcf tmr2on__byte,tmr2on__bit 1985 ; Postscale is 1 : 14 1986 ; toutps3 := 1 1987 287 1712 bsf toutps3__byte,toutps3__bit 1988 ; toutps2 := 1 1989 288 1692 bsf toutps2__byte,toutps2__bit 1990 ; toutps1 := 0 1991 289 1212 bcf toutps1__byte,toutps1__bit 1992 ; toutps0 := 1 1993 28a 1592 bsf toutps0__byte,toutps0__bit 1994 ; Prescale is 1 : 4 1995 ; t2ckps1 := 0 1996 28b 1092 bcf t2ckps1__byte,t2ckps1__bit 1997 ; t2ckps0 := 1 1998 28c 1412 bsf t2ckps0__byte,t2ckps0__bit 1999 ; Initialize the Capture / Compare / PWM < CCP > module : 2000 ; CCP1X and CCP1Y are unused : 2001 ; Capture mode every falling edge : 2002 ; ccp1m3 := 0 2003 28d 1197 bcf ccp1m3__byte,ccp1m3__bit 2004 ; ccp1m2 := 1 2005 28e 1517 bsf ccp1m2__byte,ccp1m2__bit 2006 ; ccp1m1 := 0 2007 28f 1097 bcf ccp1m1__byte,ccp1m1__bit 2008 ; ccp1m0 := 0 2009 290 1017 bcf ccp1m0__byte,ccp1m0__bit 2010 ; Turn off CCP module : 2011 ; ccp1ie := 0 2012 ; Switch from register bank 0 to register bank 1 (which contains ccp1ie__byte) 2013 291 1683 bsf rp0___byte,rp0___bit 2014 ; Register bank is now 1 2015 292 110c bcf ccp1ie__byte,ccp1ie__bit 2016 ; ccp1if := 0 2017 ; Switch from register bank 1 to register bank 0 (which contains ccp1if__byte) 2018 293 1283 bcf rp0___byte,rp0___bit 2019 ; Register bank is now 0 2020 294 110c bcf ccp1if__byte,ccp1if__bit 2021 ; procedure initialize end 2022 295 3400 retlw 0 2023 ; comment {The following procedures are used to send data back to the master :} 2024 2025 ; procedure send_byte start 2026 send_byte: 2027 0063 send_byte__variables__base equ global__variables__bank0+67 2028 0063 send_byte__bytes__base equ send_byte__variables__base+0 2029 0065 send_byte__bits__base equ send_byte__variables__base+2 2030 0002 send_byte__total__bytes equ 2 2031 0064 send_byte__809byte0 equ send_byte__bytes__base+1 2032 0063 send_byte__character equ send_byte__bytes__base+0 2033 ; This procedure will cause < character > to placed into 2034 ; a ring buffer for transmission . 2035 ; send_buffer ~~ {{ send_in_index }} := character 2036 296 0863 movf send_byte__character,w 2037 297 00e4 movwf send_byte__809byte0 2038 298 3022 movlw LOW send_buffer 2039 299 0720 addwf send_in_index,w 2040 29a 0084 movwf fsr___register 2041 29b 0864 movf send_byte__809byte0,w 2042 29c 1383 bcf irp___register,irp___bit 2043 29d 0080 movwf indf___register 2044 ; send_in_index := send_in_index + 1 2045 29e 0aa0 incf send_in_index,f 2046 ; if { send_in_index >= send_buffer_size } start 2047 29f 300a movlw 10 2048 2a0 0220 subwf send_in_index,w 2049 ; expression=`{ send_in_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2050 2a1 1803 btfsc c___byte,c___bit 2051 ; if { send_in_index >= send_buffer_size } body start 2052 ; send_in_index := 0 2053 2a2 01a0 clrf send_in_index 2054 ; if { send_in_index >= send_buffer_size } body end 2055 ; if exp=` send_in_index >= send_buffer_size ' false skip delay=4 2056 ; Other expression=`{ send_in_index >= send_buffer_size }' delay=4 2057 ; if { send_in_index >= send_buffer_size } end 2058 ; procedure send_byte end 2059 2a3 3400 retlw 0 2060 2061 ; Register bank 0 used 69 bytes of 96 available bytes 2062 ; Register bank 1 used 0 bytes of 80 available bytes 2063 ; Register bank 2 used 0 bytes of 48 available bytes 2064 ; Register bank 3 used 0 bytes of 0 available bytes 2065 2066 end