radix dec global__variables__bank0 equ 7 global__variables__bank1 equ 48 global__bit__variables__bank0 equ 24 global__bit__variables__bank1 equ 61 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers movlw 223 tris 6 ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the LED4 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See :} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / servo4 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12c509 cp = off wdte = off mclre = off fosc = intrc ; 10=0xa 4095=0xfff __config 10 configuration___address equ 4095 ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {define serial communication control constants} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; comment {Register definitions :} tmr0 equ 1 status equ 3 ; bind c status @ 0 c equ status+0 c__byte equ status+0 c__bit equ 0 ; bind z status @ 2 z equ status+0 z__byte equ status+0 z__bit equ 2 ; comment {For the 509 , there are 4 - bits of OSCCAL , for the 509 A , 6 - bits :} osccal equ 5 ; constant osccal_unit 0x10 osccal_unit equ 16 ; comment {Define port bit assignments :} porta equ 6 in0__byte equ 6 in0__bit equ 0 in1__byte equ 6 in1__bit equ 1 in2__byte equ 6 in2__bit equ 2 in3__byte equ 6 in3__bit equ 3 serial_in__byte equ 6 serial_in__bit equ 4 serial_out__byte equ 6 serial_out__bit equ 5 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 16 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'Shaft2A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 48 retlw 48 ; 1 retlw 1 ; 0 retlw 0 ; 16 retlw 16 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 39 ; random number retlw 86 ; random number retlw 250 ; random number retlw 246 ; random number retlw 119 ; random number retlw 229 ; random number retlw 39 ; random number retlw 6 ; random number retlw 39 ; random number retlw 121 ; random number retlw 67 ; random number retlw 172 ; random number retlw 43 ; random number retlw 67 ; random number retlw 191 ; random number retlw 143 ; random number ; 7 retlw 7 ; `Shaft2A' retlw 83 retlw 104 retlw 97 retlw 102 retlw 116 retlw 50 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; comment {Shaft state variables :} shaft0 equ global__variables__bank0+0 shaft1 equ global__variables__bank0+1 ; comment {Shaft counters :} shaft0_high equ global__variables__bank0+2 shaft0_low equ global__variables__bank0+3 shaft1_high equ global__variables__bank0+4 shaft1_low equ global__variables__bank0+5 ; comment {Shaft low threshold counters :} shaft0_low_high equ global__variables__bank0+6 shaft0_low_low equ global__variables__bank0+7 shaft1_low_high equ global__variables__bank0+8 shaft1_low_low equ global__variables__bank0+9 ; comment {Shaft high threshold counters :} shaft0_high_high equ global__variables__bank0+10 shaft0_high_low equ global__variables__bank0+11 shaft1_high_high equ global__variables__bank0+12 shaft1_high_low equ global__variables__bank0+13 ; comment {Interrupt and shaft direction bits :} interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 0 interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 1 shaft0_direction equ global__bit__variables__bank0+0 shaft0_direction__byte equ global__bit__variables__bank0+0 shaft0_direction__bit equ 2 shaft1_direction equ global__bit__variables__bank0+0 shaft1_direction__byte equ global__bit__variables__bank0+0 shaft1_direction__bit equ 3 ; comment {For now put all the smaller routines first so that they can live} ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} ; comment {can only call routines that are within the first 256 bytes < i . e .} ; comment {the first half > of the code page .} ; bank 1 ; Default register bank is now 1 receiving equ global__bit__variables__bank1+0 receiving__byte equ global__bit__variables__bank1+0 receiving__bit equ 0 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank1+0 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 4 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__111while__continue: ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__111while__break ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto get_byte__111while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__111while__break: ; `while serial_in ...' end ; Clear any interrupt being sent : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; char := 0 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf get_byte__char ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__125_loop: ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; char := char >> 1 bcf c___byte,c___bit ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf get_byte__char,f ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__129select0 equ get_byte__char+0 get_byte__char__129select0__byte equ get_byte__char+0 get_byte__char__129select0__bit equ 7 bsf get_byte__char__129select0__byte,get_byte__char__129select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz get_byte__count,f goto get_byte__125_loop get_byte__125_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; return char ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank1+4 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label157__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; if { receiving } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 label157__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Send the data : ; `count_down count 8 ...' start movlw 8 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__count send_byte__170_loop: ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__171select0 equ send_byte__char+0 send_byte__char__171select0__byte equ send_byte__char+0 send_byte__char__171select0__bit equ 0 btfss send_byte__char__171select0__byte,send_byte__char__171select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__171select0__byte,send_byte__char__171select0__bit bsf serial_out__byte,serial_out__bit ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz send_byte__count,f goto send_byte__170_loop send_byte__170_done: ; `count_down count 8 ...' end ; Send the stop bit : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; procedure send_byte end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 retlw 0 ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 switch__205block_start: addwf pcl___register,f goto switch__205block206 goto switch__205block209 goto switch__205block217 goto switch__205block233 switch__205block_end: ; switch_check 205 switch__205block_start switch__205block_end switch__250block_start: addwf pcl___register,f goto switch__250block251 goto switch__250block254 goto switch__250block262 goto switch__250block278 switch__250block_end: ; switch_check 250 switch__250block_start switch__250block_end delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+14 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+2 delay__total__bytes equ 3 delay__296byte6 equ delay__bytes__base+1 delay__250byte0 equ delay__bytes__base+1 delay__245byte0 equ delay__bytes__base+1 delay__205byte0 equ delay__bytes__base+1 delay__293byte6 equ delay__bytes__base+1 delay__290byte6 equ delay__bytes__base+1 delay__251byte1 equ delay__bytes__base+1 delay__206byte1 equ delay__bytes__base+1 delay__299byte6 equ delay__bytes__base+1 ; arguments_none ; uniform_delay instructions_per_delay ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; This procedure will delay for 1 / 3 of a bit time . ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__temp equ delay__bytes__base+0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 134 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Process shaft 0 : ; Uniform delay remaining = 133 Accumulated Delay = 1 ; temp := porta & 3 movlw 3 andwf porta,w movwf delay__temp ; Uniform delay remaining = 130 Accumulated Delay = 4 ; Convert 2 - bit grey code into 2 - bit binary : ; Uniform delay remaining = 130 Accumulated Delay = 4 ; if { temp @ 1 } start ; Alias variable for select temp @ 1 delay__temp__202select0 equ delay__temp+0 delay__temp__202select0__byte equ delay__temp+0 delay__temp__202select0__bit equ 1 ; expression=`{ temp @ 1 }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc delay__temp__202select0__byte,delay__temp__202select0__bit goto label202__1true label202__1false: ; Delay 1 cycles nop goto label202__1end label202__1true: ; if { temp @ 1 } body start ; Uniform delay remaining = 130 Accumulated Delay = 0 ; temp := temp ^ 1 movlw 1 xorwf delay__temp,f ; Uniform delay remaining = 128 Accumulated Delay = 2 ; Uniform delay remaining = 128 Accumulated Delay = 2 ; if { temp @ 1 } body end ; if exp=` temp @ 1 ' total delay=5 ; if exp=` temp @ 1 ' generic label202__1end: ; Other expression=`{ temp @ 1 }' delay=5 ; if { temp @ 1 } end ; Uniform delay remaining = 125 Accumulated Delay = 9 ; switch { {{ shaft0 - temp }} & 3 } movf shaft0,w movwf delay__205byte0 movf delay__temp,w subwf delay__205byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 goto switch__205block_start switch__205block206: ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Nothing changed ; do nothing : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Delay 8 cycles movlw 2 movwf delay__206byte1 delay__206delay0: decfsz delay__206byte1,f goto delay__206delay0 nop goto switch__205end switch__205block209: ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Increment : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; shaft0_direction := 0 bcf shaft0_direction__byte,shaft0_direction__bit ; Uniform delay remaining = 124 Accumulated Delay = 1 ; shaft0_low := shaft0_low + 1 incf shaft0_low,f ; Uniform delay remaining = 123 Accumulated Delay = 2 ; if { z } start ; expression=`{ z }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z__byte,z__bit ; if { z } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; shaft0_high := shaft0_high + 1 incf shaft0_high,f ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { z } body end ; if exp=`z' false skip delay=2 ; Other expression=`{ z }' delay=2 ; if { z } end ; Uniform delay remaining = 121 Accumulated Delay = 4 ; Uniform delay remaining = 121 Accumulated Delay = 4 ; Delay 4 cycles nop nop nop nop goto switch__205end switch__205block217: ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Double increment / decrement : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; if { shaft0_direction } start ; expression=`{ shaft0_direction }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 btfss shaft0_direction__byte,shaft0_direction__bit goto label219__0false label219__0true: ; if { shaft0_direction } body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Double increment : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; shaft0_low := shaft0_low - 2 movlw 254 addwf shaft0_low,f ; Uniform delay remaining = 123 Accumulated Delay = 2 ; if { ! c } start ; expression=`c' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 btfss c__byte,c__bit ; if { ! c } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; shaft0_high := shaft0_high - 1 decf shaft0_high,f ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { ! c } body end ; if exp=`c' true skip delay=2 ; Other expression=`c' delay=2 ; if { ! c } end ; Uniform delay remaining = 121 Accumulated Delay = 4 ; Uniform delay remaining = 121 Accumulated Delay = 4 ; if { shaft0_direction } body end goto label219__0end label219__0false: ; else body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Double decrement : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; shaft0_low := shaft0_low + 2 movlw 2 addwf shaft0_low,f ; Uniform delay remaining = 123 Accumulated Delay = 2 ; if { c } start ; expression=`{ c }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c__byte,c__bit ; if { c } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; shaft0_high := shaft0_high + 1 incf shaft0_high,f ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { c } body end ; if exp=`c' false skip delay=2 ; Other expression=`{ c }' delay=2 ; if { c } end ; Uniform delay remaining = 121 Accumulated Delay = 4 ; Uniform delay remaining = 121 Accumulated Delay = 4 ; else body end ; Delay 1 cycles nop ; if exp=`shaft0_direction' total delay=8 ; if exp=`shaft0_direction' generic label219__0end: ; Other expression=`{ shaft0_direction }' delay=8 ; if { shaft0_direction } end ; Uniform delay remaining = 117 Accumulated Delay = 8 ; Uniform delay remaining = 117 Accumulated Delay = 8 goto switch__205end switch__205block233: ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Decrement : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; shaft0_direction := 1 bsf shaft0_direction__byte,shaft0_direction__bit ; Uniform delay remaining = 124 Accumulated Delay = 1 ; if { shaft0_low = 0 } start movf shaft0_low,w ; expression=`{ shaft0_low = 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z___byte,z___bit ; if { shaft0_low = 0 } body start ; Uniform delay remaining = 124 Accumulated Delay = 0 ; shaft0_high := shaft0_high - 1 decf shaft0_high,f ; Uniform delay remaining = 123 Accumulated Delay = 1 ; Uniform delay remaining = 123 Accumulated Delay = 1 ; if { shaft0_low = 0 } body end ; if exp=` shaft0_low = 0 ' false skip delay=3 ; Other expression=`{ shaft0_low = 0 }' delay=3 ; if { shaft0_low = 0 } end ; Uniform delay remaining = 121 Accumulated Delay = 4 ; shaft0_low := shaft0_low - 1 decf shaft0_low,f ; Uniform delay remaining = 120 Accumulated Delay = 5 ; Uniform delay remaining = 120 Accumulated Delay = 5 ; Delay 3 cycles nop nop nop goto switch__205end switch__205end: ; Total switch delay = 20 exp_delay=7 case_delay=10 ; Uniform delay remaining = 105 Accumulated Delay = 29 ; shaft0 := temp movf delay__temp,w movwf shaft0 ; Uniform delay remaining = 103 Accumulated Delay = 31 ; Uniform delay remaining = 103 Accumulated Delay = 31 ; Process shaft 1 : ; Uniform delay remaining = 103 Accumulated Delay = 31 ; temp := {{ porta >> 2 }} & 3 rrf porta,w movwf delay__245byte0 rrf delay__245byte0,w andlw 63 andlw 3 movwf delay__temp ; Uniform delay remaining = 97 Accumulated Delay = 37 ; Convert 2 - bit grey code into 2 - bit binary : ; Uniform delay remaining = 97 Accumulated Delay = 37 ; if { temp @ 1 } start ; Alias variable for select temp @ 1 delay__temp__247select0 equ delay__temp+0 delay__temp__247select0__byte equ delay__temp+0 delay__temp__247select0__bit equ 1 ; expression=`{ temp @ 1 }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc delay__temp__247select0__byte,delay__temp__247select0__bit goto label247__1true label247__1false: ; Delay 1 cycles nop goto label247__1end label247__1true: ; if { temp @ 1 } body start ; Uniform delay remaining = 97 Accumulated Delay = 0 ; temp := temp ^ 1 movlw 1 xorwf delay__temp,f ; Uniform delay remaining = 95 Accumulated Delay = 2 ; Uniform delay remaining = 95 Accumulated Delay = 2 ; if { temp @ 1 } body end ; if exp=` temp @ 1 ' total delay=5 ; if exp=` temp @ 1 ' generic label247__1end: ; Other expression=`{ temp @ 1 }' delay=5 ; if { temp @ 1 } end ; Uniform delay remaining = 92 Accumulated Delay = 42 ; switch { {{ shaft1 - temp }} & 3 } movf shaft1,w movwf delay__250byte0 movf delay__temp,w subwf delay__250byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 goto switch__250block_start switch__250block251: ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Nothing changed ; do nothing : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Delay 8 cycles movlw 2 movwf delay__251byte1 delay__251delay0: decfsz delay__251byte1,f goto delay__251delay0 nop goto switch__250end switch__250block254: ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Increment : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; shaft1_direction := 0 bcf shaft1_direction__byte,shaft1_direction__bit ; Uniform delay remaining = 91 Accumulated Delay = 1 ; shaft1_low := shaft1_low + 1 incf shaft1_low,f ; Uniform delay remaining = 90 Accumulated Delay = 2 ; if { z } start ; expression=`{ z }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z__byte,z__bit ; if { z } body start ; Uniform delay remaining = 90 Accumulated Delay = 0 ; shaft1_high := shaft1_high + 1 incf shaft1_high,f ; Uniform delay remaining = 89 Accumulated Delay = 1 ; Uniform delay remaining = 89 Accumulated Delay = 1 ; if { z } body end ; if exp=`z' false skip delay=2 ; Other expression=`{ z }' delay=2 ; if { z } end ; Uniform delay remaining = 88 Accumulated Delay = 4 ; Uniform delay remaining = 88 Accumulated Delay = 4 ; Delay 4 cycles nop nop nop nop goto switch__250end switch__250block262: ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Double increment / decrement : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; if { shaft1_direction } start ; expression=`{ shaft1_direction }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 btfss shaft1_direction__byte,shaft1_direction__bit goto label264__0false label264__0true: ; if { shaft1_direction } body start ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Double increment : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; shaft1_low := shaft1_low - 2 movlw 254 addwf shaft1_low,f ; Uniform delay remaining = 90 Accumulated Delay = 2 ; if { ! c } start ; expression=`c' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 btfss c__byte,c__bit ; if { ! c } body start ; Uniform delay remaining = 90 Accumulated Delay = 0 ; shaft1_high := shaft1_high - 1 decf shaft1_high,f ; Uniform delay remaining = 89 Accumulated Delay = 1 ; Uniform delay remaining = 89 Accumulated Delay = 1 ; if { ! c } body end ; if exp=`c' true skip delay=2 ; Other expression=`c' delay=2 ; if { ! c } end ; Uniform delay remaining = 88 Accumulated Delay = 4 ; Uniform delay remaining = 88 Accumulated Delay = 4 ; if { shaft1_direction } body end goto label264__0end label264__0false: ; else body start ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Double decrement : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; shaft1_low := shaft1_low + 2 movlw 2 addwf shaft1_low,f ; Uniform delay remaining = 90 Accumulated Delay = 2 ; if { c } start ; expression=`{ c }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c__byte,c__bit ; if { c } body start ; Uniform delay remaining = 90 Accumulated Delay = 0 ; shaft1_high := shaft1_high + 1 incf shaft1_high,f ; Uniform delay remaining = 89 Accumulated Delay = 1 ; Uniform delay remaining = 89 Accumulated Delay = 1 ; if { c } body end ; if exp=`c' false skip delay=2 ; Other expression=`{ c }' delay=2 ; if { c } end ; Uniform delay remaining = 88 Accumulated Delay = 4 ; Uniform delay remaining = 88 Accumulated Delay = 4 ; else body end ; Delay 1 cycles nop ; if exp=`shaft1_direction' total delay=8 ; if exp=`shaft1_direction' generic label264__0end: ; Other expression=`{ shaft1_direction }' delay=8 ; if { shaft1_direction } end ; Uniform delay remaining = 84 Accumulated Delay = 8 ; Uniform delay remaining = 84 Accumulated Delay = 8 goto switch__250end switch__250block278: ; Uniform delay remaining = 92 Accumulated Delay = 0 ; Decrement : ; Uniform delay remaining = 92 Accumulated Delay = 0 ; shaft1_direction := 1 bsf shaft1_direction__byte,shaft1_direction__bit ; Uniform delay remaining = 91 Accumulated Delay = 1 ; if { shaft1_low = 0 } start movf shaft1_low,w ; expression=`{ shaft1_low = 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z___byte,z___bit ; if { shaft1_low = 0 } body start ; Uniform delay remaining = 91 Accumulated Delay = 0 ; shaft1_high := shaft1_high - 1 decf shaft1_high,f ; Uniform delay remaining = 90 Accumulated Delay = 1 ; Uniform delay remaining = 90 Accumulated Delay = 1 ; if { shaft1_low = 0 } body end ; if exp=` shaft1_low = 0 ' false skip delay=3 ; Other expression=`{ shaft1_low = 0 }' delay=3 ; if { shaft1_low = 0 } end ; Uniform delay remaining = 88 Accumulated Delay = 4 ; shaft1_low := shaft1_low - 1 decf shaft1_low,f ; Uniform delay remaining = 87 Accumulated Delay = 5 ; Uniform delay remaining = 87 Accumulated Delay = 5 ; Delay 3 cycles nop nop nop goto switch__250end switch__250end: ; Total switch delay = 20 exp_delay=7 case_delay=10 ; Uniform delay remaining = 72 Accumulated Delay = 62 ; shaft1 := temp movf delay__temp,w movwf shaft1 ; Uniform delay remaining = 70 Accumulated Delay = 64 ; Uniform delay remaining = 70 Accumulated Delay = 64 ; Now do range checks : ; Uniform delay remaining = 70 Accumulated Delay = 64 ; if { shaft0_high < shaft0_low_high || {{ shaft0_high = shaft0_low_high && shaft0_low < shaft0_low_low }} } start movf shaft0_low_high,w subwf shaft0_high,w ; expression=`shaft0_high < shaft0_low_high' exp_delay=2 true_delay=3 false_delay=9 true_size=1 false_size=12 btfsc c___byte,c___bit goto label290__4false label290__4true: ; Delay 7 cycles movlw 2 movwf delay__290byte6 delay__290delay5: decfsz delay__290byte6,f goto delay__290delay5 goto or290__0true label290__4false: movf shaft0_high,w subwf shaft0_low_high,w ; expression=`shaft0_high = shaft0_low_high' exp_delay=2 true_delay=4 false_delay=2 true_size=4 false_size=1 btfsc z___byte,z___bit goto label290__3true label290__3false: ; Delay 3 cycles nop nop nop goto and290__1false label290__3true: movf shaft0_low_low,w subwf shaft0_low,w ; expression=`shaft0_low < shaft0_low_low' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss c___byte,c___bit and290__1true: or290__0true: ; if { shaft0_high < shaft0_low_high || {{ shaft0_high = shaft0_low_high && shaft0_low < shaft0_low_low }} } body start ; Uniform delay remaining = 70 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 69 Accumulated Delay = 1 ; Uniform delay remaining = 69 Accumulated Delay = 1 ; if { shaft0_high < shaft0_low_high || {{ shaft0_high = shaft0_low_high && shaft0_low < shaft0_low_low }} } body end ; if exp=`shaft0_low < shaft0_low_low' false skip delay=4 ; Other expression=`shaft0_low < shaft0_low_low' delay=4 ; if exp=`shaft0_high = shaft0_low_high' total delay=9 ; if exp=`shaft0_high = shaft0_low_high' generic label290__3end: ; Other expression=`shaft0_high = shaft0_low_high' delay=9 and290__1false: and290__1end: ; if exp=`shaft0_high < shaft0_low_high' total delay=14 ; if exp=`shaft0_high < shaft0_low_high' generic label290__4end: ; Other expression=`shaft0_high < shaft0_low_high' delay=14 or290__0false: or290__0end: ; if { shaft0_high < shaft0_low_high || {{ shaft0_high = shaft0_low_high && shaft0_low < shaft0_low_low }} } end ; Uniform delay remaining = 56 Accumulated Delay = 78 ; if { shaft0_high > shaft0_high_high || {{ shaft0_high = shaft0_high_high && shaft0_low > shaft0_high_low }} } start movf shaft0_high,w subwf shaft0_high_high,w ; expression=`shaft0_high > shaft0_high_high' exp_delay=2 true_delay=3 false_delay=9 true_size=1 false_size=12 btfsc c___byte,c___bit goto label293__4false label293__4true: ; Delay 7 cycles movlw 2 movwf delay__293byte6 delay__293delay5: decfsz delay__293byte6,f goto delay__293delay5 goto or293__0true label293__4false: movf shaft0_high,w subwf shaft0_high_high,w ; expression=`shaft0_high = shaft0_high_high' exp_delay=2 true_delay=4 false_delay=2 true_size=4 false_size=1 btfsc z___byte,z___bit goto label293__3true label293__3false: ; Delay 3 cycles nop nop nop goto and293__1false label293__3true: movf shaft0_low,w subwf shaft0_high_low,w ; expression=`shaft0_low > shaft0_high_low' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss c___byte,c___bit and293__1true: or293__0true: ; if { shaft0_high > shaft0_high_high || {{ shaft0_high = shaft0_high_high && shaft0_low > shaft0_high_low }} } body start ; Uniform delay remaining = 56 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 55 Accumulated Delay = 1 ; Uniform delay remaining = 55 Accumulated Delay = 1 ; if { shaft0_high > shaft0_high_high || {{ shaft0_high = shaft0_high_high && shaft0_low > shaft0_high_low }} } body end ; if exp=`shaft0_low > shaft0_high_low' false skip delay=4 ; Other expression=`shaft0_low > shaft0_high_low' delay=4 ; if exp=`shaft0_high = shaft0_high_high' total delay=9 ; if exp=`shaft0_high = shaft0_high_high' generic label293__3end: ; Other expression=`shaft0_high = shaft0_high_high' delay=9 and293__1false: and293__1end: ; if exp=`shaft0_high > shaft0_high_high' total delay=14 ; if exp=`shaft0_high > shaft0_high_high' generic label293__4end: ; Other expression=`shaft0_high > shaft0_high_high' delay=14 or293__0false: or293__0end: ; if { shaft0_high > shaft0_high_high || {{ shaft0_high = shaft0_high_high && shaft0_low > shaft0_high_low }} } end ; Uniform delay remaining = 42 Accumulated Delay = 92 ; if { shaft1_high < shaft1_low_high || {{ shaft1_high = shaft1_low_high && shaft1_low < shaft1_low_low }} } start movf shaft1_low_high,w subwf shaft1_high,w ; expression=`shaft1_high < shaft1_low_high' exp_delay=2 true_delay=3 false_delay=9 true_size=1 false_size=12 btfsc c___byte,c___bit goto label296__4false label296__4true: ; Delay 7 cycles movlw 2 movwf delay__296byte6 delay__296delay5: decfsz delay__296byte6,f goto delay__296delay5 goto or296__0true label296__4false: movf shaft1_high,w subwf shaft1_low_high,w ; expression=`shaft1_high = shaft1_low_high' exp_delay=2 true_delay=4 false_delay=2 true_size=4 false_size=1 btfsc z___byte,z___bit goto label296__3true label296__3false: ; Delay 3 cycles nop nop nop goto and296__1false label296__3true: movf shaft1_low_low,w subwf shaft1_low,w ; expression=`shaft1_low < shaft1_low_low' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss c___byte,c___bit and296__1true: or296__0true: ; if { shaft1_high < shaft1_low_high || {{ shaft1_high = shaft1_low_high && shaft1_low < shaft1_low_low }} } body start ; Uniform delay remaining = 42 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 41 Accumulated Delay = 1 ; Uniform delay remaining = 41 Accumulated Delay = 1 ; if { shaft1_high < shaft1_low_high || {{ shaft1_high = shaft1_low_high && shaft1_low < shaft1_low_low }} } body end ; if exp=`shaft1_low < shaft1_low_low' false skip delay=4 ; Other expression=`shaft1_low < shaft1_low_low' delay=4 ; if exp=`shaft1_high = shaft1_low_high' total delay=9 ; if exp=`shaft1_high = shaft1_low_high' generic label296__3end: ; Other expression=`shaft1_high = shaft1_low_high' delay=9 and296__1false: and296__1end: ; if exp=`shaft1_high < shaft1_low_high' total delay=14 ; if exp=`shaft1_high < shaft1_low_high' generic label296__4end: ; Other expression=`shaft1_high < shaft1_low_high' delay=14 or296__0false: or296__0end: ; if { shaft1_high < shaft1_low_high || {{ shaft1_high = shaft1_low_high && shaft1_low < shaft1_low_low }} } end ; Uniform delay remaining = 28 Accumulated Delay = 106 ; if { shaft1_high > shaft1_high_high || {{ shaft1_high = shaft1_high_high && shaft1_low > shaft1_high_low }} } start movf shaft1_high,w subwf shaft1_high_high,w ; expression=`shaft1_high > shaft1_high_high' exp_delay=2 true_delay=3 false_delay=9 true_size=1 false_size=12 btfsc c___byte,c___bit goto label299__4false label299__4true: ; Delay 7 cycles movlw 2 movwf delay__299byte6 delay__299delay5: decfsz delay__299byte6,f goto delay__299delay5 goto or299__0true label299__4false: movf shaft1_high,w subwf shaft1_high_high,w ; expression=`shaft1_high = shaft1_high_high' exp_delay=2 true_delay=4 false_delay=2 true_size=4 false_size=1 btfsc z___byte,z___bit goto label299__3true label299__3false: ; Delay 3 cycles nop nop nop goto and299__1false label299__3true: movf shaft1_low,w subwf shaft1_high_low,w ; expression=`shaft1_low > shaft1_high_low' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss c___byte,c___bit and299__1true: or299__0true: ; if { shaft1_high > shaft1_high_high || {{ shaft1_high = shaft1_high_high && shaft1_low > shaft1_high_low }} } body start ; Uniform delay remaining = 28 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 27 Accumulated Delay = 1 ; Uniform delay remaining = 27 Accumulated Delay = 1 ; if { shaft1_high > shaft1_high_high || {{ shaft1_high = shaft1_high_high && shaft1_low > shaft1_high_low }} } body end ; if exp=`shaft1_low > shaft1_high_low' false skip delay=4 ; Other expression=`shaft1_low > shaft1_high_low' delay=4 ; if exp=`shaft1_high = shaft1_high_high' total delay=9 ; if exp=`shaft1_high = shaft1_high_high' generic label299__3end: ; Other expression=`shaft1_high = shaft1_high_high' delay=9 and299__1false: and299__1end: ; if exp=`shaft1_high > shaft1_high_high' total delay=14 ; if exp=`shaft1_high > shaft1_high_high' generic label299__4end: ; Other expression=`shaft1_high > shaft1_high_high' delay=14 or299__0false: or299__0end: ; if { shaft1_high > shaft1_high_high || {{ shaft1_high = shaft1_high_high && shaft1_low > shaft1_high_low }} } end ; Uniform delay remaining = 14 Accumulated Delay = 120 ; Uniform delay remaining = 14 Accumulated Delay = 120 ; Perform any interrupt : ; Uniform delay remaining = 14 Accumulated Delay = 120 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label304__2true label304__2false: ; Delay 2 cycles nop nop goto and304__0false label304__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label304__1false label304__1true: and304__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 14 Accumulated Delay = 0 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 13 Accumulated Delay = 1 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 12 Accumulated Delay = 2 ; Uniform delay remaining = 12 Accumulated Delay = 2 ; if { interrupt_pending && interrupt_enable } body end goto label304__1end label304__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label304__1end: ; Other expression=`interrupt_enable' delay=6 ; if exp=`interrupt_pending' total delay=9 ; if exp=`interrupt_pending' generic label304__2end: ; Other expression=`interrupt_pending' delay=9 and304__0false: and304__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 5 Accumulated Delay = 129 ; Uniform delay remaining = 5 Accumulated Delay = 129 ; Soak up remaining 5 cycles ; Delay 5 cycles nop nop nop nop nop ; procedure delay end retlw 0 ; optimize 1 ; comment {The main routine can span the 256 byte boundary :} ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; procedure main start switch__352block_start: addwf pcl___register,f goto switch__352block353 goto switch__352block358 goto switch__352block363 goto switch__352block367 goto switch__352block371 goto switch__352block377 goto switch__352block383 goto switch__352block387 switch__352block_end: ; switch_check 352 switch__352block_start switch__352block_end switch__395block_start: addwf pcl___register,f goto switch__395block396 goto switch__395block403 goto switch__395block410 goto switch__395block417 goto switch__395block424 goto switch__395block429 goto switch__395default434 goto switch__395default434 switch__395block_end: ; switch_check 395 switch__395block_start switch__395block_end switch__441block_start: addwf pcl___register,f goto switch__441block442 goto switch__441block448 goto switch__441block454 goto switch__441block460 goto switch__441block466 goto switch__441block471 goto switch__441block476 goto switch__441block481 switch__441block_end: ; switch_check 441 switch__441block_start switch__441block_end switch__349block_start: addwf pcl___register,f goto switch__349block350 goto switch__349block393 goto switch__349block439 goto switch__349default488 goto switch__349default488 goto switch__349default488 goto switch__349default488 goto switch__349default488 switch__349block_end: ; switch_check 349 switch__349block_start switch__349block_end switch__516block_start: addwf pcl___register,f goto switch__516block517 goto switch__516block517 goto switch__516block522 goto switch__516block526 switch__516block_end: ; switch_check 516 switch__516block_start switch__516block_end switch__534block_start: addwf pcl___register,f goto switch__534block535 goto switch__534block541 goto switch__534block547 goto switch__534block551 goto switch__534block555 goto switch__534block566 goto switch__534block570 goto switch__534block575 switch__534block_end: ; switch_check 534 switch__534block_start switch__534block_end switch__499block_start: addwf pcl___register,f goto switch__499end goto switch__499end goto switch__499end goto switch__499end goto switch__499end goto switch__499block500 goto switch__499block514 goto switch__499block532 switch__499block_end: ; switch_check 499 switch__499block_start switch__499block_end switch__346block_start: addwf pcl___register,f goto switch__346block347 goto switch__346block493 goto switch__346block493 goto switch__346block497 switch__346block_end: ; switch_check 346 switch__346block_start switch__346block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+6 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+7 main__total__bytes equ 7 main__346byte0 equ main__bytes__base+6 main__499byte0 equ main__bytes__base+6 main__502byte0 equ main__bytes__base+6 main__349byte0 equ main__bytes__base+6 ; arguments_none main__command equ main__bytes__base+0 main__glitch equ main__bytes__base+1 main__id_index equ main__bytes__base+2 main__high equ main__bytes__base+3 main__index equ main__bytes__base+4 main__result equ main__bytes__base+5 ; Initialize everything : ; shaft0 := 0 clrf shaft0 ; shaft0_direction := 0 ; Switch from register bank 1 to register bank 0 (which contains shaft0_direction__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf shaft0_direction__byte,shaft0_direction__bit ; shaft0_high := 0 clrf shaft0_high ; shaft0_low := 0 clrf shaft0_low ; shaft1 := 0 clrf shaft1 ; shaft1_high := 0 clrf shaft1_high ; shaft1_low := 0 clrf shaft1_low ; shaft1_direction := 0 bcf shaft1_direction__byte,shaft1_direction__bit ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; id_index := 0 clrf main__id_index ; Loop waiting for commands : ; loop_forever ... start main__341loop__forever: ; Get a command byte : ; command := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__command ; Dispatch on command : ; switch { command >> 6 } swapf main__command,w movwf main__346byte0 rrf main__346byte0,f rrf main__346byte0,w andlw 3 ; case 0 ; case 1 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__346block_start switch__346block347: ; Command = 00 xx xxxx : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__349byte0 rrf main__349byte0,f rrf main__349byte0,w andlw 7 ; case 0 ; case 1 ; case 2 goto switch__349block_start switch__349block350: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__352block_start switch__352block353: ; Read Shaft 0 < Command = 0000 0000 > : ; call send_byte {{ shaft0_high }} movf shaft0_high,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft0_low }} movf shaft0_low,w movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block358: ; Read Shaft 1 < Command = 0000 0001 > : ; call send_byte {{ shaft1_high }} movf shaft1_high,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft1_low }} movf shaft1_low,w movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block363: ; Read Shaft Low 0 < Command = 0000 0010 > : ; call send_byte {{ shaft0_low }} movf shaft0_low,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block367: ; Read Shaft Low 1 < Command = 0000 0011 > : ; call send_byte {{ shaft1_low }} movf shaft1_low,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block371: ; Set Shaft 0 < Command = 0000 0100 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft0_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf shaft0_low ; shaft0_high := high movf main__high,w movwf shaft0_high ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block377: ; Set Shaft 1 < Command = 0000 0101 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft1_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf shaft1_low ; shaft1_high := high movf main__high,w movwf shaft1_high ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block383: ; Set Shaft Low 0 < Command = 0000 0110 > : ; shaft0_low := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf shaft0_low ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__352end switch__352block387: ; Set Shaft Low 1 < Command = 0000 0111 > : ; shaft1_low := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf shaft1_low ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit switch__352end: goto switch__349end switch__349block393: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 goto switch__395block_start switch__395block396: ; Increment Shaft 0 < Command = 0000 1000 > : ; shaft0_low := shaft0_low + 1 incf shaft0_low,f ; if { z } start ; expression=`{ z }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z__byte,z__bit ; if { z } body start ; shaft0_high := shaft0_high + 1 incf shaft0_high,f ; if { z } body end ; if exp=`z' false skip delay=2 ; Other expression=`{ z }' delay=2 ; if { z } end goto switch__395end switch__395block403: ; Increment Shaft 1 < Command = 0000 1001 > : ; shaft1_low := shaft1_low + 1 incf shaft1_low,f ; if { z } start ; expression=`{ z }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z__byte,z__bit ; if { z } body start ; shaft1_high := shaft1_high + 1 incf shaft1_high,f ; if { z } body end ; if exp=`z' false skip delay=2 ; Other expression=`{ z }' delay=2 ; if { z } end goto switch__395end switch__395block410: ; Decrement Shaft 0 < Command = 0000 1010 > : ; if { shaft0_low = 0 } start movf shaft0_low,w ; expression=`{ shaft0_low = 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z___byte,z___bit ; if { shaft0_low = 0 } body start ; shaft0_high := shaft0_high - 1 decf shaft0_high,f ; if { shaft0_low = 0 } body end ; if exp=` shaft0_low = 0 ' false skip delay=3 ; Other expression=`{ shaft0_low = 0 }' delay=3 ; if { shaft0_low = 0 } end ; shaft0_low := shaft0_low - 1 decf shaft0_low,f goto switch__395end switch__395block417: ; Decrement Shaft 1 < Command = 0000 1011 > : ; if { shaft1_low = 0 } start movf shaft1_low,w ; expression=`{ shaft1_low = 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc z___byte,z___bit ; if { shaft1_low = 0 } body start ; shaft1_high := shaft1_high - 1 decf shaft1_high,f ; if { shaft1_low = 0 } body end ; if exp=` shaft1_low = 0 ' false skip delay=3 ; Other expression=`{ shaft1_low = 0 }' delay=3 ; if { shaft1_low = 0 } end ; shaft1_low := shaft1_low - 1 decf shaft1_low,f goto switch__395end switch__395block424: ; Clear Shaft 0 < Command = 0000 1100 > : ; shaft0_low := 0 clrf shaft0_low ; shaft0_high := 0 clrf shaft0_high goto switch__395end switch__395block429: ; Clear Shaft 1 < Command = 0000 1101 > : ; shaft1_low := 0 clrf shaft1_low ; shaft1_high := 0 clrf shaft1_high goto switch__395end switch__395default434: ; Command = 0000 111 x : switch__395end: goto switch__349end switch__349block439: ; Command = 0001 0 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__441block_start switch__441block442: ; Set High Threshold 0 < Command = 0001 0000 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft0_high_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w ; Switch from register bank 1 to register bank 0 (which contains shaft0_high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf shaft0_high_low ; shaft0_high_high := high ; Switch from register bank 0 to register bank 1 (which contains main__high) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf main__high,w ; Switch from register bank 1 to register bank 0 (which contains shaft0_high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf shaft0_high_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block448: ; Set High Threshold 1 < Command = 0001 0001 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft1_high_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w ; Switch from register bank 1 to register bank 0 (which contains shaft1_high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf shaft1_high_low ; shaft1_high_high := high ; Switch from register bank 0 to register bank 1 (which contains main__high) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf main__high,w ; Switch from register bank 1 to register bank 0 (which contains shaft1_high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf shaft1_high_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block454: ; Set Low Threshold 0 < Command = 0001 0010 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft0_low_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf shaft0_low_low ; shaft0_low_high := high movf main__high,w movwf shaft0_low_high ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block460: ; Set Low Threshold 1 < Command = 0001 0011 > : ; high := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__high ; shaft1_low_low := get_byte {{ }} call get_byte movf get_byte__0return__byte,w ; Switch from register bank 1 to register bank 0 (which contains shaft1_low_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf shaft1_low_low ; shaft1_low_high := high ; Switch from register bank 0 to register bank 1 (which contains main__high) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf main__high,w movwf shaft1_low_high ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block466: ; Read High Threshold 0 < Command = 0001 0100 > : ; call send_byte {{ shaft0_high_high }} ; Switch from register bank 1 to register bank 0 (which contains shaft0_high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf shaft0_high_high,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft0_high_low }} ; Switch from register bank 1 to register bank 0 (which contains shaft0_high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf shaft0_high_low,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block471: ; Read High Threshold 1 < Command = 0001 0101 > : ; call send_byte {{ shaft1_high_high }} ; Switch from register bank 1 to register bank 0 (which contains shaft1_high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf shaft1_high_high,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft1_high_low }} ; Switch from register bank 1 to register bank 0 (which contains shaft1_high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf shaft1_high_low,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block476: ; Read Low Threshold 0 < Command = 0001 0110 > : ; call send_byte {{ shaft0_low_high }} movf shaft0_low_high,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft0_low_low }} movf shaft0_low_low,w movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__441end switch__441block481: ; Read Low Threshold 1 < Command = 0001 0111 > : ; call send_byte {{ shaft1_low_high }} movf shaft1_low_high,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; call send_byte {{ shaft1_low_low }} ; Switch from register bank 1 to register bank 0 (which contains shaft1_low_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf shaft1_low_low,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit switch__441end: goto switch__349end switch__349default488: ; Command = 001 x xxxx : switch__349end: goto switch__346end switch__346block493: ; Command = 01 xx xxxx or10xx xxxx : ; Do nothing : goto switch__346end switch__346block497: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__499byte0 rrf main__499byte0,f rrf main__499byte0,w andlw 7 ; case 5 ; case 6 ; case 7 goto switch__499block_start switch__499block500: ; Command = 1110 1 xxx : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__502byte0 movlw 7 subwf main__502byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 btfss z___byte,z___bit goto label502__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits < Command = 1110 1111 > : ; result := 0 clrf main__result ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_enable__byte,interrupt_enable__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label505__0end ; if { interrupt_enable } body start ; result := result | 2 movlw 2 iorwf main__result,f ; if { interrupt_enable } body end label505__0end: ; if exp=`interrupt_enable' empty false ; Other expression=`{ interrupt_enable }' delay=-1 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_pending__byte,interrupt_pending__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label508__0end ; if { interrupt_pending } body start ; result := result | 1 movlw 1 iorwf main__result,f ; if { interrupt_pending } body end label508__0end: ; if exp=`interrupt_pending' empty false ; Other expression=`{ interrupt_pending }' delay=-1 ; if { interrupt_pending } end ; call send_byte {{ result }} movf main__result,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { {{ command & 7 }} = 7 } body end ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label502__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__499end switch__499block514: ; Shared Interrupt commands . ; switch { {{ command >> 1 }} & 3 } bcf c___byte,c___bit rrf main__command,w andlw 3 ; case 0 1 ; case 2 ; case 3 goto switch__516block_start switch__516block517: ; Set Interrupt Bits < Command = 1110 00 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__519select0 equ main__command+0 main__command__519select0__byte equ main__command+0 main__command__519select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__519select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__519select0__byte,main__command__519select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__520select0 equ main__command+0 main__command__520select0__byte equ main__command+0 main__command__520select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__520select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__520select0__byte,main__command__520select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__516end switch__516block522: ; Set Interrupt Pending < Command = 1110 010 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__524select0 equ main__command+0 main__command__524select0__byte equ main__command+0 main__command__524select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__524select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__524select0__byte,main__command__524select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__516end switch__516block526: ; Set Interrupt Enable < Command = 1110 011 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__528select0 equ main__command+0 main__command__528select0__byte equ main__command+0 main__command__528select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__528select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__528select0__byte,main__command__528select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__516end: goto switch__499end switch__499block532: ; Shared commands < Command = 1111 1 ccc > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__534block_start switch__534block535: ; Clock Decrement < Command = 1111 1000 > : ; if < osccal != 0 > < ; osccal := osccal - osccal_unit movlw 240 addwf osccal,f ; > goto switch__534end switch__534block541: ; Clock Increment < Command = 1111 1001 > : ; if < osccal + osccal_unit != 0 > < ; osccal := osccal + osccal_unit movlw 16 addwf osccal,f ; > goto switch__534end switch__534block547: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__534end switch__534block551: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__534end switch__534block555: ; ID Next < Command = 1111 1100 > : ; if { id_index >= id . size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end ; call send_byte {{ id ~~ {{ id_index }} }} incf main__id_index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; id_index := id_index + 1 incf main__id_index,f ; if { id_index >= id . size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end goto switch__534end switch__534block566: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf main__id_index goto switch__534end switch__534block570: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf main__glitch,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; glitch := 0 clrf main__glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__534end switch__534block575: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf main__glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf main__glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__534end: switch__499end: switch__346end: goto main__341loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 17 bytes of 25 available bytes ; Register bank 1 used 13 bytes of 16 available bytes end