1 radix dec 2 0008 global__variables__bank0 equ 8 3 0030 global__variables__bank1 equ 48 4 0050 global__variables__bank2 equ 80 5 0070 global__variables__bank3 equ 112 6 001f global__bit__variables__bank0 equ 31 7 003e global__bit__variables__bank1 equ 62 8 0050 global__bit__variables__bank2 equ 80 9 0070 global__bit__variables__bank3 equ 112 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 17 0004 rp0___byte equ 4 18 0005 rp0___bit equ 5 19 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 20 0004 rp1___byte equ 4 21 0006 rp1___bit equ 6 22 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 23 0003 pa0___byte equ 3 24 0005 pa0___bit equ 5 25 0004 fsr___register equ 4 26 org 0 27 start: 28 ; Use oscillator calibration value already in register W 29 000 025 movwf 5 30 ; Initialize TRIS registers 31 001 ccc movlw 204 32 002 006 tris 6 33 003 cf1 movlw 241 34 004 007 tris 7 35 ; Switch from register bank 0 to register bank 1 36 005 5a4 bsf rp0___byte,rp0___bit 37 ; Register bank is now 1 38 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 39 006 5a3 bsf pa0___byte,pa0___bit 40 007 a3b goto main 41 ; comment ############################################################################# 42 ; comment {} 43 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 44 ; comment {All rights reserved .} 45 ; comment {} 46 ; comment {Permission to use , copy , modify , distribute , and sell this software} 47 ; comment {for any purpose is hereby granted without fee provided that the above} 48 ; comment {copyright notice and this permission are retained . The author makes} 49 ; comment {no representations about the suitability of this software for any purpose .} 50 ; comment {It is provided { as is } without express or implied warranty .} 51 ; comment {} 52 ; comment {This is the code that implements the LED4 RoboBrick . Basically} 53 ; comment {it just waits for commands that come in at 2400 baud and responds} 54 ; comment {to them . See :} 55 ; comment {} 56 ; comment {http : / / web . gramlich . net / projects / robobricks / thresh4 / index . html} 57 ; comment {} 58 ; comment {for more details .} 59 ; comment {} 60 ; comment ############################################################################# 61 ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock 62 ; 4052=0xfd4 4095=0xfff 63 __config 4052 64 0fff configuration___address equ 4095 65 ; comment {Define processor constants :} 66 ; constant clock_rate 4000000 67 3d0900 clock_rate equ 4000000 68 ; constant clocks_per_instruction 4 69 0004 clocks_per_instruction equ 4 70 ; constant instruction_rate clock_rate / clocks_per_instruction 71 f4240 instruction_rate equ 1000000 72 ; comment {Define serial communication control constants :} 73 ; constant baud_rate 2400 74 0960 baud_rate equ 2400 75 ; constant instructions_per_bit instruction_rate / baud_rate 76 01a0 instructions_per_bit equ 416 77 ; constant delays_per_bit 3 78 0003 delays_per_bit equ 3 79 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 80 008a instructions_per_delay equ 138 81 ; constant extra_instructions_per_bit 9 82 0009 extra_instructions_per_bit equ 9 83 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 84 0003 extra_instructions_per_delay equ 3 85 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 86 0087 delay_instructions equ 135 87 ; comment {Register definitions :} 88 ; comment {TMR0 register :} 89 0001 tmr0 equ 1 90 ; comment {STATUS register :} 91 0003 status equ 3 92 ; bind c status @ 0 93 0003 c equ status+0 94 0003 c__byte equ status+0 95 0000 c__bit equ 0 96 ; bind z status @ 2 97 0003 z equ status+0 98 0003 z__byte equ status+0 99 0002 z__bit equ 2 100 ; comment {OSCCAL register :} 101 0005 osccal equ 5 102 ; constant osccal_unit 4 103 0004 osccal_unit equ 4 104 ; comment {On the 505 , the OPTION register is only setable via the option instrucition .} 105 ; constant rbwu_bit 7 106 0007 rbwu_bit equ 7 107 ; constant rbpu_bit 6 108 0006 rbpu_bit equ 6 109 ; constant t0cs_bit 5 110 0005 t0cs_bit equ 5 111 ; constant t0se_bit 4 112 0004 t0se_bit equ 4 113 ; constant psa_bit 3 114 0003 psa_bit equ 3 115 ; constant ps2_bit 2 116 0002 ps2_bit equ 2 117 ; constant ps1_bit 1 118 0001 ps1_bit equ 1 119 ; constant ps0_bit 0 120 0000 ps0_bit equ 0 121 ; constant rbuw_mask {{ 1 << rbwu_bit }} 122 0080 rbuw_mask equ 128 123 ; constant rbpu_mask {{ 1 << rbpu_bit }} 124 0040 rbpu_mask equ 64 125 ; constant t0cs_mask {{ 1 << t0cs_bit }} 126 0020 t0cs_mask equ 32 127 ; constant t0se_mask {{ 1 << t0se_bit }} 128 0010 t0se_mask equ 16 129 ; comment {Disable Wake - up and pull - ups {;} set timer to internal {;} edge_source to raising :} 130 ; constant option_mask rbuw_mask | rbpu_mask 131 00c0 option_mask equ 192 132 ; comment {Define port B bit assignments :} 133 ; constant serial_in_bit 0 134 0000 serial_in_bit equ 0 135 ; constant serial_out_bit 1 136 0001 serial_out_bit equ 1 137 ; constant motor0e_bit 2 138 0002 motor0e_bit equ 2 139 ; constant motor1e_bit 3 140 0003 motor1e_bit equ 3 141 ; comment {Define port C bit assignments :} 142 ; constant motor0a_bit 0 143 0000 motor0a_bit equ 0 144 ; constant motor0b_bit 1 145 0001 motor0b_bit equ 1 146 ; constant motor1a_bit 4 147 0004 motor1a_bit equ 4 148 ; constant motor1b_bit 5 149 0005 motor1b_bit equ 5 150 ; comment {Define the ports {;}} 151 0006 portb equ 6 152 0007 portc equ 7 153 0006 motor0a__byte equ 6 154 0000 motor0a__bit equ 0 155 0006 motor0b__byte equ 6 156 0001 motor0b__bit equ 1 157 0006 motor1a__byte equ 6 158 0004 motor1a__bit equ 4 159 0006 motor1b__byte equ 6 160 0005 motor1b__bit equ 5 161 0007 serial_in__byte equ 7 162 0000 serial_in__bit equ 0 163 0007 serial_out__byte equ 7 164 0001 serial_out__bit equ 1 165 0007 motor0e__byte equ 7 166 0002 motor0e__bit equ 2 167 0007 motor1e__byte equ 7 168 0003 motor1e__bit equ 3 169 ; comment {Define some masks :} 170 ; constant motor0a_mask {{ 1 << motor0a_bit }} 171 0001 motor0a_mask equ 1 172 ; constant motor0e_mask {{ 1 << motor0e_bit }} 173 0004 motor0e_mask equ 4 174 ; constant motor0b_mask {{ 1 << motor0b_bit }} 175 0002 motor0b_mask equ 2 176 ; constant motor1a_mask {{ 1 << motor1a_bit }} 177 0010 motor1a_mask equ 16 178 ; constant motor1e_mask {{ 1 << motor1e_bit }} 179 0008 motor1e_mask equ 8 180 ; constant motor1b_mask {{ 1 << motor1b_bit }} 181 0020 motor1b_mask equ 32 182 ; constant serial_in_mask {{ 1 << serial_in_bit }} 183 0001 serial_in_mask equ 1 184 ; constant serial_out_mask {{ 1 << serial_out_bit }} 185 0002 serial_out_mask equ 2 186 ; comment {Define duty cycle and motor on / off masks :} 187 0008 actual_speed0 equ global__variables__bank0+0 188 0009 actual_speed1 equ global__variables__bank0+1 189 000a motor0_off equ global__variables__bank0+2 190 000b motor0_on equ global__variables__bank0+3 191 000c motor1_off equ global__variables__bank0+4 192 000d motor1_on equ global__variables__bank0+5 193 ; comment {Ramp variables :} 194 000e desired_speed0 equ global__variables__bank0+6 195 000f desired_speed1 equ global__variables__bank0+7 196 0010 ramp0 equ global__variables__bank0+8 197 0011 ramp1 equ global__variables__bank0+9 198 0012 ramp0_delay equ global__variables__bank0+10 199 0013 ramp1_delay equ global__variables__bank0+11 200 0014 ramp0_offset equ global__variables__bank0+12 201 0015 ramp1_offset equ global__variables__bank0+13 202 ; comment {Fail safe variables :} 203 0016 fail_safe equ global__variables__bank0+14 204 0017 fail_safe_errors equ global__variables__bank0+15 205 0018 fail_safe_high_counter equ global__variables__bank0+16 206 0019 fail_safe_low_counter equ global__variables__bank0+17 207 001a mask equ global__variables__bank0+18 208 001b motor0 equ global__variables__bank0+19 209 001c motor1 equ global__variables__bank0+20 210 ; comment {Mode < pulsed vs . continuous > bits :} 211 001f motor0_mode equ global__bit__variables__bank0+0 212 001f motor0_mode__byte equ global__bit__variables__bank0+0 213 0000 motor0_mode__bit equ 0 214 001f motor1_mode equ global__bit__variables__bank0+0 215 001f motor1_mode__byte equ global__bit__variables__bank0+0 216 0001 motor1_mode__bit equ 1 217 001f motor0_direction equ global__bit__variables__bank0+0 218 001f motor0_direction__byte equ global__bit__variables__bank0+0 219 0002 motor0_direction__bit equ 2 220 001f motor1_direction equ global__bit__variables__bank0+0 221 001f motor1_direction__byte equ global__bit__variables__bank0+0 222 0003 motor1_direction__bit equ 3 223 ; bank 1 224 ; Default register bank is now 1 225 ; comment {Shared command registers and option :} 226 0030 glitch equ global__variables__bank1+0 227 0031 id_index equ global__variables__bank1+1 228 0032 option equ global__variables__bank1+2 229 0033 spare equ global__variables__bank1+3 230 ; string_constants Start 231 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 232 008 4a3 bcf pa0___byte,pa0___bit 233 string___fetch: 234 009 022 movwf pcl___register 235 ; id = 1 , 0 , 14 , 2 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'Motor2C' , 15 , 0s'Gramlich&Benson' 236 0000 id___string equ 0 237 id: 238 00a 1e2 addwf pcl___register,f 239 ; Length = 48 240 00b 830 retlw 48 241 ; 1 242 00c 801 retlw 1 243 ; 0 244 00d 800 retlw 0 245 ; 14 246 00e 80e retlw 14 247 ; 2 248 00f 802 retlw 2 249 ; 0 250 010 800 retlw 0 251 ; 0 252 011 800 retlw 0 253 ; 0 254 012 800 retlw 0 255 ; 0 256 013 800 retlw 0 257 ; 0r'16' 258 014 80e retlw 14 ; random number 259 015 831 retlw 49 ; random number 260 016 8d8 retlw 216 ; random number 261 017 86b retlw 107 ; random number 262 018 85d retlw 93 ; random number 263 019 89e retlw 158 ; random number 264 01a 839 retlw 57 ; random number 265 01b 89f retlw 159 ; random number 266 01c 891 retlw 145 ; random number 267 01d 80e retlw 14 ; random number 268 01e 895 retlw 149 ; random number 269 01f 884 retlw 132 ; random number 270 020 804 retlw 4 ; random number 271 021 8e6 retlw 230 ; random number 272 022 864 retlw 100 ; random number 273 023 810 retlw 16 ; random number 274 ; 7 275 024 807 retlw 7 276 ; `Motor2C' 277 025 84d retlw 77 278 026 86f retlw 111 279 027 874 retlw 116 280 028 86f retlw 111 281 029 872 retlw 114 282 02a 832 retlw 50 283 02b 843 retlw 67 284 ; 15 285 02c 80f retlw 15 286 ; `Gramlich&Benson' 287 02d 847 retlw 71 288 02e 872 retlw 114 289 02f 861 retlw 97 290 030 86d retlw 109 291 031 86c retlw 108 292 032 869 retlw 105 293 033 863 retlw 99 294 034 868 retlw 104 295 035 826 retlw 38 296 036 842 retlw 66 297 037 865 retlw 101 298 038 86e retlw 110 299 039 873 retlw 115 300 03a 86f retlw 111 301 03b 86e retlw 110 302 ; string__constants End 303 ; comment {For now put all the smaller routines first so that they can live} 304 ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} 305 ; comment {can only call routines that are within the first 256 bytes < i . e .} 306 ; comment {the first half > of the code page .} 307 ; bank 1 308 ; Default register bank is now 1 309 ; comment {Globals :} 310 003e receiving equ global__bit__variables__bank1+0 311 003e receiving__byte equ global__bit__variables__bank1+0 312 0000 receiving__bit equ 0 313 314 ; procedure get_byte start 315 get_byte: 316 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 317 ; Procedure must be called with PCLATH set to code bank 0 318 0034 get_byte__variables__base equ global__variables__bank1+4 319 0034 get_byte__bytes__base equ get_byte__variables__base+0 320 0037 get_byte__bits__base equ get_byte__variables__base+3 321 0004 get_byte__total__bytes equ 4 322 ; arguments_none 323 0034 get_byte__0return__byte equ get_byte__bytes__base+0 324 ; Wait for a character and return it . 325 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 326 ; way the next call to get_byte < > will sychronize on the start 327 ; bit instead of possibly starting a little later . 328 0035 get_byte__count equ get_byte__bytes__base+1 329 0036 get_byte__char equ get_byte__bytes__base+2 330 ; Wait for start bit : 331 ; receiving := 1 332 03c 51e bsf receiving__byte,receiving__bit 333 ; `while serial_in ...' start 334 get_byte__173while__continue: 335 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 336 03d 707 btfss serial_in__byte,serial_in__bit 337 03e a43 goto get_byte__173while__break 338 ; call delay {{ }} 339 ; Switch from register bank 1 to register bank 0 340 03f 4a4 bcf rp0___byte,rp0___bit 341 ; Register bank is now 0 342 040 9ec call delay 343 ; Switch from register bank 0 to register bank 1 344 041 5a4 bsf rp0___byte,rp0___bit 345 ; Register bank is now 1 346 042 a3d goto get_byte__173while__continue 347 ; if exp=`serial_in' false goto 348 ; Other expression=`serial_in' delay=-1 349 get_byte__173while__break: 350 ; `while serial_in ...' end 351 ; Clear any interrupt being sent : 352 ; serial_out := 1 353 043 527 bsf serial_out__byte,serial_out__bit 354 ; Skip over start bit : 355 ; call delay {{ }} 356 ; Switch from register bank 1 to register bank 0 357 044 4a4 bcf rp0___byte,rp0___bit 358 ; Register bank is now 0 359 045 9ec call delay 360 ; call delay {{ }} 361 046 9ec call delay 362 ; call delay {{ }} 363 047 9ec call delay 364 ; Sample in the middle third of each data bit : 365 ; char := 0 366 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 367 048 5a4 bsf rp0___byte,rp0___bit 368 ; Register bank is now 1 369 049 076 clrf get_byte__char 370 ; `count_down count 8 ...' start 371 04a c08 movlw 8 372 04b 035 movwf get_byte__count 373 get_byte__187_loop: 374 ; call delay {{ }} 375 ; Switch from register bank 1 to register bank 0 376 04c 4a4 bcf rp0___byte,rp0___bit 377 ; Register bank is now 0 378 04d 9ec call delay 379 ; 2 cycles : 380 ; char := char >> 1 381 04e 403 bcf c___byte,c___bit 382 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 383 04f 5a4 bsf rp0___byte,rp0___bit 384 ; Register bank is now 1 385 050 336 rrf get_byte__char,f 386 ; 2 cycles : 387 ; if { serial_in } start 388 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 389 051 607 btfsc serial_in__byte,serial_in__bit 390 ; if { serial_in } body start 391 ; char @ 7 := 1 392 ; Select char @ 7 393 0036 get_byte__char__193select0 equ get_byte__char+0 394 0036 get_byte__char__193select0__byte equ get_byte__char+0 395 0007 get_byte__char__193select0__bit equ 7 396 052 5f6 bsf get_byte__char__193select0__byte,get_byte__char__193select0__bit 397 ; if { serial_in } body end 398 ; if exp=`serial_in' false skip delay=2 399 ; Other expression=`{ serial_in }' delay=2 400 ; if { serial_in } end 401 ; call delay {{ }} 402 ; Switch from register bank 1 to register bank 0 403 053 4a4 bcf rp0___byte,rp0___bit 404 ; Register bank is now 0 405 054 9ec call delay 406 ; call delay {{ }} 407 055 9ec call delay 408 ; 3 cycles at end of loop for test and branch : 409 ; 2 + 2 + 3 = 7 410 ; nop extra_instructions_per_bit - 7 411 ; Delay 2 cycles 412 056 000 nop 413 057 000 nop 414 ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) 415 058 5a4 bsf rp0___byte,rp0___bit 416 ; Register bank is now 1 417 059 2f5 decfsz get_byte__count,f 418 05a a4c goto get_byte__187_loop 419 get_byte__187_done: 420 ; `count_down count 8 ...' end 421 ; Skip over 2 / 3 ' s of stop bit : 422 ; call delay {{ }} 423 ; Switch from register bank 1 to register bank 0 424 05b 4a4 bcf rp0___byte,rp0___bit 425 ; Register bank is now 0 426 05c 9ec call delay 427 ; call delay {{ }} 428 05d 9ec call delay 429 ; return char 430 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 431 05e 5a4 bsf rp0___byte,rp0___bit 432 ; Register bank is now 1 433 05f 216 movf get_byte__char,w 434 060 034 movwf get_byte__0return__byte 435 061 800 retlw 0 436 ; procedure get_byte end 437 438 ; procedure send_byte start 439 send_byte: 440 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 441 ; Procedure must be called with PCLATH set to code bank 0 442 0038 send_byte__variables__base equ global__variables__bank1+8 443 0038 send_byte__bytes__base equ send_byte__variables__base+0 444 003a send_byte__bits__base equ send_byte__variables__base+2 445 0002 send_byte__total__bytes equ 2 446 0038 send_byte__char equ send_byte__bytes__base+0 447 ; Send < char > to < tx > : 448 0039 send_byte__count equ send_byte__bytes__base+1 449 ; < receiving > will be 1 if the last get / put routine was a get . 450 ; Before we start transmitting a response back , we want to ensure 451 ; that there has been enough time to turn the line line around . 452 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 453 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 454 ; for good measure . Technically , the second call to delay < > 455 ; is not really needed . 456 ; if { receiving } start 457 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 458 062 71e btfss receiving__byte,receiving__bit 459 063 a69 goto label224__0end 460 ; if { receiving } body start 461 ; receiving := 0 462 064 41e bcf receiving__byte,receiving__bit 463 ; call delay {{ }} 464 ; Switch from register bank 1 to register bank 0 465 065 4a4 bcf rp0___byte,rp0___bit 466 ; Register bank is now 0 467 066 9ec call delay 468 ; call delay {{ }} 469 067 9ec call delay 470 ; if { receiving } body end 471 ; Switch from register bank 0 to register bank 1 472 068 5a4 bsf rp0___byte,rp0___bit 473 ; Register bank is now 1 474 label224__0end: 475 ; if exp=`receiving' empty false 476 ; Other expression=`{ receiving }' delay=-1 477 ; if { receiving } end 478 ; Send the start bit : 479 ; serial_out := 0 480 069 427 bcf serial_out__byte,serial_out__bit 481 ; call delay {{ }} 482 ; Switch from register bank 1 to register bank 0 483 06a 4a4 bcf rp0___byte,rp0___bit 484 ; Register bank is now 0 485 06b 9ec call delay 486 ; call delay {{ }} 487 06c 9ec call delay 488 ; call delay {{ }} 489 06d 9ec call delay 490 ; Send the data : 491 ; `count_down count 8 ...' start 492 06e c08 movlw 8 493 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 494 06f 5a4 bsf rp0___byte,rp0___bit 495 ; Register bank is now 1 496 070 039 movwf send_byte__count 497 send_byte__237_loop: 498 ; 4 cycles : 499 ; serial_out := char @ 0 500 ; Alias variable for select char @ 0 501 0038 send_byte__char__239select0 equ send_byte__char+0 502 0038 send_byte__char__239select0__byte equ send_byte__char+0 503 0000 send_byte__char__239select0__bit equ 0 504 071 718 btfss send_byte__char__239select0__byte,send_byte__char__239select0__bit 505 072 427 bcf serial_out__byte,serial_out__bit 506 073 618 btfsc send_byte__char__239select0__byte,send_byte__char__239select0__bit 507 074 527 bsf serial_out__byte,serial_out__bit 508 ; 2 cycles : 509 ; char := char >> 1 510 075 403 bcf c___byte,c___bit 511 076 338 rrf send_byte__char,f 512 ; call delay {{ }} 513 ; Switch from register bank 1 to register bank 0 514 077 4a4 bcf rp0___byte,rp0___bit 515 ; Register bank is now 0 516 078 9ec call delay 517 ; call delay {{ }} 518 079 9ec call delay 519 ; call delay {{ }} 520 07a 9ec call delay 521 ; Test and jump at end of loop takes 3 cycles : 522 ; 4 + 2 + 3 = 9 = no NOP ' s needed 523 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 524 07b 5a4 bsf rp0___byte,rp0___bit 525 ; Register bank is now 1 526 07c 2f9 decfsz send_byte__count,f 527 07d a71 goto send_byte__237_loop 528 send_byte__237_done: 529 ; `count_down count 8 ...' end 530 ; Send the stop bit : 531 ; serial_out := 1 532 07e 527 bsf serial_out__byte,serial_out__bit 533 ; call delay {{ }} 534 ; Switch from register bank 1 to register bank 0 535 07f 4a4 bcf rp0___byte,rp0___bit 536 ; Register bank is now 0 537 080 9ec call delay 538 ; call delay {{ }} 539 081 9ec call delay 540 ; call delay {{ }} 541 082 9ec call delay 542 ; procedure send_byte end 543 ; Switch from register bank 0 to register bank 1 544 083 5a4 bsf rp0___byte,rp0___bit 545 ; Register bank is now 1 546 084 800 retlw 0 547 ; bank 0 548 ; Default register bank is now 0 549 550 ; procedure set_up start 551 set_up: 552 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 553 ; Procedure must be called with PCLATH set to code bank 0 554 001d set_up__variables__base equ global__variables__bank0+21 555 001d set_up__bytes__base equ set_up__variables__base+0 556 001d set_up__bits__base equ set_up__variables__base+0 557 0001 set_up__total__bytes equ 1 558 ; arguments_none 559 ; This procedure will set the speed of motor to speed . 560 ; Reset failsafe : 561 ; fail_safe_low_counter := 0 562 085 079 clrf fail_safe_low_counter 563 ; fail_safe_high_counter := fail_safe 564 086 216 movf fail_safe,w 565 087 038 movwf fail_safe_high_counter 566 ; Mode Dir On Off 567 ; = = = = = = = = = = = = = = = = = = 568 ; 0 0 A 0 569 ; 0 1 B 0 570 ; 1 0 A B 571 ; 1 1 B A 572 ; Motor 0 : 573 ; if { ramp0 = 0 } start 574 088 210 movf ramp0,w 575 ; expression=`{ ramp0 = 0 }' exp_delay=1 true_delay=4 false_delay=7 true_size=4 false_size=7 576 089 743 btfss z___byte,z___bit 577 08a a90 goto label276__0false 578 label276__0true: 579 ; if { ramp0 = 0 } body start 580 ; No ramping : 581 ; actual_speed0 := desired_speed0 582 08b 20e movf desired_speed0,w 583 08c 028 movwf actual_speed0 584 ; ramp0_delay := 0 585 08d 072 clrf ramp0_delay 586 ; ramp0_offset := 0 587 08e 074 clrf ramp0_offset 588 ; if { ramp0 = 0 } body end 589 08f a97 goto label276__0end 590 label276__0false: 591 ; else body start 592 ; Ramping : 593 ; if { desired_speed0 < actual_speed0 } start 594 090 208 movf actual_speed0,w 595 091 08e subwf desired_speed0,w 596 ; expression=`{ desired_speed0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 597 092 703 btfss c___byte,c___bit 598 ; if { desired_speed0 < actual_speed0 } body start 599 ; ramp0_offset := 0xff 600 093 cff movlw 255 601 ; 1 instructions found for sharing 602 094 603 btfsc c___byte,c___bit 603 ; else body start 604 ; ramp0_offset := 1 605 095 c01 movlw 1 606 ; 1 instructions found for sharing 607 ; if exp=` desired_speed0 < actual_speed0 ' single true and false skip delay=6 608 ; Other expression=`{ desired_speed0 < actual_speed0 }' delay=6 609 ; 1 shared instructions follow 610 096 034 movwf ramp0_offset 611 ; if { desired_speed0 < actual_speed0 } end 612 ; else body end 613 ; if exp=` ramp0 = 0 ' generic 614 label276__0end: 615 ; Other expression=`{ ramp0 = 0 }' delay=-1 616 ; if { ramp0 = 0 } end 617 ; FIXME : do a motor0_off := 0 and delete the appropriate statements below ; 618 ; if { motor0_direction } start 619 ; expression=`{ motor0_direction }' exp_delay=0 true_delay=-2 false_delay=-2 true_size=7 false_size=7 620 097 75f btfss motor0_direction__byte,motor0_direction__bit 621 098 aa1 goto label290__0false 622 label290__0true: 623 ; if { motor0_direction } body start 624 ; Direction = 1 < Backward > : 625 ; if { motor0_mode } start 626 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 627 099 61f btfsc motor0_mode__byte,motor0_mode__bit 628 09a a9d goto label292__0true 629 label292__0false: 630 ; else body start 631 ; Mode = 0 < Pulsed > 632 ; motor0_off := 0 633 09b 06a clrf motor0_off 634 ; else body end 635 09c a9f goto label292__0end 636 label292__0true: 637 ; if { motor0_mode } body start 638 ; Mode = 1 < Continuous > : 639 ; motor0_off := motor0a_mask 640 09d c01 movlw 1 641 09e 02a movwf motor0_off 642 ; if { motor0_mode } body end 643 ; if exp=`motor0_mode' generic 644 label292__0end: 645 ; Other expression=`{ motor0_mode }' delay=-1 646 ; if { motor0_mode } end 647 ; motor0_on := motor0b_mask 648 09f c02 movlw 2 649 ; 1 instructions found for sharing 650 0a0 aa8 goto label290__0end 651 label290__0false: 652 ; else body start 653 ; Direction = 0 < Forward > : 654 ; if { motor0_mode } start 655 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 656 0a1 61f btfsc motor0_mode__byte,motor0_mode__bit 657 0a2 aa5 goto label302__0true 658 label302__0false: 659 ; else body start 660 ; Mode = 0 < Pulsed > : 661 ; motor0_off := 0 662 0a3 06a clrf motor0_off 663 ; else body end 664 0a4 aa7 goto label302__0end 665 label302__0true: 666 ; if { motor0_mode } body start 667 ; Mode = 1 < Continuous > : 668 ; motor0_off := motor0b_mask 669 0a5 c02 movlw 2 670 0a6 02a movwf motor0_off 671 ; if { motor0_mode } body end 672 ; if exp=`motor0_mode' generic 673 label302__0end: 674 ; Other expression=`{ motor0_mode }' delay=-1 675 ; if { motor0_mode } end 676 ; motor0_on := motor0a_mask 677 0a7 c01 movlw 1 678 ; 1 instructions found for sharing 679 ; if exp=`motor0_direction' generic 680 label290__0end: 681 ; Other expression=`{ motor0_direction }' delay=-1 682 ; 1 shared instructions follow 683 0a8 02b movwf motor0_on 684 ; if { motor0_direction } end 685 ; Motor1 : 686 ; if { ramp1 = 0 } start 687 0a9 211 movf ramp1,w 688 ; expression=`{ ramp1 = 0 }' exp_delay=1 true_delay=4 false_delay=7 true_size=4 false_size=7 689 0aa 743 btfss z___byte,z___bit 690 0ab ab1 goto label313__0false 691 label313__0true: 692 ; if { ramp1 = 0 } body start 693 ; No ramping : 694 ; actual_speed1 := desired_speed1 695 0ac 20f movf desired_speed1,w 696 0ad 029 movwf actual_speed1 697 ; ramp1_delay := 0 698 0ae 073 clrf ramp1_delay 699 ; ramp1_offset := 0 700 0af 075 clrf ramp1_offset 701 ; if { ramp1 = 0 } body end 702 0b0 ab8 goto label313__0end 703 label313__0false: 704 ; else body start 705 ; Ramping : 706 ; if { desired_speed1 < actual_speed1 } start 707 0b1 209 movf actual_speed1,w 708 0b2 08f subwf desired_speed1,w 709 ; expression=`{ desired_speed1 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 710 0b3 703 btfss c___byte,c___bit 711 ; if { desired_speed1 < actual_speed1 } body start 712 ; ramp1_offset := 0xff 713 0b4 cff movlw 255 714 ; 1 instructions found for sharing 715 0b5 603 btfsc c___byte,c___bit 716 ; else body start 717 ; ramp1_offset := 1 718 0b6 c01 movlw 1 719 ; 1 instructions found for sharing 720 ; if exp=` desired_speed1 < actual_speed1 ' single true and false skip delay=6 721 ; Other expression=`{ desired_speed1 < actual_speed1 }' delay=6 722 ; 1 shared instructions follow 723 0b7 035 movwf ramp1_offset 724 ; if { desired_speed1 < actual_speed1 } end 725 ; else body end 726 ; if exp=` ramp1 = 0 ' generic 727 label313__0end: 728 ; Other expression=`{ ramp1 = 0 }' delay=-1 729 ; if { ramp1 = 0 } end 730 ; FIXME : do a motor1 := 0 here and delete the appropriate statements below : 731 ; if { motor1_direction } start 732 ; expression=`{ motor1_direction }' exp_delay=0 true_delay=-2 false_delay=-2 true_size=7 false_size=7 733 0b8 77f btfss motor1_direction__byte,motor1_direction__bit 734 0b9 ac2 goto label327__0false 735 label327__0true: 736 ; if { motor1_direction } body start 737 ; Direction = 1 < Backward > : 738 ; if { motor1_mode } start 739 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 740 0ba 63f btfsc motor1_mode__byte,motor1_mode__bit 741 0bb abe goto label329__0true 742 label329__0false: 743 ; else body start 744 ; Mode = 1 < Pulsed > 745 ; motor1_off := 0 746 0bc 06c clrf motor1_off 747 ; else body end 748 0bd ac0 goto label329__0end 749 label329__0true: 750 ; if { motor1_mode } body start 751 ; Mode = 1 < Continuous > : 752 ; motor1_off := motor1a_mask 753 0be c10 movlw 16 754 0bf 02c movwf motor1_off 755 ; if { motor1_mode } body end 756 ; if exp=`motor1_mode' generic 757 label329__0end: 758 ; Other expression=`{ motor1_mode }' delay=-1 759 ; if { motor1_mode } end 760 ; motor1_on := motor1b_mask 761 0c0 c20 movlw 32 762 ; 1 instructions found for sharing 763 0c1 ac9 goto label327__0end 764 label327__0false: 765 ; else body start 766 ; Direction = 0 < Forward > : 767 ; if { motor1_mode } start 768 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 769 0c2 63f btfsc motor1_mode__byte,motor1_mode__bit 770 0c3 ac6 goto label339__0true 771 label339__0false: 772 ; else body start 773 ; Mode = 0 < Pulsed > : 774 ; motor1_off := 0 775 0c4 06c clrf motor1_off 776 ; else body end 777 0c5 ac8 goto label339__0end 778 label339__0true: 779 ; if { motor1_mode } body start 780 ; Mode = 1 < Continuous > : 781 ; motor1_off := motor1b_mask 782 0c6 c20 movlw 32 783 0c7 02c movwf motor1_off 784 ; if { motor1_mode } body end 785 ; if exp=`motor1_mode' generic 786 label339__0end: 787 ; Other expression=`{ motor1_mode }' delay=-1 788 ; if { motor1_mode } end 789 ; motor1_on := motor1a_mask 790 0c8 c10 movlw 16 791 ; 1 instructions found for sharing 792 ; if exp=`motor1_direction' generic 793 label327__0end: 794 ; Other expression=`{ motor1_direction }' delay=-1 795 ; 1 shared instructions follow 796 0c9 02d movwf motor1_on 797 ; if { motor1_direction } end 798 ; procedure set_up end 799 0ca 800 retlw 0 800 ; bank 1 801 ; Default register bank is now 1 802 ; comment {This is kind of ugly . The main routine pretty much fills up all} 803 ; comment {of code bank 1 . We need a little extra space . So we push global} 804 ; comment {variable initialization off to this little chunk of code in code} 805 ; comment {bank 0 . Not pretty .} 806 807 ; procedure reset start 808 reset: 809 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 810 ; Procedure must be called with PCLATH set to code bank 0 811 003a reset__variables__base equ global__variables__bank1+10 812 003a reset__bytes__base equ reset__variables__base+0 813 003a reset__bits__base equ reset__variables__base+0 814 0000 reset__total__bytes equ 0 815 ; arguments_none 816 ; Initialize the OPTION register : 817 ; inline assembly statements begin 818 0cb cc0 movlw option_mask 819 0cc 002 option 820 ; inline assembly statements end 821 ; FIXME : By a little careful global rearrangement , it should be possible 822 ; to use a loop to initialize everything . It is quite likely that it is 823 ; OK to just zero out all veriables < except option . > 824 ; Initialize everything else : 825 ; motor0e := 1 826 0cd 547 bsf motor0e__byte,motor0e__bit 827 ; motor1e := 1 828 0ce 567 bsf motor1e__byte,motor1e__bit 829 ; option := option_mask 830 0cf cc0 movlw 192 831 0d0 032 movwf option 832 ; actual_speed0 := 0 833 0d1 068 clrf actual_speed0 834 ; actual_speed1 := 0 835 0d2 069 clrf actual_speed1 836 ; motor0_off := 0 837 0d3 06a clrf motor0_off 838 ; motor0_on := 0 839 0d4 06b clrf motor0_on 840 ; motor1_off := 0 841 0d5 06c clrf motor1_off 842 ; motor1_on := 0 843 0d6 06d clrf motor1_on 844 ; desired_speed0 := 0 845 0d7 06e clrf desired_speed0 846 ; desired_speed1 := 0 847 0d8 06f clrf desired_speed1 848 ; ramp0 := 0 849 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 850 0d9 4a4 bcf rp0___byte,rp0___bit 851 ; Register bank is now 0 852 0da 070 clrf ramp0 853 ; ramp1 := 0 854 0db 071 clrf ramp1 855 ; ramp0_delay := 0 856 0dc 072 clrf ramp0_delay 857 ; ramp1_delay := 0 858 0dd 073 clrf ramp1_delay 859 ; ramp0_offset := 0 860 0de 074 clrf ramp0_offset 861 ; ramp1_offset := 0 862 0df 075 clrf ramp1_offset 863 ; motor0_direction := 0 864 0e0 45f bcf motor0_direction__byte,motor0_direction__bit 865 ; motor1_direction := 0 866 0e1 47f bcf motor1_direction__byte,motor1_direction__bit 867 ; motor0_mode := 0 868 0e2 41f bcf motor0_mode__byte,motor0_mode__bit 869 ; motor1_mode := 0 870 0e3 43f bcf motor1_mode__byte,motor1_mode__bit 871 ; fail_safe := 0 872 0e4 076 clrf fail_safe 873 ; fail_safe_errors := 0 874 0e5 077 clrf fail_safe_errors 875 ; fail_safe_high_counter := 0 876 0e6 078 clrf fail_safe_high_counter 877 ; fail_safe_low_counter := 0 878 0e7 079 clrf fail_safe_low_counter 879 ; glitch := 0 880 ; Switch from register bank 0 to register bank 1 (which contains glitch) 881 0e8 5a4 bsf rp0___byte,rp0___bit 882 ; Register bank is now 1 883 0e9 070 clrf glitch 884 ; id_index := 0 885 0ea 071 clrf id_index 886 ; procedure reset end 887 0eb 800 retlw 0 888 ; bank 0 889 ; Default register bank is now 0 890 ; comment {procedure xdelay <} 891 ; comment arguments_none 892 ; comment returns_nothing 893 ; comment {uniform_delay delay_instructions} 894 ; comment {} 895 ; comment {# Delay for 1 / 3 of a bit time .} 896 ; comment {} 897 ; comment {# Kick the dog :} 898 ; comment watch_dog_reset 899 ; comment {} 900 ; comment {# Do failsafe management :} 901 ; comment {mask := portb & < motor0e_mask | motor1e_mask >} 902 ; comment {} 903 ; comment {# This is the first probe of TMR0 :} 904 ; comment {if < tmr0 < actual_speed0 > <} 905 ; comment {motor0 := motor0_on} 906 ; comment {> else <} 907 ; comment {motor0 := motor0_off} 908 ; comment > 909 ; comment {if < tmr0 < actual_speed1 > <} 910 ; comment {motor1 := motor1_on} 911 ; comment {> else <} 912 ; comment {motor1 := motor1_off} 913 ; comment > 914 ; comment {spare := mask | motor0 | motor1} 915 ; comment {portb := spare} 916 ; comment > 917 918 ; procedure delay start 919 ; optimize 0 920 delay: 921 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 922 ; Procedure must be called with PCLATH set to code bank 0 923 001e delay__variables__base equ global__variables__bank0+22 924 001e delay__bytes__base equ delay__variables__base+0 925 001f delay__bits__base equ delay__variables__base+1 926 0001 delay__total__bytes equ 1 927 001e delay__514byte2 equ delay__bytes__base+0 928 001e delay__459byte2 equ delay__bytes__base+0 929 001e delay__431byte1 equ delay__bytes__base+0 930 001e delay__492byte2 equ delay__bytes__base+0 931 001e delay__461byte2 equ delay__bytes__base+0 932 001e delay__462byte2 equ delay__bytes__base+0 933 ; arguments_none 934 ; uniform_delay delay_instructions 935 ; Uniform delay remaining = 131 Accumulated Delay = 0 936 ; Uniform delay remaining = 131 Accumulated Delay = 0 937 ; Delay for 1 / 3 of a bit time . 938 ; Uniform delay remaining = 131 Accumulated Delay = 0 939 ; Uniform delay remaining = 131 Accumulated Delay = 0 940 ; Kick the dog : 941 ; Uniform delay remaining = 131 Accumulated Delay = 0 942 ; watch_dog_reset 943 0ec 004 clrwdt 944 ; Uniform delay remaining = 130 Accumulated Delay = 1 945 ; Uniform delay remaining = 130 Accumulated Delay = 1 946 ; Do failsafe management : 947 ; Uniform delay remaining = 130 Accumulated Delay = 1 948 ; mask := portb & {{ motor0e_mask | motor1e_mask }} 949 0ed c0c movlw 12 950 0ee 146 andwf portb,w 951 0ef 03a movwf mask 952 ; Uniform delay remaining = 127 Accumulated Delay = 4 953 ; Uniform delay remaining = 127 Accumulated Delay = 4 954 ; This is the first probe of TMR0 : 955 ; Uniform delay remaining = 127 Accumulated Delay = 4 956 ; if { tmr0 < actual_speed0 } start 957 0f0 208 movf actual_speed0,w 958 0f1 081 subwf tmr0,w 959 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 960 0f2 703 btfss c___byte,c___bit 961 ; if { tmr0 < actual_speed0 } body start 962 ; Uniform delay remaining = 127 Accumulated Delay = 0 963 ; motor0 := motor0_on 964 0f3 20b movf motor0_on,w 965 ; 1 instructions found for sharing 966 ; Uniform delay remaining = 125 Accumulated Delay = 2 967 ; if { tmr0 < actual_speed0 } body end 968 0f4 603 btfsc c___byte,c___bit 969 ; else body start 970 ; Uniform delay remaining = 127 Accumulated Delay = 0 971 ; motor0 := motor0_off 972 0f5 20a movf motor0_off,w 973 ; 1 instructions found for sharing 974 ; Uniform delay remaining = 125 Accumulated Delay = 2 975 ; else body end 976 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 977 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 978 ; 1 shared instructions follow 979 0f6 03b movwf motor0 980 ; if { tmr0 < actual_speed0 } end 981 ; Uniform delay remaining = 120 Accumulated Delay = 11 982 ; if { tmr0 < actual_speed1 } start 983 0f7 209 movf actual_speed1,w 984 0f8 081 subwf tmr0,w 985 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 986 0f9 703 btfss c___byte,c___bit 987 ; if { tmr0 < actual_speed1 } body start 988 ; Uniform delay remaining = 120 Accumulated Delay = 0 989 ; motor1 := motor1_on 990 0fa 20d movf motor1_on,w 991 ; 1 instructions found for sharing 992 ; Uniform delay remaining = 118 Accumulated Delay = 2 993 ; if { tmr0 < actual_speed1 } body end 994 0fb 603 btfsc c___byte,c___bit 995 ; else body start 996 ; Uniform delay remaining = 120 Accumulated Delay = 0 997 ; motor1 := motor1_off 998 0fc 20c movf motor1_off,w 999 ; 1 instructions found for sharing 1000 ; Uniform delay remaining = 118 Accumulated Delay = 2 1001 ; else body end 1002 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1003 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1004 ; 1 shared instructions follow 1005 0fd 03c movwf motor1 1006 ; if { tmr0 < actual_speed1 } end 1007 ; Uniform delay remaining = 113 Accumulated Delay = 18 1008 ; portb := mask | motor0 | motor1 1009 0fe 21a movf mask,w 1010 0ff 11b iorwf motor0,w 1011 100 11c iorwf motor1,w 1012 101 026 movwf portb 1013 ; Uniform delay remaining = 109 Accumulated Delay = 22 1014 ; Uniform delay remaining = 109 Accumulated Delay = 22 1015 ; First check out < fail_safe_counter > : 1016 ; Uniform delay remaining = 109 Accumulated Delay = 22 1017 ; fail_safe_low_counter := fail_safe_low_counter - 1 1018 102 0f9 decf fail_safe_low_counter,f 1019 ; Uniform delay remaining = 108 Accumulated Delay = 23 1020 ; if { z } start 1021 ; expression=`{ z }' exp_delay=0 true_delay=17 false_delay=0 true_size=28 false_size=0 1022 103 643 btfsc z__byte,z__bit 1023 104 b0a goto label459__0true 1024 label459__0false: 1025 ; Delay 16 cycles 1026 105 c05 movlw 5 1027 106 03e movwf delay__459byte2 1028 delay__459delay1: 1029 107 2fe decfsz delay__459byte2,f 1030 108 b07 goto delay__459delay1 1031 109 b26 goto label459__0end 1032 label459__0true: 1033 ; if { z } body start 1034 ; Uniform delay remaining = 108 Accumulated Delay = 0 1035 ; fail_safe_high_counter := fail_safe_high_counter - 1 1036 10a 0f8 decf fail_safe_high_counter,f 1037 ; Uniform delay remaining = 107 Accumulated Delay = 1 1038 ; if { z } start 1039 ; expression=`{ z }' exp_delay=0 true_delay=13 false_delay=0 true_size=18 false_size=0 1040 10b 643 btfsc z__byte,z__bit 1041 10c b14 goto label461__0true 1042 label461__0false: 1043 ; Delay 12 cycles 1044 10d c03 movlw 3 1045 10e 03e movwf delay__461byte2 1046 delay__461delay1: 1047 10f 2fe decfsz delay__461byte2,f 1048 110 b0f goto delay__461delay1 1049 111 000 nop 1050 112 000 nop 1051 113 b26 goto label461__0end 1052 label461__0true: 1053 ; if { z } body start 1054 ; Uniform delay remaining = 107 Accumulated Delay = 0 1055 ; if { fail_safe != 0 } start 1056 114 216 movf fail_safe,w 1057 ; expression=`{ fail_safe != 0 }' exp_delay=1 true_delay=9 false_delay=0 true_size=9 false_size=0 1058 115 743 btfss z___byte,z___bit 1059 116 b1d goto label462__0true 1060 label462__0false: 1061 ; Delay 8 cycles 1062 117 c02 movlw 2 1063 118 03e movwf delay__462byte2 1064 delay__462delay1: 1065 119 2fe decfsz delay__462byte2,f 1066 11a b19 goto delay__462delay1 1067 11b 000 nop 1068 11c b26 goto label462__0end 1069 label462__0true: 1070 ; if { fail_safe != 0 } body start 1071 ; Uniform delay remaining = 107 Accumulated Delay = 0 1072 ; Turn the motors off : 1073 ; Uniform delay remaining = 107 Accumulated Delay = 0 1074 ; motor0_on := 0 1075 11d 06b clrf motor0_on 1076 ; Uniform delay remaining = 106 Accumulated Delay = 1 1077 ; motor0_off := 0 1078 11e 06a clrf motor0_off 1079 ; Uniform delay remaining = 105 Accumulated Delay = 2 1080 ; motor1_on := 0 1081 11f 06d clrf motor1_on 1082 ; Uniform delay remaining = 104 Accumulated Delay = 3 1083 ; motor1_off := 0 1084 120 06c clrf motor1_off 1085 ; Uniform delay remaining = 103 Accumulated Delay = 4 1086 ; desired_speed0 := 0 1087 121 06e clrf desired_speed0 1088 ; Uniform delay remaining = 102 Accumulated Delay = 5 1089 ; desired_speed1 := 0 1090 122 06f clrf desired_speed1 1091 ; Uniform delay remaining = 101 Accumulated Delay = 6 1092 ; actual_speed0 := 0 1093 123 068 clrf actual_speed0 1094 ; Uniform delay remaining = 100 Accumulated Delay = 7 1095 ; actual_speed0 := 0 1096 124 068 clrf actual_speed0 1097 ; Uniform delay remaining = 99 Accumulated Delay = 8 1098 ; fail_safe_errors := fail_safe_errors + 1 1099 125 2b7 incf fail_safe_errors,f 1100 ; Uniform delay remaining = 98 Accumulated Delay = 9 1101 ; Uniform delay remaining = 98 Accumulated Delay = 9 1102 ; if { fail_safe != 0 } body end 1103 ; if exp=` fail_safe != 0 ' total delay=13 1104 ; if exp=` fail_safe != 0 ' generic 1105 label462__0end: 1106 ; Other expression=`{ fail_safe != 0 }' delay=13 1107 ; if { fail_safe != 0 } end 1108 ; Uniform delay remaining = 94 Accumulated Delay = 13 1109 ; Uniform delay remaining = 94 Accumulated Delay = 13 1110 ; if { z } body end 1111 ; if exp=`z' total delay=16 1112 ; if exp=`z' generic 1113 label461__0end: 1114 ; Other expression=`{ z }' delay=16 1115 ; if { z } end 1116 ; Uniform delay remaining = 91 Accumulated Delay = 17 1117 ; Uniform delay remaining = 91 Accumulated Delay = 17 1118 ; if { z } body end 1119 ; if exp=`z' total delay=20 1120 ; if exp=`z' generic 1121 label459__0end: 1122 ; Other expression=`{ z }' delay=20 1123 ; if { z } end 1124 ; Uniform delay remaining = 88 Accumulated Delay = 43 1125 ; Uniform delay remaining = 88 Accumulated Delay = 43 1126 ; This is the second probe of TMR0 : 1127 ; Uniform delay remaining = 88 Accumulated Delay = 43 1128 ; if { tmr0 < actual_speed0 } start 1129 126 208 movf actual_speed0,w 1130 127 081 subwf tmr0,w 1131 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1132 128 703 btfss c___byte,c___bit 1133 ; if { tmr0 < actual_speed0 } body start 1134 ; Uniform delay remaining = 88 Accumulated Delay = 0 1135 ; motor0 := motor0_on 1136 129 20b movf motor0_on,w 1137 ; 1 instructions found for sharing 1138 ; Uniform delay remaining = 86 Accumulated Delay = 2 1139 ; if { tmr0 < actual_speed0 } body end 1140 12a 603 btfsc c___byte,c___bit 1141 ; else body start 1142 ; Uniform delay remaining = 88 Accumulated Delay = 0 1143 ; motor0 := motor0_off 1144 12b 20a movf motor0_off,w 1145 ; 1 instructions found for sharing 1146 ; Uniform delay remaining = 86 Accumulated Delay = 2 1147 ; else body end 1148 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1149 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1150 ; 1 shared instructions follow 1151 12c 03b movwf motor0 1152 ; if { tmr0 < actual_speed0 } end 1153 ; Uniform delay remaining = 81 Accumulated Delay = 50 1154 ; if { tmr0 < actual_speed1 } start 1155 12d 209 movf actual_speed1,w 1156 12e 081 subwf tmr0,w 1157 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1158 12f 703 btfss c___byte,c___bit 1159 ; if { tmr0 < actual_speed1 } body start 1160 ; Uniform delay remaining = 81 Accumulated Delay = 0 1161 ; motor1 := motor1_on 1162 130 20d movf motor1_on,w 1163 ; 1 instructions found for sharing 1164 ; Uniform delay remaining = 79 Accumulated Delay = 2 1165 ; if { tmr0 < actual_speed1 } body end 1166 131 603 btfsc c___byte,c___bit 1167 ; else body start 1168 ; Uniform delay remaining = 81 Accumulated Delay = 0 1169 ; motor1 := motor1_off 1170 132 20c movf motor1_off,w 1171 ; 1 instructions found for sharing 1172 ; Uniform delay remaining = 79 Accumulated Delay = 2 1173 ; else body end 1174 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1175 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1176 ; 1 shared instructions follow 1177 133 03c movwf motor1 1178 ; if { tmr0 < actual_speed1 } end 1179 ; Uniform delay remaining = 74 Accumulated Delay = 57 1180 ; portb := mask | motor0 | motor1 1181 134 21a movf mask,w 1182 135 11b iorwf motor0,w 1183 136 11c iorwf motor1,w 1184 137 026 movwf portb 1185 ; Uniform delay remaining = 70 Accumulated Delay = 61 1186 ; Uniform delay remaining = 70 Accumulated Delay = 61 1187 ; Do < ramp0 > management : 1188 ; Uniform delay remaining = 70 Accumulated Delay = 61 1189 ; ramp0_delay := ramp0_delay - 1 1190 138 0f2 decf ramp0_delay,f 1191 ; Uniform delay remaining = 69 Accumulated Delay = 62 1192 ; if { z } start 1193 ; expression=`{ z }' exp_delay=0 true_delay=9 false_delay=0 true_size=10 false_size=0 1194 139 643 btfsc z__byte,z__bit 1195 13a b41 goto label492__0true 1196 label492__0false: 1197 ; Delay 8 cycles 1198 13b c02 movlw 2 1199 13c 03e movwf delay__492byte2 1200 delay__492delay1: 1201 13d 2fe decfsz delay__492byte2,f 1202 13e b3d goto delay__492delay1 1203 13f 000 nop 1204 140 b4b goto label492__0end 1205 label492__0true: 1206 ; if { z } body start 1207 ; Uniform delay remaining = 69 Accumulated Delay = 0 1208 ; ramp0_delay := ramp0 1209 141 210 movf ramp0,w 1210 142 032 movwf ramp0_delay 1211 ; Uniform delay remaining = 67 Accumulated Delay = 2 1212 ; if { actual_speed0 != desired_speed0 } start 1213 143 208 movf actual_speed0,w 1214 144 08e subwf desired_speed0,w 1215 ; expression=`{ actual_speed0 != desired_speed0 }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1216 145 743 btfss z___byte,z___bit 1217 146 b49 goto label494__0true 1218 label494__0false: 1219 ; Delay 1 cycles 1220 147 000 nop 1221 148 b4b goto label494__0end 1222 label494__0true: 1223 ; if { actual_speed0 != desired_speed0 } body start 1224 ; Uniform delay remaining = 67 Accumulated Delay = 0 1225 ; actual_speed0 := actual_speed0 + ramp0_offset 1226 149 214 movf ramp0_offset,w 1227 14a 1e8 addwf actual_speed0,f 1228 ; Uniform delay remaining = 65 Accumulated Delay = 2 1229 ; Uniform delay remaining = 65 Accumulated Delay = 2 1230 ; if { actual_speed0 != desired_speed0 } body end 1231 ; if exp=` actual_speed0 != desired_speed0 ' total delay=7 1232 ; if exp=` actual_speed0 != desired_speed0 ' generic 1233 label494__0end: 1234 ; Other expression=`{ actual_speed0 != desired_speed0 }' delay=7 1235 ; if { actual_speed0 != desired_speed0 } end 1236 ; Uniform delay remaining = 60 Accumulated Delay = 9 1237 ; Uniform delay remaining = 60 Accumulated Delay = 9 1238 ; if { z } body end 1239 ; if exp=`z' total delay=12 1240 ; if exp=`z' generic 1241 label492__0end: 1242 ; Other expression=`{ z }' delay=12 1243 ; if { z } end 1244 ; Uniform delay remaining = 57 Accumulated Delay = 74 1245 ; Uniform delay remaining = 57 Accumulated Delay = 74 1246 ; This is the third probe of TMR0 : 1247 ; Uniform delay remaining = 57 Accumulated Delay = 74 1248 ; if { tmr0 < actual_speed0 } start 1249 14b 208 movf actual_speed0,w 1250 14c 081 subwf tmr0,w 1251 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1252 14d 703 btfss c___byte,c___bit 1253 ; if { tmr0 < actual_speed0 } body start 1254 ; Uniform delay remaining = 57 Accumulated Delay = 0 1255 ; motor0 := motor0_on 1256 14e 20b movf motor0_on,w 1257 ; 1 instructions found for sharing 1258 ; Uniform delay remaining = 55 Accumulated Delay = 2 1259 ; if { tmr0 < actual_speed0 } body end 1260 14f 603 btfsc c___byte,c___bit 1261 ; else body start 1262 ; Uniform delay remaining = 57 Accumulated Delay = 0 1263 ; motor0 := motor0_off 1264 150 20a movf motor0_off,w 1265 ; 1 instructions found for sharing 1266 ; Uniform delay remaining = 55 Accumulated Delay = 2 1267 ; else body end 1268 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1269 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1270 ; 1 shared instructions follow 1271 151 03b movwf motor0 1272 ; if { tmr0 < actual_speed0 } end 1273 ; Uniform delay remaining = 50 Accumulated Delay = 81 1274 ; if { tmr0 < actual_speed1 } start 1275 152 209 movf actual_speed1,w 1276 153 081 subwf tmr0,w 1277 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1278 154 703 btfss c___byte,c___bit 1279 ; if { tmr0 < actual_speed1 } body start 1280 ; Uniform delay remaining = 50 Accumulated Delay = 0 1281 ; motor1 := motor1_on 1282 155 20d movf motor1_on,w 1283 ; 1 instructions found for sharing 1284 ; Uniform delay remaining = 48 Accumulated Delay = 2 1285 ; if { tmr0 < actual_speed1 } body end 1286 156 603 btfsc c___byte,c___bit 1287 ; else body start 1288 ; Uniform delay remaining = 50 Accumulated Delay = 0 1289 ; motor1 := motor1_off 1290 157 20c movf motor1_off,w 1291 ; 1 instructions found for sharing 1292 ; Uniform delay remaining = 48 Accumulated Delay = 2 1293 ; else body end 1294 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1295 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1296 ; 1 shared instructions follow 1297 158 03c movwf motor1 1298 ; if { tmr0 < actual_speed1 } end 1299 ; Uniform delay remaining = 43 Accumulated Delay = 88 1300 ; portb := mask | motor0 | motor1 1301 159 21a movf mask,w 1302 15a 11b iorwf motor0,w 1303 15b 11c iorwf motor1,w 1304 15c 026 movwf portb 1305 ; Uniform delay remaining = 39 Accumulated Delay = 92 1306 ; Uniform delay remaining = 39 Accumulated Delay = 92 1307 ; Do < ramp1 > management : 1308 ; Uniform delay remaining = 39 Accumulated Delay = 92 1309 ; ramp1_delay := ramp1_delay - 1 1310 15d 0f3 decf ramp1_delay,f 1311 ; Uniform delay remaining = 38 Accumulated Delay = 93 1312 ; if { z } start 1313 ; expression=`{ z }' exp_delay=0 true_delay=9 false_delay=0 true_size=10 false_size=0 1314 15e 643 btfsc z__byte,z__bit 1315 15f b66 goto label514__0true 1316 label514__0false: 1317 ; Delay 8 cycles 1318 160 c02 movlw 2 1319 161 03e movwf delay__514byte2 1320 delay__514delay1: 1321 162 2fe decfsz delay__514byte2,f 1322 163 b62 goto delay__514delay1 1323 164 000 nop 1324 165 b70 goto label514__0end 1325 label514__0true: 1326 ; if { z } body start 1327 ; Uniform delay remaining = 38 Accumulated Delay = 0 1328 ; ramp1_delay := ramp1 1329 166 211 movf ramp1,w 1330 167 033 movwf ramp1_delay 1331 ; Uniform delay remaining = 36 Accumulated Delay = 2 1332 ; if { actual_speed1 != desired_speed1 } start 1333 168 209 movf actual_speed1,w 1334 169 08f subwf desired_speed1,w 1335 ; expression=`{ actual_speed1 != desired_speed1 }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1336 16a 743 btfss z___byte,z___bit 1337 16b b6e goto label516__0true 1338 label516__0false: 1339 ; Delay 1 cycles 1340 16c 000 nop 1341 16d b70 goto label516__0end 1342 label516__0true: 1343 ; if { actual_speed1 != desired_speed1 } body start 1344 ; Uniform delay remaining = 36 Accumulated Delay = 0 1345 ; actual_speed1 := actual_speed1 + ramp1_offset 1346 16e 215 movf ramp1_offset,w 1347 16f 1e9 addwf actual_speed1,f 1348 ; Uniform delay remaining = 34 Accumulated Delay = 2 1349 ; Uniform delay remaining = 34 Accumulated Delay = 2 1350 ; if { actual_speed1 != desired_speed1 } body end 1351 ; if exp=` actual_speed1 != desired_speed1 ' total delay=7 1352 ; if exp=` actual_speed1 != desired_speed1 ' generic 1353 label516__0end: 1354 ; Other expression=`{ actual_speed1 != desired_speed1 }' delay=7 1355 ; if { actual_speed1 != desired_speed1 } end 1356 ; Uniform delay remaining = 29 Accumulated Delay = 9 1357 ; Uniform delay remaining = 29 Accumulated Delay = 9 1358 ; if { z } body end 1359 ; if exp=`z' total delay=12 1360 ; if exp=`z' generic 1361 label514__0end: 1362 ; Other expression=`{ z }' delay=12 1363 ; if { z } end 1364 ; Uniform delay remaining = 26 Accumulated Delay = 105 1365 ; Uniform delay remaining = 26 Accumulated Delay = 105 1366 ; This is the forth probe of TMR0 : 1367 ; Uniform delay remaining = 26 Accumulated Delay = 105 1368 ; if { tmr0 < actual_speed0 } start 1369 170 208 movf actual_speed0,w 1370 171 081 subwf tmr0,w 1371 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1372 172 703 btfss c___byte,c___bit 1373 ; if { tmr0 < actual_speed0 } body start 1374 ; Uniform delay remaining = 26 Accumulated Delay = 0 1375 ; motor0 := motor0_on 1376 173 20b movf motor0_on,w 1377 ; 1 instructions found for sharing 1378 ; Uniform delay remaining = 24 Accumulated Delay = 2 1379 ; if { tmr0 < actual_speed0 } body end 1380 174 603 btfsc c___byte,c___bit 1381 ; else body start 1382 ; Uniform delay remaining = 26 Accumulated Delay = 0 1383 ; motor0 := motor0_off 1384 175 20a movf motor0_off,w 1385 ; 1 instructions found for sharing 1386 ; Uniform delay remaining = 24 Accumulated Delay = 2 1387 ; else body end 1388 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1389 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1390 ; 1 shared instructions follow 1391 176 03b movwf motor0 1392 ; if { tmr0 < actual_speed0 } end 1393 ; Uniform delay remaining = 19 Accumulated Delay = 112 1394 ; if { tmr0 < actual_speed1 } start 1395 177 209 movf actual_speed1,w 1396 178 081 subwf tmr0,w 1397 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1398 179 703 btfss c___byte,c___bit 1399 ; if { tmr0 < actual_speed1 } body start 1400 ; Uniform delay remaining = 19 Accumulated Delay = 0 1401 ; motor1 := motor1_on 1402 17a 20d movf motor1_on,w 1403 ; 1 instructions found for sharing 1404 ; Uniform delay remaining = 17 Accumulated Delay = 2 1405 ; if { tmr0 < actual_speed1 } body end 1406 17b 603 btfsc c___byte,c___bit 1407 ; else body start 1408 ; Uniform delay remaining = 19 Accumulated Delay = 0 1409 ; motor1 := motor1_off 1410 17c 20c movf motor1_off,w 1411 ; 1 instructions found for sharing 1412 ; Uniform delay remaining = 17 Accumulated Delay = 2 1413 ; else body end 1414 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1415 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1416 ; 1 shared instructions follow 1417 17d 03c movwf motor1 1418 ; if { tmr0 < actual_speed1 } end 1419 ; Uniform delay remaining = 12 Accumulated Delay = 119 1420 ; portb := mask | motor0 | motor1 1421 17e 21a movf mask,w 1422 17f 11b iorwf motor0,w 1423 180 11c iorwf motor1,w 1424 181 026 movwf portb 1425 ; Uniform delay remaining = 8 Accumulated Delay = 123 1426 ; Uniform delay remaining = 8 Accumulated Delay = 123 1427 ; Soak up remaining 8 cycles 1428 ; Delay 8 cycles 1429 182 c02 movlw 2 1430 183 03e movwf delay__431byte1 1431 delay__431delay0: 1432 184 2fe decfsz delay__431byte1,f 1433 185 b84 goto delay__431delay0 1434 186 000 nop 1435 ; procedure delay end 1436 187 800 retlw 0 1437 ; optimize 1 1438 ; origin 0x200 1439 org 512 1440 ; bank 1 1441 ; Default register bank is now 1 1442 1443 ; procedure main start 1444 switch__586block_start: 1445 200 1e2 addwf pcl___register,f 1446 201 aa8 goto switch__586block587 1447 202 aa8 goto switch__586block587 1448 203 abe goto switch__586block597 1449 204 ac8 goto switch__586block603 1450 205 ace goto switch__586block608 1451 206 ace goto switch__586block608 1452 207 ace goto switch__586block608 1453 208 ace goto switch__586block608 1454 switch__586block_end: 1455 ; switch_check 586 switch__586block_start switch__586block_end 1456 switch__657block_start: 1457 209 1e2 addwf pcl___register,f 1458 20a b34 goto switch__657block658 1459 20b b3c goto switch__657block662 1460 20c b43 goto switch__657block666 1461 20d b43 goto switch__657block666 1462 20e b4c goto switch__657block674 1463 20f b4c goto switch__657block674 1464 210 b66 goto switch__657block696 1465 211 b66 goto switch__657block696 1466 switch__657block_end: 1467 ; switch_check 657 switch__657block_start switch__657block_end 1468 switch__709block_start: 1469 212 1e2 addwf pcl___register,f 1470 213 b7d goto switch__709block710 1471 214 b88 goto switch__709block715 1472 215 b90 goto switch__709block719 1473 216 b96 goto switch__709block723 1474 217 b9c goto switch__709block727 1475 218 b9e goto switch__709block731 1476 219 ba0 goto switch__709block735 1477 21a ba2 goto switch__709block739 1478 switch__709block_end: 1479 ; switch_check 709 switch__709block_start switch__709block_end 1480 switch__583block_start: 1481 21b 1e2 addwf pcl___register,f 1482 21c aa5 goto switch__583block584 1483 21d af4 goto switch__583block624 1484 21e b2b goto switch__583block647 1485 21f b31 goto switch__583block655 1486 220 b7a goto switch__583block707 1487 221 ba4 goto switch__583block745 1488 222 baf goto switch__583default753 1489 223 baf goto switch__583default753 1490 switch__583block_end: 1491 ; switch_check 583 switch__583block_start switch__583block_end 1492 switch__763block_start: 1493 224 1e2 addwf pcl___register,f 1494 225 bb9 goto switch__763block764 1495 226 bbc goto switch__763block768 1496 227 bbf goto switch__763block772 1497 228 bc5 goto switch__763block776 1498 229 bca goto switch__763block780 1499 22a bda goto switch__763block791 1500 22b bdc goto switch__763block795 1501 22c be3 goto switch__763block800 1502 switch__763block_end: 1503 ; switch_check 763 switch__763block_start switch__763block_end 1504 switch__760block_start: 1505 22d 1e2 addwf pcl___register,f 1506 22e be6 goto switch__760end 1507 22f be6 goto switch__760end 1508 230 be6 goto switch__760end 1509 231 be6 goto switch__760end 1510 232 be6 goto switch__760end 1511 233 be6 goto switch__760end 1512 234 be6 goto switch__760end 1513 235 bb6 goto switch__760block761 1514 switch__760block_end: 1515 ; switch_check 760 switch__760block_start switch__760block_end 1516 switch__553block_start: 1517 236 1e2 addwf pcl___register,f 1518 237 a49 goto switch__553block554 1519 238 a75 goto switch__553block567 1520 239 a9f goto switch__553block581 1521 23a bb0 goto switch__553block758 1522 switch__553block_end: 1523 ; switch_check 553 switch__553block_start switch__553block_end 1524 main: 1525 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1526 ; Procedure must be called with PCLATH set to code bank 0 1527 003a main__variables__base equ global__variables__bank1+10 1528 003a main__bytes__base equ main__variables__base+0 1529 003e main__bits__base equ main__variables__base+4 1530 0004 main__total__bytes equ 4 1531 003c main__760byte0 equ main__bytes__base+2 1532 003c main__556byte1 equ main__bytes__base+2 1533 003c main__553byte0 equ main__bytes__base+2 1534 003c main__556byte3 equ main__bytes__base+2 1535 003c main__583byte0 equ main__bytes__base+2 1536 003c main__569byte0 equ main__bytes__base+2 1537 003d main__556byte2 equ main__bytes__base+3 1538 ; arguments_none 1539 003a main__command equ main__bytes__base+0 1540 003b main__temp equ main__bytes__base+1 1541 ; call reset {{ }} 1542 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1543 23b 4a3 bcf pa0___byte,pa0___bit 1544 23c 9cb call reset 1545 ; Loop waiting for commands : 1546 ; loop_forever ... start 1547 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1548 23d 5a3 bsf pa0___byte,pa0___bit 1549 main__548loop__forever: 1550 ; Get a command byte : 1551 ; command := get_byte {{ }} 1552 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1553 23e 4a3 bcf pa0___byte,pa0___bit 1554 23f 93c call get_byte 1555 240 214 movf get_byte__0return__byte,w 1556 241 03a movwf main__command 1557 ; Dispatch on command : 1558 ; switch { command >> 6 } 1559 242 39a swapf main__command,w 1560 243 03c movwf main__553byte0 1561 244 33c rrf main__553byte0,f 1562 245 31c rrf main__553byte0,w 1563 246 e03 andlw 3 1564 ; case 0 1565 ; case 1 1566 ; case 2 1567 ; case 3 1568 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1569 247 5a3 bsf pa0___byte,pa0___bit 1570 248 a36 goto switch__553block_start 1571 switch__553block554: 1572 ; Set Quick < Command = 00 hh hhdm > : 1573 ; temp := {{ {{ command << 2 }} & 0xf0 }} | {{ command >> 2 }} 1574 249 35a rlf main__command,w 1575 24a 03c movwf main__556byte3 1576 24b 35c rlf main__556byte3,w 1577 24c ef0 andlw 240 1578 24d 03d movwf main__556byte2 1579 24e 31a rrf main__command,w 1580 24f 03c movwf main__556byte1 1581 250 31c rrf main__556byte1,w 1582 251 e3f andlw 63 1583 252 11d iorwf main__556byte2,w 1584 253 03b movwf main__temp 1585 ; if { command @ 0 } start 1586 ; Alias variable for select command @ 0 1587 003a main__command__557select0 equ main__command+0 1588 003a main__command__557select0__byte equ main__command+0 1589 0000 main__command__557select0__bit equ 0 1590 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=5 false_delay=5 true_size=5 false_size=5 1591 254 71a btfss main__command__557select0__byte,main__command__557select0__bit 1592 255 a63 goto label557__1false 1593 label557__1true: 1594 ; if { command @ 0 } body start 1595 ; Motor : 1596 ; desired_speed1 := temp 1597 256 21b movf main__temp,w 1598 257 02f movwf desired_speed1 1599 ; motor1_direction := command @ 1 1600 ; Alias variable for select command @ 1 1601 003a main__command__560select0 equ main__command+0 1602 003a main__command__560select0__byte equ main__command+0 1603 0001 main__command__560select0__bit equ 1 1604 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1605 258 4a4 bcf rp0___byte,rp0___bit 1606 ; Register bank is now 0 1607 259 47f bcf motor1_direction__byte,motor1_direction__bit 1608 ; Switch from register bank 0 to register bank 1 (which contains main__command__560select0__byte) 1609 25a 5a4 bsf rp0___byte,rp0___bit 1610 ; Register bank is now 1 1611 25b 443 bcf z___byte,z___bit 1612 25c 63a btfsc main__command__560select0__byte,main__command__560select0__bit 1613 25d 543 bsf z___byte,z___bit 1614 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1615 25e 4a4 bcf rp0___byte,rp0___bit 1616 ; Register bank is now 0 1617 25f 643 btfsc z___byte,z___bit 1618 260 57f bsf motor1_direction__byte,motor1_direction__bit 1619 ; if { command @ 0 } body end 1620 ; Switch from register bank 0 to register bank 1 1621 261 5a4 bsf rp0___byte,rp0___bit 1622 ; Register bank is now 1 1623 262 a6f goto label557__1end 1624 label557__1false: 1625 ; else body start 1626 ; desired_speed0 := temp 1627 263 21b movf main__temp,w 1628 264 02e movwf desired_speed0 1629 ; motor0_direction := command @ 1 1630 ; Alias variable for select command @ 1 1631 003a main__command__563select0 equ main__command+0 1632 003a main__command__563select0__byte equ main__command+0 1633 0001 main__command__563select0__bit equ 1 1634 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1635 265 4a4 bcf rp0___byte,rp0___bit 1636 ; Register bank is now 0 1637 266 45f bcf motor0_direction__byte,motor0_direction__bit 1638 ; Switch from register bank 0 to register bank 1 (which contains main__command__563select0__byte) 1639 267 5a4 bsf rp0___byte,rp0___bit 1640 ; Register bank is now 1 1641 268 443 bcf z___byte,z___bit 1642 269 63a btfsc main__command__563select0__byte,main__command__563select0__bit 1643 26a 543 bsf z___byte,z___bit 1644 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1645 26b 4a4 bcf rp0___byte,rp0___bit 1646 ; Register bank is now 0 1647 26c 643 btfsc z___byte,z___bit 1648 26d 55f bsf motor0_direction__byte,motor0_direction__bit 1649 ; else body end 1650 ; if exp=` command @ 0 ' generic 1651 ; Switch from register bank 0 to register bank 1 1652 26e 5a4 bsf rp0___byte,rp0___bit 1653 ; Register bank is now 1 1654 label557__1end: 1655 ; Other expression=`{ command @ 0 }' delay=-1 1656 ; if { command @ 0 } end 1657 ; call set_up {{ }} 1658 ; Switch from register bank 1 to register bank 0 1659 26f 4a4 bcf rp0___byte,rp0___bit 1660 ; Register bank is now 0 1661 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1662 270 4a3 bcf pa0___byte,pa0___bit 1663 271 985 call set_up 1664 ; Switch from register bank 0 to register bank 1 1665 272 5a4 bsf rp0___byte,rp0___bit 1666 ; Register bank is now 1 1667 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1668 273 5a3 bsf pa0___byte,pa0___bit 1669 274 be6 goto switch__553end 1670 switch__553block567: 1671 ; Set Low < Command = 01 ll lldm > : 1672 ; temp := {{ command >> 2 }} & 0xf 1673 275 31a rrf main__command,w 1674 276 03c movwf main__569byte0 1675 277 31c rrf main__569byte0,w 1676 278 e0f andlw 15 1677 279 03b movwf main__temp 1678 ; if { command @ 0 } start 1679 ; Alias variable for select command @ 0 1680 003a main__command__570select0 equ main__command+0 1681 003a main__command__570select0__byte equ main__command+0 1682 0000 main__command__570select0__bit equ 0 1683 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=7 false_delay=7 true_size=7 false_size=7 1684 27a 71a btfss main__command__570select0__byte,main__command__570select0__bit 1685 27b a8b goto label570__1false 1686 label570__1true: 1687 ; if { command @ 0 } body start 1688 ; Motor 1 : 1689 ; desired_speed1 := desired_speed1 & 0xf0 | temp 1690 27c cf0 movlw 240 1691 27d 14f andwf desired_speed1,w 1692 27e 11b iorwf main__temp,w 1693 27f 02f movwf desired_speed1 1694 ; motor1_direction := command @ 1 1695 ; Alias variable for select command @ 1 1696 003a main__command__573select0 equ main__command+0 1697 003a main__command__573select0__byte equ main__command+0 1698 0001 main__command__573select0__bit equ 1 1699 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1700 280 4a4 bcf rp0___byte,rp0___bit 1701 ; Register bank is now 0 1702 281 47f bcf motor1_direction__byte,motor1_direction__bit 1703 ; Switch from register bank 0 to register bank 1 (which contains main__command__573select0__byte) 1704 282 5a4 bsf rp0___byte,rp0___bit 1705 ; Register bank is now 1 1706 283 443 bcf z___byte,z___bit 1707 284 63a btfsc main__command__573select0__byte,main__command__573select0__bit 1708 285 543 bsf z___byte,z___bit 1709 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1710 286 4a4 bcf rp0___byte,rp0___bit 1711 ; Register bank is now 0 1712 287 643 btfsc z___byte,z___bit 1713 288 57f bsf motor1_direction__byte,motor1_direction__bit 1714 ; if { command @ 0 } body end 1715 ; Switch from register bank 0 to register bank 1 1716 289 5a4 bsf rp0___byte,rp0___bit 1717 ; Register bank is now 1 1718 28a a99 goto label570__1end 1719 label570__1false: 1720 ; else body start 1721 ; Motor 0 : 1722 ; desired_speed0 := desired_speed0 & 0xf0 | temp 1723 28b cf0 movlw 240 1724 28c 14e andwf desired_speed0,w 1725 28d 11b iorwf main__temp,w 1726 28e 02e movwf desired_speed0 1727 ; motor0_direction := command @ 1 1728 ; Alias variable for select command @ 1 1729 003a main__command__577select0 equ main__command+0 1730 003a main__command__577select0__byte equ main__command+0 1731 0001 main__command__577select0__bit equ 1 1732 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1733 28f 4a4 bcf rp0___byte,rp0___bit 1734 ; Register bank is now 0 1735 290 45f bcf motor0_direction__byte,motor0_direction__bit 1736 ; Switch from register bank 0 to register bank 1 (which contains main__command__577select0__byte) 1737 291 5a4 bsf rp0___byte,rp0___bit 1738 ; Register bank is now 1 1739 292 443 bcf z___byte,z___bit 1740 293 63a btfsc main__command__577select0__byte,main__command__577select0__bit 1741 294 543 bsf z___byte,z___bit 1742 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1743 295 4a4 bcf rp0___byte,rp0___bit 1744 ; Register bank is now 0 1745 296 643 btfsc z___byte,z___bit 1746 297 55f bsf motor0_direction__byte,motor0_direction__bit 1747 ; else body end 1748 ; if exp=` command @ 0 ' generic 1749 ; Switch from register bank 0 to register bank 1 1750 298 5a4 bsf rp0___byte,rp0___bit 1751 ; Register bank is now 1 1752 label570__1end: 1753 ; Other expression=`{ command @ 0 }' delay=-1 1754 ; if { command @ 0 } end 1755 ; call set_up {{ }} 1756 ; Switch from register bank 1 to register bank 0 1757 299 4a4 bcf rp0___byte,rp0___bit 1758 ; Register bank is now 0 1759 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1760 29a 4a3 bcf pa0___byte,pa0___bit 1761 29b 985 call set_up 1762 ; Switch from register bank 0 to register bank 1 1763 29c 5a4 bsf rp0___byte,rp0___bit 1764 ; Register bank is now 1 1765 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1766 29d 5a3 bsf pa0___byte,pa0___bit 1767 29e be6 goto switch__553end 1768 switch__553block581: 1769 ; Command = 10 xx xxxx : 1770 ; switch { {{ command >> 3 }} & 7 } 1771 29f 31a rrf main__command,w 1772 2a0 03c movwf main__583byte0 1773 2a1 33c rrf main__583byte0,f 1774 2a2 31c rrf main__583byte0,w 1775 2a3 e07 andlw 7 1776 ; case 0 1777 ; case 1 1778 ; case 2 1779 ; case 3 1780 ; case 4 1781 ; case 5 1782 2a4 a1b goto switch__583block_start 1783 switch__583block584: 1784 ; Command = 1000 0 xxx : 1785 ; switch { command & 7 } 1786 2a5 c07 movlw 7 1787 2a6 15a andwf main__command,w 1788 ; case 0 1 1789 ; case 2 1790 ; case 3 1791 ; case 4 5 6 7 1792 2a7 a00 goto switch__586block_start 1793 switch__586block587: 1794 ; Set Ramp < Command = 1000 000 m > : 1795 ; temp := get_byte {{ }} 1796 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1797 2a8 4a3 bcf pa0___byte,pa0___bit 1798 2a9 93c call get_byte 1799 2aa 214 movf get_byte__0return__byte,w 1800 2ab 03b movwf main__temp 1801 ; if { command @ 0 } start 1802 ; Alias variable for select command @ 0 1803 003a main__command__590select0 equ main__command+0 1804 003a main__command__590select0__byte equ main__command+0 1805 0000 main__command__590select0__bit equ 0 1806 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=2 1807 ; Switch from code bank 0 to code bank 1 before possible transfer (btfss) 1808 2ac 5a3 bsf pa0___byte,pa0___bit 1809 2ad 71a btfss main__command__590select0__byte,main__command__590select0__bit 1810 2ae ab4 goto label590__1false 1811 label590__1true: 1812 ; if { command @ 0 } body start 1813 ; ramp1 := temp 1814 2af 21b movf main__temp,w 1815 ; Switch from register bank 1 to register bank 0 (which contains ramp1) 1816 2b0 4a4 bcf rp0___byte,rp0___bit 1817 ; Register bank is now 0 1818 2b1 031 movwf ramp1 1819 ; if { command @ 0 } body end 1820 ; Switch from register bank 0 to register bank 1 1821 2b2 5a4 bsf rp0___byte,rp0___bit 1822 ; Register bank is now 1 1823 2b3 ab8 goto label590__1end 1824 label590__1false: 1825 ; else body start 1826 ; ramp0 := temp 1827 2b4 21b movf main__temp,w 1828 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 1829 2b5 4a4 bcf rp0___byte,rp0___bit 1830 ; Register bank is now 0 1831 2b6 030 movwf ramp0 1832 ; else body end 1833 ; if exp=` command @ 0 ' generic 1834 ; Switch from register bank 0 to register bank 1 1835 2b7 5a4 bsf rp0___byte,rp0___bit 1836 ; Register bank is now 1 1837 label590__1end: 1838 ; Other expression=`{ command @ 0 }' delay=-1 1839 ; if { command @ 0 } end 1840 ; call set_up {{ }} 1841 ; Switch from register bank 1 to register bank 0 1842 2b8 4a4 bcf rp0___byte,rp0___bit 1843 ; Register bank is now 0 1844 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1845 2b9 4a3 bcf pa0___byte,pa0___bit 1846 2ba 985 call set_up 1847 ; Switch from register bank 0 to register bank 1 1848 2bb 5a4 bsf rp0___byte,rp0___bit 1849 ; Register bank is now 1 1850 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1851 2bc 5a3 bsf pa0___byte,pa0___bit 1852 2bd af3 goto switch__586end 1853 switch__586block597: 1854 ; Set Failsafe < Command = 1000 0010 > : 1855 ; fail_safe := get_byte {{ }} 1856 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1857 2be 4a3 bcf pa0___byte,pa0___bit 1858 2bf 93c call get_byte 1859 2c0 214 movf get_byte__0return__byte,w 1860 ; Switch from register bank 1 to register bank 0 (which contains fail_safe) 1861 2c1 4a4 bcf rp0___byte,rp0___bit 1862 ; Register bank is now 0 1863 2c2 036 movwf fail_safe 1864 ; fail_safe_high_counter := fail_safe 1865 2c3 038 movwf fail_safe_high_counter 1866 ; fail_safe_low_counter := 0 1867 2c4 079 clrf fail_safe_low_counter 1868 ; Switch from register bank 0 to register bank 1 1869 2c5 5a4 bsf rp0___byte,rp0___bit 1870 ; Register bank is now 1 1871 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1872 2c6 5a3 bsf pa0___byte,pa0___bit 1873 2c7 af3 goto switch__586end 1874 switch__586block603: 1875 ; Reset Failsafe < Command = 1000 0011 > : 1876 ; fail_safe_high_counter := fail_safe 1877 ; Switch from register bank 1 to register bank 0 (which contains fail_safe) 1878 2c8 4a4 bcf rp0___byte,rp0___bit 1879 ; Register bank is now 0 1880 2c9 216 movf fail_safe,w 1881 2ca 038 movwf fail_safe_high_counter 1882 ; fail_safe_low_counter := 0 1883 2cb 079 clrf fail_safe_low_counter 1884 ; Switch from register bank 0 to register bank 1 1885 2cc 5a4 bsf rp0___byte,rp0___bit 1886 ; Register bank is now 1 1887 2cd af3 goto switch__586end 1888 switch__586block608: 1889 ; Set Speed < Command = 1000 01 dm > : 1890 ; temp := get_byte {{ }} 1891 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1892 2ce 4a3 bcf pa0___byte,pa0___bit 1893 2cf 93c call get_byte 1894 2d0 214 movf get_byte__0return__byte,w 1895 2d1 03b movwf main__temp 1896 ; if { command @ 0 } start 1897 ; Alias variable for select command @ 0 1898 003a main__command__611select0 equ main__command+0 1899 003a main__command__611select0__byte equ main__command+0 1900 0000 main__command__611select0__bit equ 0 1901 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=5 false_delay=5 true_size=5 false_size=5 1902 ; Switch from code bank 0 to code bank 1 before possible transfer (btfss) 1903 2d2 5a3 bsf pa0___byte,pa0___bit 1904 2d3 71a btfss main__command__611select0__byte,main__command__611select0__bit 1905 2d4 ae2 goto label611__1false 1906 label611__1true: 1907 ; if { command @ 0 } body start 1908 ; Motor 1 : 1909 ; desired_speed1 := temp 1910 2d5 21b movf main__temp,w 1911 2d6 02f movwf desired_speed1 1912 ; motor1_direction := command @ 1 1913 ; Alias variable for select command @ 1 1914 003a main__command__614select0 equ main__command+0 1915 003a main__command__614select0__byte equ main__command+0 1916 0001 main__command__614select0__bit equ 1 1917 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1918 2d7 4a4 bcf rp0___byte,rp0___bit 1919 ; Register bank is now 0 1920 2d8 47f bcf motor1_direction__byte,motor1_direction__bit 1921 ; Switch from register bank 0 to register bank 1 (which contains main__command__614select0__byte) 1922 2d9 5a4 bsf rp0___byte,rp0___bit 1923 ; Register bank is now 1 1924 2da 443 bcf z___byte,z___bit 1925 2db 63a btfsc main__command__614select0__byte,main__command__614select0__bit 1926 2dc 543 bsf z___byte,z___bit 1927 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1928 2dd 4a4 bcf rp0___byte,rp0___bit 1929 ; Register bank is now 0 1930 2de 643 btfsc z___byte,z___bit 1931 2df 57f bsf motor1_direction__byte,motor1_direction__bit 1932 ; if { command @ 0 } body end 1933 ; Switch from register bank 0 to register bank 1 1934 2e0 5a4 bsf rp0___byte,rp0___bit 1935 ; Register bank is now 1 1936 2e1 aee goto label611__1end 1937 label611__1false: 1938 ; else body start 1939 ; Motor 0 : 1940 ; desired_speed0 := temp 1941 2e2 21b movf main__temp,w 1942 2e3 02e movwf desired_speed0 1943 ; motor0_direction := command @ 1 1944 ; Alias variable for select command @ 1 1945 003a main__command__618select0 equ main__command+0 1946 003a main__command__618select0__byte equ main__command+0 1947 0001 main__command__618select0__bit equ 1 1948 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1949 2e4 4a4 bcf rp0___byte,rp0___bit 1950 ; Register bank is now 0 1951 2e5 45f bcf motor0_direction__byte,motor0_direction__bit 1952 ; Switch from register bank 0 to register bank 1 (which contains main__command__618select0__byte) 1953 2e6 5a4 bsf rp0___byte,rp0___bit 1954 ; Register bank is now 1 1955 2e7 443 bcf z___byte,z___bit 1956 2e8 63a btfsc main__command__618select0__byte,main__command__618select0__bit 1957 2e9 543 bsf z___byte,z___bit 1958 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1959 2ea 4a4 bcf rp0___byte,rp0___bit 1960 ; Register bank is now 0 1961 2eb 643 btfsc z___byte,z___bit 1962 2ec 55f bsf motor0_direction__byte,motor0_direction__bit 1963 ; else body end 1964 ; if exp=` command @ 0 ' generic 1965 ; Switch from register bank 0 to register bank 1 1966 2ed 5a4 bsf rp0___byte,rp0___bit 1967 ; Register bank is now 1 1968 label611__1end: 1969 ; Other expression=`{ command @ 0 }' delay=-1 1970 ; if { command @ 0 } end 1971 ; call set_up {{ }} 1972 ; Switch from register bank 1 to register bank 0 1973 2ee 4a4 bcf rp0___byte,rp0___bit 1974 ; Register bank is now 0 1975 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1976 2ef 4a3 bcf pa0___byte,pa0___bit 1977 2f0 985 call set_up 1978 ; Switch from register bank 0 to register bank 1 1979 2f1 5a4 bsf rp0___byte,rp0___bit 1980 ; Register bank is now 1 1981 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1982 2f2 5a3 bsf pa0___byte,pa0___bit 1983 switch__586end: 1984 2f3 baf goto switch__583end 1985 switch__583block624: 1986 ; Command = 1000 1 xxx : 1987 ; if { command @ 2 } start 1988 ; Alias variable for select command @ 2 1989 003a main__command__626select0 equ main__command+0 1990 003a main__command__626select0__byte equ main__command+0 1991 0002 main__command__626select0__bit equ 2 1992 ; expression=`{ command @ 2 }' exp_delay=0 true_delay=-1 false_delay=-1 true_size=9 false_size=9 1993 2f4 75a btfss main__command__626select0__byte,main__command__626select0__bit 1994 2f5 b0e goto label626__1false 1995 label626__1true: 1996 ; if { command @ 2 } body start 1997 ; Set direction < Command = 1000 11 dm > : 1998 ; if { command @ 0 } start 1999 ; Alias variable for select command @ 0 2000 003a main__command__628select0 equ main__command+0 2001 003a main__command__628select0__byte equ main__command+0 2002 0000 main__command__628select0__bit equ 0 2003 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=3 true_size=3 false_size=3 2004 2f6 71a btfss main__command__628select0__byte,main__command__628select0__bit 2005 2f7 b03 goto label628__1false 2006 label628__1true: 2007 ; if { command @ 0 } body start 2008 ; Motor 1 : 2009 ; motor1_direction := command @ 1 2010 ; Alias variable for select command @ 1 2011 003a main__command__630select0 equ main__command+0 2012 003a main__command__630select0__byte equ main__command+0 2013 0001 main__command__630select0__bit equ 1 2014 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2015 2f8 4a4 bcf rp0___byte,rp0___bit 2016 ; Register bank is now 0 2017 2f9 47f bcf motor1_direction__byte,motor1_direction__bit 2018 ; Switch from register bank 0 to register bank 1 (which contains main__command__630select0__byte) 2019 2fa 5a4 bsf rp0___byte,rp0___bit 2020 ; Register bank is now 1 2021 2fb 443 bcf z___byte,z___bit 2022 2fc 63a btfsc main__command__630select0__byte,main__command__630select0__bit 2023 2fd 543 bsf z___byte,z___bit 2024 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2025 2fe 4a4 bcf rp0___byte,rp0___bit 2026 ; Register bank is now 0 2027 2ff 643 btfsc z___byte,z___bit 2028 300 57f bsf motor1_direction__byte,motor1_direction__bit 2029 ; if { command @ 0 } body end 2030 ; Switch from register bank 0 to register bank 1 2031 301 5a4 bsf rp0___byte,rp0___bit 2032 ; Register bank is now 1 2033 302 b0d goto label628__1end 2034 label628__1false: 2035 ; else body start 2036 ; Motor 0 : 2037 ; motor0_direction := command @ 1 2038 ; Alias variable for select command @ 1 2039 003a main__command__633select0 equ main__command+0 2040 003a main__command__633select0__byte equ main__command+0 2041 0001 main__command__633select0__bit equ 1 2042 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2043 303 4a4 bcf rp0___byte,rp0___bit 2044 ; Register bank is now 0 2045 304 45f bcf motor0_direction__byte,motor0_direction__bit 2046 ; Switch from register bank 0 to register bank 1 (which contains main__command__633select0__byte) 2047 305 5a4 bsf rp0___byte,rp0___bit 2048 ; Register bank is now 1 2049 306 443 bcf z___byte,z___bit 2050 307 63a btfsc main__command__633select0__byte,main__command__633select0__bit 2051 308 543 bsf z___byte,z___bit 2052 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2053 309 4a4 bcf rp0___byte,rp0___bit 2054 ; Register bank is now 0 2055 30a 643 btfsc z___byte,z___bit 2056 30b 55f bsf motor0_direction__byte,motor0_direction__bit 2057 ; else body end 2058 ; if exp=` command @ 0 ' generic 2059 ; Switch from register bank 0 to register bank 1 2060 30c 5a4 bsf rp0___byte,rp0___bit 2061 ; Register bank is now 1 2062 label628__1end: 2063 ; Other expression=`{ command @ 0 }' delay=-1 2064 ; if { command @ 0 } end 2065 ; if { command @ 2 } body end 2066 30d b25 goto label626__1end 2067 label626__1false: 2068 ; else body start 2069 ; Set mode < Command = 1000 10 xm > : 2070 ; if { command @ 0 } start 2071 ; Alias variable for select command @ 0 2072 003a main__command__637select0 equ main__command+0 2073 003a main__command__637select0__byte equ main__command+0 2074 0000 main__command__637select0__bit equ 0 2075 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=3 true_size=3 false_size=3 2076 30e 71a btfss main__command__637select0__byte,main__command__637select0__bit 2077 30f b1b goto label637__1false 2078 label637__1true: 2079 ; if { command @ 0 } body start 2080 ; Motor 1 : 2081 ; motor1_mode := command @ 1 2082 ; Alias variable for select command @ 1 2083 003a main__command__639select0 equ main__command+0 2084 003a main__command__639select0__byte equ main__command+0 2085 0001 main__command__639select0__bit equ 1 2086 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2087 310 4a4 bcf rp0___byte,rp0___bit 2088 ; Register bank is now 0 2089 311 43f bcf motor1_mode__byte,motor1_mode__bit 2090 ; Switch from register bank 0 to register bank 1 (which contains main__command__639select0__byte) 2091 312 5a4 bsf rp0___byte,rp0___bit 2092 ; Register bank is now 1 2093 313 443 bcf z___byte,z___bit 2094 314 63a btfsc main__command__639select0__byte,main__command__639select0__bit 2095 315 543 bsf z___byte,z___bit 2096 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2097 316 4a4 bcf rp0___byte,rp0___bit 2098 ; Register bank is now 0 2099 317 643 btfsc z___byte,z___bit 2100 318 53f bsf motor1_mode__byte,motor1_mode__bit 2101 ; if { command @ 0 } body end 2102 ; Switch from register bank 0 to register bank 1 2103 319 5a4 bsf rp0___byte,rp0___bit 2104 ; Register bank is now 1 2105 31a b25 goto label637__1end 2106 label637__1false: 2107 ; else body start 2108 ; Motor 0 : 2109 ; motor0_mode := command @ 1 2110 ; Alias variable for select command @ 1 2111 003a main__command__642select0 equ main__command+0 2112 003a main__command__642select0__byte equ main__command+0 2113 0001 main__command__642select0__bit equ 1 2114 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2115 31b 4a4 bcf rp0___byte,rp0___bit 2116 ; Register bank is now 0 2117 31c 41f bcf motor0_mode__byte,motor0_mode__bit 2118 ; Switch from register bank 0 to register bank 1 (which contains main__command__642select0__byte) 2119 31d 5a4 bsf rp0___byte,rp0___bit 2120 ; Register bank is now 1 2121 31e 443 bcf z___byte,z___bit 2122 31f 63a btfsc main__command__642select0__byte,main__command__642select0__bit 2123 320 543 bsf z___byte,z___bit 2124 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2125 321 4a4 bcf rp0___byte,rp0___bit 2126 ; Register bank is now 0 2127 322 643 btfsc z___byte,z___bit 2128 323 51f bsf motor0_mode__byte,motor0_mode__bit 2129 ; else body end 2130 ; if exp=` command @ 0 ' generic 2131 ; Switch from register bank 0 to register bank 1 2132 324 5a4 bsf rp0___byte,rp0___bit 2133 ; Register bank is now 1 2134 label637__1end: 2135 ; Other expression=`{ command @ 0 }' delay=-1 2136 ; if { command @ 0 } end 2137 ; else body end 2138 ; if exp=` command @ 2 ' generic 2139 label626__1end: 2140 ; Other expression=`{ command @ 2 }' delay=-1 2141 ; if { command @ 2 } end 2142 ; call set_up {{ }} 2143 ; Switch from register bank 1 to register bank 0 2144 325 4a4 bcf rp0___byte,rp0___bit 2145 ; Register bank is now 0 2146 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2147 326 4a3 bcf pa0___byte,pa0___bit 2148 327 985 call set_up 2149 ; Switch from register bank 0 to register bank 1 2150 328 5a4 bsf rp0___byte,rp0___bit 2151 ; Register bank is now 1 2152 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2153 329 5a3 bsf pa0___byte,pa0___bit 2154 32a baf goto switch__583end 2155 switch__583block647: 2156 ; Set Prescaler < Command = 1001 0 ppp > : 2157 ; option := option_mask | {{ command & 7 }} 2158 32b c07 movlw 7 2159 32c 15a andwf main__command,w 2160 32d dc0 iorlw 192 2161 32e 032 movwf option 2162 ; inline assembly statements begin 2163 32f 002 option 2164 ; inline assembly statements end 2165 330 baf goto switch__583end 2166 switch__583block655: 2167 ; Command = 1001 1 xxx : 2168 ; switch { command & 7 } 2169 331 c07 movlw 7 2170 332 15a andwf main__command,w 2171 ; case 0 2172 ; case 1 2173 ; case 2 3 2174 ; case 4 5 2175 ; case 6 7 2176 333 a09 goto switch__657block_start 2177 switch__657block658: 2178 ; Read Failsafe < Command = 1001 1000 > : 2179 ; call send_byte {{ fail_safe }} 2180 ; Switch from register bank 1 to register bank 0 (which contains fail_safe) 2181 334 4a4 bcf rp0___byte,rp0___bit 2182 ; Register bank is now 0 2183 335 216 movf fail_safe,w 2184 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2185 336 5a4 bsf rp0___byte,rp0___bit 2186 ; Register bank is now 1 2187 337 038 movwf send_byte__char 2188 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2189 338 4a3 bcf pa0___byte,pa0___bit 2190 339 962 call send_byte 2191 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2192 33a 5a3 bsf pa0___byte,pa0___bit 2193 33b b79 goto switch__657end 2194 switch__657block662: 2195 ; Read Prescaler < Command = 1001 1001 > : 2196 ; call send_byte {{ option & 7 }} 2197 33c c07 movlw 7 2198 33d 152 andwf option,w 2199 33e 038 movwf send_byte__char 2200 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2201 33f 4a3 bcf pa0___byte,pa0___bit 2202 340 962 call send_byte 2203 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2204 341 5a3 bsf pa0___byte,pa0___bit 2205 342 b79 goto switch__657end 2206 switch__657block666: 2207 ; Read Speed < Command = 1001 101 m > : 2208 ; if { command @ 0 } start 2209 ; Alias variable for select command @ 0 2210 003a main__command__668select0 equ main__command+0 2211 003a main__command__668select0__byte equ main__command+0 2212 0000 main__command__668select0__bit equ 0 2213 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=-1 false_delay=-1 true_size=1 false_size=1 2214 343 61a btfsc main__command__668select0__byte,main__command__668select0__bit 2215 ; if { command @ 0 } body start 2216 ; call send_byte {{ actual_speed1 }} 2217 344 209 movf actual_speed1,w 2218 ; 2 instructions found for sharing 2219 345 71a btfss main__command__668select0__byte,main__command__668select0__bit 2220 ; else body start 2221 ; call send_byte {{ actual_speed0 }} 2222 346 208 movf actual_speed0,w 2223 ; 2 instructions found for sharing 2224 ; if exp=` command @ 0 ' single true and false skip delay=4 2225 ; Other expression=`{ command @ 0 }' delay=4 2226 ; 2 shared instructions follow 2227 347 038 movwf send_byte__char 2228 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2229 348 4a3 bcf pa0___byte,pa0___bit 2230 349 962 call send_byte 2231 ; if { command @ 0 } end 2232 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2233 34a 5a3 bsf pa0___byte,pa0___bit 2234 34b b79 goto switch__657end 2235 switch__657block674: 2236 ; Read Mode / Direction < Command = 1001 110 m > : 2237 ; temp := 0 2238 34c 07b clrf main__temp 2239 ; if { command @ 0 } start 2240 ; Alias variable for select command @ 0 2241 003a main__command__677select0 equ main__command+0 2242 003a main__command__677select0__byte equ main__command+0 2243 0000 main__command__677select0__bit equ 0 2244 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 2245 34d 71a btfss main__command__677select0__byte,main__command__677select0__bit 2246 34e b58 goto label677__1false 2247 label677__1true: 2248 ; if { command @ 0 } body start 2249 ; Motor 1 : 2250 ; if { motor1_direction } start 2251 ; expression=`{ motor1_direction }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2252 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2253 34f 4a4 bcf rp0___byte,rp0___bit 2254 ; Register bank is now 0 2255 350 67f btfsc motor1_direction__byte,motor1_direction__bit 2256 ; if { motor1_direction } body start 2257 ; temp @ 1 := 1 2258 ; Select temp @ 1 2259 003b main__temp__680select0 equ main__temp+0 2260 003b main__temp__680select0__byte equ main__temp+0 2261 0001 main__temp__680select0__bit equ 1 2262 ; Switch from register bank 0 to register bank 1 (which contains main__temp__680select0__byte) 2263 351 5a4 bsf rp0___byte,rp0___bit 2264 ; Register bank is now 1 2265 352 53b bsf main__temp__680select0__byte,main__temp__680select0__bit 2266 ; if { motor1_direction } body end 2267 ; if exp=`motor1_direction' false skip delay=2 2268 ; Other expression=`{ motor1_direction }' delay=2 2269 ; if { motor1_direction } end 2270 ; if { motor1_mode } start 2271 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2272 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2273 353 4a4 bcf rp0___byte,rp0___bit 2274 ; Register bank is now 0 2275 354 63f btfsc motor1_mode__byte,motor1_mode__bit 2276 ; if { motor1_mode } body start 2277 ; temp @ 0 := 1 2278 ; Select temp @ 0 2279 003b main__temp__683select0 equ main__temp+0 2280 003b main__temp__683select0__byte equ main__temp+0 2281 0000 main__temp__683select0__bit equ 0 2282 ; Switch from register bank 0 to register bank 1 (which contains main__temp__683select0__byte) 2283 355 5a4 bsf rp0___byte,rp0___bit 2284 ; Register bank is now 1 2285 356 51b bsf main__temp__683select0__byte,main__temp__683select0__bit 2286 ; if { motor1_mode } body end 2287 ; if exp=`motor1_mode' false skip delay=2 2288 ; Other expression=`{ motor1_mode }' delay=2 2289 ; if { motor1_mode } end 2290 ; if { command @ 0 } body end 2291 357 b60 goto label677__1end 2292 label677__1false: 2293 ; else body start 2294 ; Motor 0 : 2295 ; if { motor0_direction } start 2296 ; expression=`{ motor0_direction }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2297 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2298 358 4a4 bcf rp0___byte,rp0___bit 2299 ; Register bank is now 0 2300 359 65f btfsc motor0_direction__byte,motor0_direction__bit 2301 ; if { motor0_direction } body start 2302 ; temp @ 1 := 1 2303 ; Select temp @ 1 2304 003b main__temp__688select0 equ main__temp+0 2305 003b main__temp__688select0__byte equ main__temp+0 2306 0001 main__temp__688select0__bit equ 1 2307 ; Switch from register bank 0 to register bank 1 (which contains main__temp__688select0__byte) 2308 35a 5a4 bsf rp0___byte,rp0___bit 2309 ; Register bank is now 1 2310 35b 53b bsf main__temp__688select0__byte,main__temp__688select0__bit 2311 ; if { motor0_direction } body end 2312 ; if exp=`motor0_direction' false skip delay=2 2313 ; Other expression=`{ motor0_direction }' delay=2 2314 ; if { motor0_direction } end 2315 ; if { motor0_mode } start 2316 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2317 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2318 35c 4a4 bcf rp0___byte,rp0___bit 2319 ; Register bank is now 0 2320 35d 61f btfsc motor0_mode__byte,motor0_mode__bit 2321 ; if { motor0_mode } body start 2322 ; temp @ 0 := 1 2323 ; Select temp @ 0 2324 003b main__temp__691select0 equ main__temp+0 2325 003b main__temp__691select0__byte equ main__temp+0 2326 0000 main__temp__691select0__bit equ 0 2327 ; Switch from register bank 0 to register bank 1 (which contains main__temp__691select0__byte) 2328 35e 5a4 bsf rp0___byte,rp0___bit 2329 ; Register bank is now 1 2330 35f 51b bsf main__temp__691select0__byte,main__temp__691select0__bit 2331 ; if { motor0_mode } body end 2332 ; if exp=`motor0_mode' false skip delay=2 2333 ; Other expression=`{ motor0_mode }' delay=2 2334 ; if { motor0_mode } end 2335 ; else body end 2336 ; if exp=` command @ 0 ' generic 2337 label677__1end: 2338 ; Other expression=`{ command @ 0 }' delay=-1 2339 ; if { command @ 0 } end 2340 ; call send_byte {{ temp }} 2341 360 21b movf main__temp,w 2342 361 038 movwf send_byte__char 2343 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2344 362 4a3 bcf pa0___byte,pa0___bit 2345 363 962 call send_byte 2346 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2347 364 5a3 bsf pa0___byte,pa0___bit 2348 365 b79 goto switch__657end 2349 switch__657block696: 2350 ; Read Ramp < Command = 1001 101 m > : 2351 ; if { command @ 0 } start 2352 ; Alias variable for select command @ 0 2353 003a main__command__698select0 equ main__command+0 2354 003a main__command__698select0__byte equ main__command+0 2355 0000 main__command__698select0__bit equ 0 2356 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 2357 366 443 bcf z___byte,z___bit 2358 367 61a btfsc main__command__698select0__byte,main__command__698select0__bit 2359 368 543 bsf z___byte,z___bit 2360 ; if { command @ 0 } body start 2361 ; temp := ramp1 2362 ; Switch from register bank 1 to register bank 0 (which contains ramp1) 2363 369 4a4 bcf rp0___byte,rp0___bit 2364 ; Register bank is now 0 2365 36a 643 btfsc z___byte,z___bit 2366 36b 211 movf ramp1,w 2367 ; 1 instructions found for sharing 2368 ; Switch from register bank 0 to register bank 1 (which contains main__command__698select0__byte) 2369 36c 5a4 bsf rp0___byte,rp0___bit 2370 ; Register bank is now 1 2371 36d 443 bcf z___byte,z___bit 2372 36e 61a btfsc main__command__698select0__byte,main__command__698select0__bit 2373 36f 543 bsf z___byte,z___bit 2374 ; else body start 2375 ; temp := ramp0 2376 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 2377 370 4a4 bcf rp0___byte,rp0___bit 2378 ; Register bank is now 0 2379 371 743 btfss z___byte,z___bit 2380 372 210 movf ramp0,w 2381 ; 1 instructions found for sharing 2382 ; if exp=` command @ 0 ' single true and false skip delay=4 2383 ; Other expression=`{ command @ 0 }' delay=4 2384 ; 1 shared instructions follow 2385 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 2386 373 5a4 bsf rp0___byte,rp0___bit 2387 ; Register bank is now 1 2388 374 03b movwf main__temp 2389 ; if { command @ 0 } end 2390 ; call send_byte {{ temp }} 2391 375 038 movwf send_byte__char 2392 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2393 376 4a3 bcf pa0___byte,pa0___bit 2394 377 962 call send_byte 2395 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2396 378 5a3 bsf pa0___byte,pa0___bit 2397 switch__657end: 2398 379 baf goto switch__583end 2399 switch__583block707: 2400 ; Command = 0110 0 xxx : 2401 ; switch { command & 7 } 2402 37a c07 movlw 7 2403 37b 15a andwf main__command,w 2404 ; case 0 2405 ; case 1 2406 ; case 2 2407 ; case 3 2408 ; case 4 2409 ; case 5 2410 ; case 6 2411 ; case 7 2412 37c a12 goto switch__709block_start 2413 switch__709block710: 2414 ; Read Failsafe Errors < Command = 1010 0000 > : 2415 ; call send_byte {{ fail_safe_errors }} 2416 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_errors) 2417 37d 4a4 bcf rp0___byte,rp0___bit 2418 ; Register bank is now 0 2419 37e 217 movf fail_safe_errors,w 2420 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2421 37f 5a4 bsf rp0___byte,rp0___bit 2422 ; Register bank is now 1 2423 380 038 movwf send_byte__char 2424 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2425 381 4a3 bcf pa0___byte,pa0___bit 2426 382 962 call send_byte 2427 ; fail_safe_errors := 0 2428 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_errors) 2429 383 4a4 bcf rp0___byte,rp0___bit 2430 ; Register bank is now 0 2431 384 077 clrf fail_safe_errors 2432 ; Switch from register bank 0 to register bank 1 2433 385 5a4 bsf rp0___byte,rp0___bit 2434 ; Register bank is now 1 2435 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2436 386 5a3 bsf pa0___byte,pa0___bit 2437 387 ba3 goto switch__709end 2438 switch__709block715: 2439 ; Read Failsafe Counter < Command = 1010 0001 > : 2440 ; call send_byte {{ fail_safe_high_counter }} 2441 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_high_counter) 2442 388 4a4 bcf rp0___byte,rp0___bit 2443 ; Register bank is now 0 2444 389 218 movf fail_safe_high_counter,w 2445 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2446 38a 5a4 bsf rp0___byte,rp0___bit 2447 ; Register bank is now 1 2448 38b 038 movwf send_byte__char 2449 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2450 38c 4a3 bcf pa0___byte,pa0___bit 2451 38d 962 call send_byte 2452 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2453 38e 5a3 bsf pa0___byte,pa0___bit 2454 38f ba3 goto switch__709end 2455 switch__709block719: 2456 ; Read Actual Speed 0 < Command = 1010 0010 > : 2457 ; call send_byte {{ actual_speed0 }} 2458 390 208 movf actual_speed0,w 2459 391 038 movwf send_byte__char 2460 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2461 392 4a3 bcf pa0___byte,pa0___bit 2462 393 962 call send_byte 2463 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2464 394 5a3 bsf pa0___byte,pa0___bit 2465 395 ba3 goto switch__709end 2466 switch__709block723: 2467 ; Read Actual Speed 1 < Command = 1010 0011 > : 2468 ; call send_byte {{ actual_speed1 }} 2469 396 209 movf actual_speed1,w 2470 397 038 movwf send_byte__char 2471 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2472 398 4a3 bcf pa0___byte,pa0___bit 2473 399 962 call send_byte 2474 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2475 39a 5a3 bsf pa0___byte,pa0___bit 2476 39b ba3 goto switch__709end 2477 switch__709block727: 2478 ; Set Motor 0 off < Command = 1010 0100 > : 2479 ; motor0e := 0 2480 39c 447 bcf motor0e__byte,motor0e__bit 2481 39d ba3 goto switch__709end 2482 switch__709block731: 2483 ; Set Motor 0 on < Command = 1010 0101 > : 2484 ; motor0e := 1 2485 39e 547 bsf motor0e__byte,motor0e__bit 2486 39f ba3 goto switch__709end 2487 switch__709block735: 2488 ; Set Motor 1 off < Command = 1010 0110 > : 2489 ; motor1e := 0 2490 3a0 467 bcf motor1e__byte,motor1e__bit 2491 3a1 ba3 goto switch__709end 2492 switch__709block739: 2493 ; Set Motor 1 on < Command = 1010 0111 > : 2494 ; motor1e := 1 2495 3a2 567 bsf motor1e__byte,motor1e__bit 2496 switch__709end: 2497 3a3 baf goto switch__583end 2498 switch__583block745: 2499 ; if { command & 3 = 0 } start 2500 3a4 c03 movlw 3 2501 3a5 15a andwf main__command,w 2502 ; expression=`{ command & 3 = 0 }' exp_delay=2 true_delay=-1 false_delay=0 true_size=2 false_size=0 2503 3a6 743 btfss z___byte,z___bit 2504 3a7 bae goto label746__0end 2505 ; if { command & 3 = 0 } body start 2506 ; FIXME : Code generator chokes on single call instruction 2507 ; in the then clause . Add ' ramp0 := 0 ' to work around ! ! ! 2508 ; ramp0 := 0 2509 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 2510 3a8 4a4 bcf rp0___byte,rp0___bit 2511 ; Register bank is now 0 2512 3a9 070 clrf ramp0 2513 ; call reset {{ }} 2514 ; Switch from register bank 0 to register bank 1 2515 3aa 5a4 bsf rp0___byte,rp0___bit 2516 ; Register bank is now 1 2517 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2518 3ab 4a3 bcf pa0___byte,pa0___bit 2519 3ac 9cb call reset 2520 ; if { command & 3 = 0 } body end 2521 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 2522 3ad 5a3 bsf pa0___byte,pa0___bit 2523 label746__0end: 2524 ; if exp=` command & 3 = 0 ' empty false 2525 ; Other expression=`{ command & 3 = 0 }' delay=-1 2526 ; if { command & 3 = 0 } end 2527 3ae baf goto switch__583end 2528 switch__583default753: 2529 ; Do nothing : 2530 switch__583end: 2531 3af be6 goto switch__553end 2532 switch__553block758: 2533 ; Command = 11 xx xxxx : 2534 ; switch { {{ command >> 3 }} & 7 } 2535 3b0 31a rrf main__command,w 2536 3b1 03c movwf main__760byte0 2537 3b2 33c rrf main__760byte0,f 2538 3b3 31c rrf main__760byte0,w 2539 3b4 e07 andlw 7 2540 ; case 7 2541 3b5 a2d goto switch__760block_start 2542 switch__760block761: 2543 ; Shared commands < Command = 1111 1 ccc > : 2544 ; switch { command & 7 } 2545 3b6 c07 movlw 7 2546 3b7 15a andwf main__command,w 2547 ; case 0 2548 ; case 1 2549 ; case 2 2550 ; case 3 2551 ; case 4 2552 ; case 5 2553 ; case 6 2554 ; case 7 2555 3b8 a24 goto switch__763block_start 2556 switch__763block764: 2557 ; Clock Decrement < Command = 1111 1000 > : 2558 ; osccal := osccal - osccal_unit 2559 3b9 cfc movlw 252 2560 3ba 1e5 addwf osccal,f 2561 3bb be6 goto switch__763end 2562 switch__763block768: 2563 ; Clock Increment < Command = 1111 1001 > : 2564 ; osccal := osccal + osccal_unit 2565 3bc c04 movlw 4 2566 3bd 1e5 addwf osccal,f 2567 3be be6 goto switch__763end 2568 switch__763block772: 2569 ; Clock Read < Command = 1111 1010 > : 2570 ; call send_byte {{ osccal }} 2571 3bf 205 movf osccal,w 2572 3c0 038 movwf send_byte__char 2573 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2574 3c1 4a3 bcf pa0___byte,pa0___bit 2575 3c2 962 call send_byte 2576 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2577 3c3 5a3 bsf pa0___byte,pa0___bit 2578 3c4 be6 goto switch__763end 2579 switch__763block776: 2580 ; Clock Pulse < Command = 1111 1011 > : 2581 ; call send_byte {{ 0 }} 2582 3c5 078 clrf send_byte__char 2583 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2584 3c6 4a3 bcf pa0___byte,pa0___bit 2585 3c7 962 call send_byte 2586 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2587 3c8 5a3 bsf pa0___byte,pa0___bit 2588 3c9 be6 goto switch__763end 2589 switch__763block780: 2590 ; ID Next < Command = 1111 1100 > : 2591 ; if { id_index >= id . size } start 2592 3ca c30 movlw 48 2593 3cb 091 subwf id_index,w 2594 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2595 3cc 603 btfsc c___byte,c___bit 2596 ; if { id_index >= id . size } body start 2597 ; id_index := 0 2598 3cd 071 clrf id_index 2599 ; if { id_index >= id . size } body end 2600 ; if exp=` id_index >= id . size ' false skip delay=4 2601 ; Other expression=`{ id_index >= id . size }' delay=4 2602 ; if { id_index >= id . size } end 2603 ; call send_byte {{ id ~~ {{ id_index }} }} 2604 3ce 291 incf id_index,w 2605 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2606 3cf 4a3 bcf pa0___byte,pa0___bit 2607 3d0 90a call id 2608 3d1 038 movwf send_byte__char 2609 3d2 962 call send_byte 2610 ; id_index := id_index + 1 2611 3d3 2b1 incf id_index,f 2612 ; if { id_index >= id . size } start 2613 3d4 c30 movlw 48 2614 3d5 091 subwf id_index,w 2615 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2616 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) 2617 3d6 5a3 bsf pa0___byte,pa0___bit 2618 3d7 603 btfsc c___byte,c___bit 2619 ; if { id_index >= id . size } body start 2620 ; id_index := 0 2621 3d8 071 clrf id_index 2622 ; if { id_index >= id . size } body end 2623 ; if exp=` id_index >= id . size ' false skip delay=4 2624 ; Other expression=`{ id_index >= id . size }' delay=4 2625 ; if { id_index >= id . size } end 2626 3d9 be6 goto switch__763end 2627 switch__763block791: 2628 ; ID Reset < Command = 1111 1101 > : 2629 ; id_index := 0 2630 3da 071 clrf id_index 2631 3db be6 goto switch__763end 2632 switch__763block795: 2633 ; Glitch Read < Command = 1111 1110 > : 2634 ; call send_byte {{ glitch }} 2635 3dc 210 movf glitch,w 2636 3dd 038 movwf send_byte__char 2637 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2638 3de 4a3 bcf pa0___byte,pa0___bit 2639 3df 962 call send_byte 2640 ; glitch := 0 2641 3e0 070 clrf glitch 2642 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2643 3e1 5a3 bsf pa0___byte,pa0___bit 2644 3e2 be6 goto switch__763end 2645 switch__763block800: 2646 ; Glitch < Command = 1111 1111 > : 2647 ; if { glitch != 0xff } start 2648 3e3 290 incf glitch,w 2649 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 2650 3e4 743 btfss z___byte,z___bit 2651 ; if { glitch != 0xff } body start 2652 ; glitch := glitch + 1 2653 3e5 2b0 incf glitch,f 2654 ; if { glitch != 0xff } body end 2655 ; if exp=` glitch != 0xff ' false skip delay=3 2656 ; Other expression=`{ glitch != 0xff }' delay=3 2657 ; if { glitch != 0xff } end 2658 switch__763end: 2659 switch__760end: 2660 switch__553end: 2661 3e6 a3e goto main__548loop__forever 2662 ; loop_forever ... end 2663 ; procedure main end 2664 2665 ; Register bank 0 used 23 bytes of 24 available bytes 2666 ; Register bank 1 used 14 bytes of 16 available bytes 2667 ; Register bank 2 used 0 bytes of 16 available bytes 2668 ; Register bank 3 used 0 bytes of 16 available bytes 2669 2670 end