1 radix dec 2 0008 global__variables__bank0 equ 8 3 0030 global__variables__bank1 equ 48 4 0050 global__variables__bank2 equ 80 5 0070 global__variables__bank3 equ 112 6 001e global__bit__variables__bank0 equ 30 7 003d global__bit__variables__bank1 equ 61 8 0050 global__bit__variables__bank2 equ 80 9 0070 global__bit__variables__bank3 equ 112 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 17 0004 rp0___byte equ 4 18 0005 rp0___bit equ 5 19 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 20 0004 rp1___byte equ 4 21 0006 rp1___bit equ 6 22 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 23 0003 pa0___byte equ 3 24 0005 pa0___bit equ 5 25 0004 fsr___register equ 4 26 org 0 27 start: 28 ; Use oscillator calibration value already in register W 29 000 025 movwf 5 30 ; Initialize TRIS registers 31 001 ccc movlw 204 32 002 006 tris 6 33 003 cf1 movlw 241 34 004 007 tris 7 35 ; Switch from register bank 0 to register bank 1 36 005 5a4 bsf rp0___byte,rp0___bit 37 ; Register bank is now 1 38 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 39 006 5a3 bsf pa0___byte,pa0___bit 40 007 a44 goto main 41 ; comment ############################################################################# 42 ; comment {} 43 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 44 ; comment {All rights reserved .} 45 ; comment {} 46 ; comment {Permission to use , copy , modify , distribute , and sell this software} 47 ; comment {for any purpose is hereby granted without fee provided that the above} 48 ; comment {copyright notice and this permission are retained . The author makes} 49 ; comment {no representations about the suitability of this software for any purpose .} 50 ; comment {It is provided { as is } without express or implied warranty .} 51 ; comment {} 52 ; comment {This is the code that implements the Motor2 RoboBrick . Basically} 53 ; comment {it just waits for commands that come in at 2400 baud and responds} 54 ; comment {to them . See :} 55 ; comment {} 56 ; comment {http : / / web . gramlich . net / projects / robobricks / motor2 / index . html} 57 ; comment {} 58 ; comment {for more details .} 59 ; comment {} 60 ; comment ############################################################################# 61 ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock 62 ; 4052=0xfd4 4095=0xfff 63 __config 4052 64 0fff configuration___address equ 4095 65 ; comment {Define processor constants :} 66 ; constant clock_rate 4000000 67 3d0900 clock_rate equ 4000000 68 ; constant clocks_per_instruction 4 69 0004 clocks_per_instruction equ 4 70 ; constant instruction_rate clock_rate / clocks_per_instruction 71 f4240 instruction_rate equ 1000000 72 ; comment {Define serial communication control constants :} 73 ; constant baud_rate 2400 74 0960 baud_rate equ 2400 75 ; constant instructions_per_bit instruction_rate / baud_rate 76 01a0 instructions_per_bit equ 416 77 ; constant delays_per_bit 3 78 0003 delays_per_bit equ 3 79 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 80 008a instructions_per_delay equ 138 81 ; comment {Most RoboBricks use 9 cycles per loop , but this one needs 12 :} 82 ; constant extra_instructions_per_bit 12 83 000c extra_instructions_per_bit equ 12 84 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 85 0004 extra_instructions_per_delay equ 4 86 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 87 0086 delay_instructions equ 134 88 ; comment {Register definitions :} 89 ; comment {TMR0 register :} 90 0001 tmr0 equ 1 91 ; comment {STATUS register :} 92 0003 status equ 3 93 ; bind c status @ 0 94 0003 c equ status+0 95 0003 c__byte equ status+0 96 0000 c__bit equ 0 97 ; bind z status @ 2 98 0003 z equ status+0 99 0003 z__byte equ status+0 100 0002 z__bit equ 2 101 ; comment {OSCCAL register :} 102 0005 osccal equ 5 103 ; constant osccal_unit 4 104 0004 osccal_unit equ 4 105 ; comment {On the 505 , the OPTION register is only setable via the option instrucition .} 106 ; constant rbwu_bit 7 107 0007 rbwu_bit equ 7 108 ; constant rbpu_bit 6 109 0006 rbpu_bit equ 6 110 ; constant t0cs_bit 5 111 0005 t0cs_bit equ 5 112 ; constant t0se_bit 4 113 0004 t0se_bit equ 4 114 ; constant psa_bit 3 115 0003 psa_bit equ 3 116 ; constant ps2_bit 2 117 0002 ps2_bit equ 2 118 ; constant ps1_bit 1 119 0001 ps1_bit equ 1 120 ; constant ps0_bit 0 121 0000 ps0_bit equ 0 122 ; constant rbuw_mask {{ 1 << rbwu_bit }} 123 0080 rbuw_mask equ 128 124 ; constant rbpu_mask {{ 1 << rbpu_bit }} 125 0040 rbpu_mask equ 64 126 ; constant t0cs_mask {{ 1 << t0cs_bit }} 127 0020 t0cs_mask equ 32 128 ; constant t0se_mask {{ 1 << t0se_bit }} 129 0010 t0se_mask equ 16 130 ; comment {Disable Wake - up and pull - ups {;} set timer to internal {;} edge_source to raising :} 131 ; constant option_mask rbuw_mask | rbpu_mask 132 00c0 option_mask equ 192 133 ; comment {Define port bit assignments} 134 ; constant motor0a_bit 0 135 0000 motor0a_bit equ 0 136 ; constant motor0b_bit 1 137 0001 motor0b_bit equ 1 138 ; constant motor1a_bit 4 139 0004 motor1a_bit equ 4 140 ; constant motor1b_bit 5 141 0005 motor1b_bit equ 5 142 ; constant serial_in_bit 0 143 0000 serial_in_bit equ 0 144 ; constant serial_out_bit 1 145 0001 serial_out_bit equ 1 146 ; constant motor0e_bit 2 147 0002 motor0e_bit equ 2 148 ; constant motor1e_bit 3 149 0003 motor1e_bit equ 3 150 0006 portb equ 6 151 0007 portc equ 7 152 0006 motor0a__byte equ 6 153 0000 motor0a__bit equ 0 154 0006 motor0b__byte equ 6 155 0001 motor0b__bit equ 1 156 0006 motor1a__byte equ 6 157 0004 motor1a__bit equ 4 158 0006 motor1b__byte equ 6 159 0005 motor1b__bit equ 5 160 0007 serial_in__byte equ 7 161 0000 serial_in__bit equ 0 162 0007 serial_out__byte equ 7 163 0001 serial_out__bit equ 1 164 0007 motor0e__byte equ 7 165 0002 motor0e__bit equ 2 166 0007 motor1e__byte equ 7 167 0003 motor1e__bit equ 3 168 ; constant motor0a_mask {{ 1 << motor0a_bit }} 169 0001 motor0a_mask equ 1 170 ; constant motor0b_mask {{ 1 << motor0b_bit }} 171 0002 motor0b_mask equ 2 172 ; constant motor1a_mask {{ 1 << motor1a_bit }} 173 0010 motor1a_mask equ 16 174 ; constant motor1b_mask {{ 1 << motor1b_bit }} 175 0020 motor1b_mask equ 32 176 ; constant serial_in_mask {{ 1 << serial_in_bit }} 177 0001 serial_in_mask equ 1 178 ; constant serial_out_mask {{ 1 << serial_out_bit }} 179 0002 serial_out_mask equ 2 180 ; constant motor0e_mask {{ 1 << motor0e_bit }} 181 0004 motor0e_mask equ 4 182 ; constant motor1e_mask {{ 1 << motor1e_bit }} 183 0008 motor1e_mask equ 8 184 ; comment {Define duty cycle and motor on / off masks :} 185 0008 actual_speed0 equ global__variables__bank0+0 186 0009 actual_speed1 equ global__variables__bank0+1 187 000a motor0_off equ global__variables__bank0+2 188 000b motor0_on equ global__variables__bank0+3 189 000c motor1_off equ global__variables__bank0+4 190 000d motor1_on equ global__variables__bank0+5 191 ; comment {Ramp variables :} 192 000e desired_speed0 equ global__variables__bank0+6 193 000f desired_speed1 equ global__variables__bank0+7 194 0010 ramp0 equ global__variables__bank0+8 195 0011 ramp1 equ global__variables__bank0+9 196 0012 ramp0_delay equ global__variables__bank0+10 197 0013 ramp1_delay equ global__variables__bank0+11 198 0014 ramp0_offset equ global__variables__bank0+12 199 0015 ramp1_offset equ global__variables__bank0+13 200 ; comment {Fail safe variables :} 201 0016 fail_safe equ global__variables__bank0+14 202 0017 fail_safe_errors equ global__variables__bank0+15 203 0018 fail_safe_high_counter equ global__variables__bank0+16 204 0019 fail_safe_low_counter equ global__variables__bank0+17 205 ; comment {Mode < pulsed vs . continuous > bits :} 206 001e motor0_mode equ global__bit__variables__bank0+0 207 001e motor0_mode__byte equ global__bit__variables__bank0+0 208 0000 motor0_mode__bit equ 0 209 001e motor1_mode equ global__bit__variables__bank0+0 210 001e motor1_mode__byte equ global__bit__variables__bank0+0 211 0001 motor1_mode__bit equ 1 212 001e motor0_direction equ global__bit__variables__bank0+0 213 001e motor0_direction__byte equ global__bit__variables__bank0+0 214 0002 motor0_direction__bit equ 2 215 001e motor1_direction equ global__bit__variables__bank0+0 216 001e motor1_direction__byte equ global__bit__variables__bank0+0 217 0003 motor1_direction__bit equ 3 218 ; bank 1 219 ; Default register bank is now 1 220 ; comment {Shared command registers and option :} 221 0030 glitch equ global__variables__bank1+0 222 0031 id_index equ global__variables__bank1+1 223 0032 option equ global__variables__bank1+2 224 ; string_constants Start 225 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 226 008 4a3 bcf pa0___byte,pa0___bit 227 string___fetch: 228 009 022 movwf pcl___register 229 ; id = 1 , 0 , 14 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'Motor2B' , 15 , 0s'Gramlich&Benson' 230 0000 id___string equ 0 231 id: 232 00a 1e2 addwf pcl___register,f 233 ; Length = 48 234 00b 830 retlw 48 235 ; 1 236 00c 801 retlw 1 237 ; 0 238 00d 800 retlw 0 239 ; 14 240 00e 80e retlw 14 241 ; 0 242 00f 800 retlw 0 243 ; 0 244 010 800 retlw 0 245 ; 0 246 011 800 retlw 0 247 ; 0 248 012 800 retlw 0 249 ; 0 250 013 800 retlw 0 251 ; 0r'16' 252 014 8bc retlw 188 ; random number 253 015 87c retlw 124 ; random number 254 016 8ff retlw 255 ; random number 255 017 860 retlw 96 ; random number 256 018 8cc retlw 204 ; random number 257 019 84f retlw 79 ; random number 258 01a 845 retlw 69 ; random number 259 01b 8ec retlw 236 ; random number 260 01c 86f retlw 111 ; random number 261 01d 8e2 retlw 226 ; random number 262 01e 8c9 retlw 201 ; random number 263 01f 85b retlw 91 ; random number 264 020 821 retlw 33 ; random number 265 021 80f retlw 15 ; random number 266 022 87d retlw 125 ; random number 267 023 889 retlw 137 ; random number 268 ; 7 269 024 807 retlw 7 270 ; `Motor2B' 271 025 84d retlw 77 272 026 86f retlw 111 273 027 874 retlw 116 274 028 86f retlw 111 275 029 872 retlw 114 276 02a 832 retlw 50 277 02b 842 retlw 66 278 ; 15 279 02c 80f retlw 15 280 ; `Gramlich&Benson' 281 02d 847 retlw 71 282 02e 872 retlw 114 283 02f 861 retlw 97 284 030 86d retlw 109 285 031 86c retlw 108 286 032 869 retlw 105 287 033 863 retlw 99 288 034 868 retlw 104 289 035 826 retlw 38 290 036 842 retlw 66 291 037 865 retlw 101 292 038 86e retlw 110 293 039 873 retlw 115 294 03a 86f retlw 111 295 03b 86e retlw 110 296 ; string__constants End 297 ; comment {For now put all the smaller routines first so that they can live} 298 ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} 299 ; comment {can only call routines that are within the first 256 bytes < i . e .} 300 ; comment {the first half > of the code page .} 301 ; bank 1 302 ; Default register bank is now 1 303 ; comment {Globals :} 304 003d receiving equ global__bit__variables__bank1+0 305 003d receiving__byte equ global__bit__variables__bank1+0 306 0000 receiving__bit equ 0 307 308 ; procedure get_byte start 309 get_byte: 310 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 311 ; Procedure must be called with PCLATH set to code bank 0 312 0033 get_byte__variables__base equ global__variables__bank1+3 313 0033 get_byte__bytes__base equ get_byte__variables__base+0 314 0036 get_byte__bits__base equ get_byte__variables__base+3 315 0004 get_byte__total__bytes equ 4 316 ; arguments_none 317 0033 get_byte__0return__byte equ get_byte__bytes__base+0 318 ; Wait for a character and return it . 319 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 320 ; way the next call to get_byte < > will sychronize on the start 321 ; bit instead of possibly starting a little later . 322 0034 get_byte__count equ get_byte__bytes__base+1 323 0035 get_byte__char equ get_byte__bytes__base+2 324 ; Wait for start bit : 325 ; receiving := 1 326 03c 51d bsf receiving__byte,receiving__bit 327 ; `while serial_in ...' start 328 get_byte__163while__continue: 329 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 330 03d 707 btfss serial_in__byte,serial_in__bit 331 03e a43 goto get_byte__163while__break 332 ; call delay {{ }} 333 ; Switch from register bank 1 to register bank 0 334 03f 4a4 bcf rp0___byte,rp0___bit 335 ; Register bank is now 0 336 040 9f4 call delay 337 ; Switch from register bank 0 to register bank 1 338 041 5a4 bsf rp0___byte,rp0___bit 339 ; Register bank is now 1 340 042 a3d goto get_byte__163while__continue 341 ; if exp=`serial_in' false goto 342 ; Other expression=`serial_in' delay=-1 343 get_byte__163while__break: 344 ; `while serial_in ...' end 345 ; 3 cycles to escape loop : 346 ; Skip over start bit : 347 ; 1 cycle to code bank switch : 348 ; call delay {{ }} 349 ; Switch from register bank 1 to register bank 0 350 043 4a4 bcf rp0___byte,rp0___bit 351 ; Register bank is now 0 352 044 9f4 call delay 353 ; call delay {{ }} 354 045 9f4 call delay 355 ; call delay {{ }} 356 046 9f4 call delay 357 ; 1 cycle to code bank switch back : 358 ; Sample in the middle third of each data bit : 359 ; 1 cycle : 360 ; char := 0 361 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 362 047 5a4 bsf rp0___byte,rp0___bit 363 ; Register bank is now 1 364 048 075 clrf get_byte__char 365 ; 2 cycles to set up loop : 366 ; 3 + 1 + 1 + 1 + 2 = 8 367 ; `count_down count 8 ...' start 368 049 c08 movlw 8 369 04a 034 movwf get_byte__count 370 get_byte__180_loop: 371 ; 1 cycle to code bank switch : 372 ; call delay {{ }} 373 ; Switch from register bank 1 to register bank 0 374 04b 4a4 bcf rp0___byte,rp0___bit 375 ; Register bank is now 0 376 04c 9f4 call delay 377 ; 1 cycle to code bank switch back : 378 ; 2 cycles : 379 ; char := char >> 1 380 04d 403 bcf c___byte,c___bit 381 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 382 04e 5a4 bsf rp0___byte,rp0___bit 383 ; Register bank is now 1 384 04f 335 rrf get_byte__char,f 385 ; 2 cycles : 386 ; if { serial_in } start 387 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 388 050 607 btfsc serial_in__byte,serial_in__bit 389 ; if { serial_in } body start 390 ; char @ 7 := 1 391 ; Select char @ 7 392 0035 get_byte__char__188select0 equ get_byte__char+0 393 0035 get_byte__char__188select0__byte equ get_byte__char+0 394 0007 get_byte__char__188select0__bit equ 7 395 051 5f5 bsf get_byte__char__188select0__byte,get_byte__char__188select0__bit 396 ; if { serial_in } body end 397 ; if exp=`serial_in' false skip delay=2 398 ; Other expression=`{ serial_in }' delay=2 399 ; if { serial_in } end 400 ; 1 cycle to code bank switch : 401 ; call delay {{ }} 402 ; Switch from register bank 1 to register bank 0 403 052 4a4 bcf rp0___byte,rp0___bit 404 ; Register bank is now 0 405 053 9f4 call delay 406 ; call delay {{ }} 407 054 9f4 call delay 408 ; 1 cycle to code bank switch back : 409 ; 3 cycles at end of loop for test and branch : 410 ; 1 + 1 + 2 + 2 + 1 + 1 + 3 = 11 411 ; nop extra_instructions_per_bit - 11 412 ; Delay 1 cycles 413 055 000 nop 414 ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) 415 056 5a4 bsf rp0___byte,rp0___bit 416 ; Register bank is now 1 417 057 2f4 decfsz get_byte__count,f 418 058 a4b goto get_byte__180_loop 419 get_byte__180_done: 420 ; `count_down count 8 ...' end 421 ; Skip over 2 / 3 ' s of stop bit : 422 ; call delay {{ }} 423 ; Switch from register bank 1 to register bank 0 424 059 4a4 bcf rp0___byte,rp0___bit 425 ; Register bank is now 0 426 05a 9f4 call delay 427 ; call delay {{ }} 428 05b 9f4 call delay 429 ; return char 430 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 431 05c 5a4 bsf rp0___byte,rp0___bit 432 ; Register bank is now 1 433 05d 215 movf get_byte__char,w 434 05e 033 movwf get_byte__0return__byte 435 05f 800 retlw 0 436 ; procedure get_byte end 437 438 ; procedure send_byte start 439 send_byte: 440 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 441 ; Procedure must be called with PCLATH set to code bank 0 442 0037 send_byte__variables__base equ global__variables__bank1+7 443 0037 send_byte__bytes__base equ send_byte__variables__base+0 444 003a send_byte__bits__base equ send_byte__variables__base+3 445 0003 send_byte__total__bytes equ 3 446 0039 send_byte__237byte1 equ send_byte__bytes__base+2 447 0037 send_byte__char equ send_byte__bytes__base+0 448 ; Send < char > to < tx > : 449 0038 send_byte__count equ send_byte__bytes__base+1 450 ; < receiving > will be 1 if the last get / put routine was a get . 451 ; Before we start transmitting a response back , we want to ensure 452 ; that there has been enough time to turn the line line around . 453 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 454 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 455 ; for good measure . Technically , the second call to delay < > 456 ; is not really needed . 457 ; if { receiving } start 458 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 459 060 71d btfss receiving__byte,receiving__bit 460 061 a67 goto label221__0end 461 ; if { receiving } body start 462 ; receiving := 0 463 062 41d bcf receiving__byte,receiving__bit 464 ; call delay {{ }} 465 ; Switch from register bank 1 to register bank 0 466 063 4a4 bcf rp0___byte,rp0___bit 467 ; Register bank is now 0 468 064 9f4 call delay 469 ; call delay {{ }} 470 065 9f4 call delay 471 ; if { receiving } body end 472 ; Switch from register bank 0 to register bank 1 473 066 5a4 bsf rp0___byte,rp0___bit 474 ; Register bank is now 1 475 label221__0end: 476 ; if exp=`receiving' empty false 477 ; Other expression=`{ receiving }' delay=-1 478 ; if { receiving } end 479 ; Send the start bit : 480 ; 1 cycle : 481 ; serial_out := 0 482 067 427 bcf serial_out__byte,serial_out__bit 483 ; 1 cycle for code bank switch : 484 ; call delay {{ }} 485 ; Switch from register bank 1 to register bank 0 486 068 4a4 bcf rp0___byte,rp0___bit 487 ; Register bank is now 0 488 069 9f4 call delay 489 ; call delay {{ }} 490 06a 9f4 call delay 491 ; call delay {{ }} 492 06b 9f4 call delay 493 ; 1 cycle for code bank switch : 494 ; 2 cycles for loop setup : 495 ; 1 + 1 + 1 + 2 = 5 496 ; nop extra_instructions_per_bit - 5 497 ; Delay 7 cycles 498 06c c02 movlw 2 499 ; Switch from register bank 0 to register bank 1 (which contains send_byte__237byte1) 500 06d 5a4 bsf rp0___byte,rp0___bit 501 ; Register bank is now 1 502 06e 039 movwf send_byte__237byte1 503 send_byte__237delay0: 504 06f 2f9 decfsz send_byte__237byte1,f 505 070 a6f goto send_byte__237delay0 506 ; Send the data : 507 ; `count_down count 8 ...' start 508 071 c08 movlw 8 509 072 038 movwf send_byte__count 510 send_byte__240_loop: 511 ; 4 cycles : 512 ; serial_out := char @ 0 513 ; Alias variable for select char @ 0 514 0037 send_byte__char__242select0 equ send_byte__char+0 515 0037 send_byte__char__242select0__byte equ send_byte__char+0 516 0000 send_byte__char__242select0__bit equ 0 517 073 717 btfss send_byte__char__242select0__byte,send_byte__char__242select0__bit 518 074 427 bcf serial_out__byte,serial_out__bit 519 075 617 btfsc send_byte__char__242select0__byte,send_byte__char__242select0__bit 520 076 527 bsf serial_out__byte,serial_out__bit 521 ; 2 cycles : 522 ; char := char >> 1 523 077 403 bcf c___byte,c___bit 524 078 337 rrf send_byte__char,f 525 ; 1 cycle for code bank switch : 526 ; call delay {{ }} 527 ; Switch from register bank 1 to register bank 0 528 079 4a4 bcf rp0___byte,rp0___bit 529 ; Register bank is now 0 530 07a 9f4 call delay 531 ; call delay {{ }} 532 07b 9f4 call delay 533 ; call delay {{ }} 534 07c 9f4 call delay 535 ; 1 cycle for code bank switch : 536 ; Test and jump at end of loop takes 3 cycles : 537 ; 4 + 2 + 1 + 1 + 3 = 11 538 ; nop extra_instructions_per_bit - 11 539 ; Delay 1 cycles 540 07d 000 nop 541 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 542 07e 5a4 bsf rp0___byte,rp0___bit 543 ; Register bank is now 1 544 07f 2f8 decfsz send_byte__count,f 545 080 a73 goto send_byte__240_loop 546 send_byte__240_done: 547 ; `count_down count 8 ...' end 548 ; Send the stop bit : 549 ; 1 cycle extra needed to balance loop : 550 ; nop 1 551 ; Delay 1 cycles 552 081 000 nop 553 ; 1 cycle : 554 ; serial_out := 1 555 082 527 bsf serial_out__byte,serial_out__bit 556 ; 1 cycle for code bank switch : 557 ; call delay {{ }} 558 ; Switch from register bank 1 to register bank 0 559 083 4a4 bcf rp0___byte,rp0___bit 560 ; Register bank is now 0 561 084 9f4 call delay 562 ; call delay {{ }} 563 085 9f4 call delay 564 ; call delay {{ }} 565 086 9f4 call delay 566 ; 1 cycle for code bank switch : 567 ; 2 cycles for call / return : 568 ; 2 cycles for argument 569 ; 1 + 1 + 1 + 2 + 2 = 7 570 ; nop extra_instructions_per_bit - 7 571 ; Delay 5 cycles 572 087 000 nop 573 088 000 nop 574 089 000 nop 575 08a 000 nop 576 08b 000 nop 577 ; procedure send_byte end 578 ; Switch from register bank 0 to register bank 1 579 08c 5a4 bsf rp0___byte,rp0___bit 580 ; Register bank is now 1 581 08d 800 retlw 0 582 ; bank 0 583 ; Default register bank is now 0 584 585 ; procedure set_up start 586 set_up: 587 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 588 ; Procedure must be called with PCLATH set to code bank 0 589 001a set_up__variables__base equ global__variables__bank0+18 590 001a set_up__bytes__base equ set_up__variables__base+0 591 001a set_up__bits__base equ set_up__variables__base+0 592 0001 set_up__total__bytes equ 1 593 ; arguments_none 594 ; This procedure will set the speed of motor to speed . 595 ; Reset failsafe : 596 ; fail_safe_low_counter := 0 597 08e 079 clrf fail_safe_low_counter 598 ; fail_safe_high_counter := fail_safe 599 08f 216 movf fail_safe,w 600 090 038 movwf fail_safe_high_counter 601 ; Mode Dir On Off 602 ; = = = = = = = = = = = = = = = = = = 603 ; 0 0 A 0 604 ; 0 1 B 0 605 ; 1 0 A B 606 ; 1 1 B A 607 ; Motor 0 : 608 ; if { ramp0 = 0 } start 609 091 210 movf ramp0,w 610 ; expression=`{ ramp0 = 0 }' exp_delay=1 true_delay=4 false_delay=7 true_size=4 false_size=7 611 092 743 btfss z___byte,z___bit 612 093 a99 goto label291__0false 613 label291__0true: 614 ; if { ramp0 = 0 } body start 615 ; No ramping : 616 ; actual_speed0 := desired_speed0 617 094 20e movf desired_speed0,w 618 095 028 movwf actual_speed0 619 ; ramp0_delay := 0 620 096 072 clrf ramp0_delay 621 ; ramp0_offset := 0 622 097 074 clrf ramp0_offset 623 ; if { ramp0 = 0 } body end 624 098 aa0 goto label291__0end 625 label291__0false: 626 ; else body start 627 ; Ramping : 628 ; if { desired_speed0 < actual_speed0 } start 629 099 208 movf actual_speed0,w 630 09a 08e subwf desired_speed0,w 631 ; expression=`{ desired_speed0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 632 09b 703 btfss c___byte,c___bit 633 ; if { desired_speed0 < actual_speed0 } body start 634 ; ramp0_offset := 0xff 635 09c cff movlw 255 636 ; 1 instructions found for sharing 637 09d 603 btfsc c___byte,c___bit 638 ; else body start 639 ; ramp0_offset := 1 640 09e c01 movlw 1 641 ; 1 instructions found for sharing 642 ; if exp=` desired_speed0 < actual_speed0 ' single true and false skip delay=6 643 ; Other expression=`{ desired_speed0 < actual_speed0 }' delay=6 644 ; 1 shared instructions follow 645 09f 034 movwf ramp0_offset 646 ; if { desired_speed0 < actual_speed0 } end 647 ; else body end 648 ; if exp=` ramp0 = 0 ' generic 649 label291__0end: 650 ; Other expression=`{ ramp0 = 0 }' delay=-1 651 ; if { ramp0 = 0 } end 652 ; FIXME : do a motor0_off := 0 and delete the appropriate statements below ; 653 ; if { motor0_direction } start 654 ; expression=`{ motor0_direction }' exp_delay=0 true_delay=-2 false_delay=-2 true_size=7 false_size=7 655 0a0 75e btfss motor0_direction__byte,motor0_direction__bit 656 0a1 aaa goto label305__0false 657 label305__0true: 658 ; if { motor0_direction } body start 659 ; Direction = 1 < Backward > : 660 ; if { motor0_mode } start 661 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 662 0a2 61e btfsc motor0_mode__byte,motor0_mode__bit 663 0a3 aa6 goto label307__0true 664 label307__0false: 665 ; else body start 666 ; Mode = 0 < Pulsed > 667 ; motor0_off := 0 668 0a4 06a clrf motor0_off 669 ; else body end 670 0a5 aa8 goto label307__0end 671 label307__0true: 672 ; if { motor0_mode } body start 673 ; Mode = 1 < Continuous > : 674 ; motor0_off := motor0a_mask 675 0a6 c01 movlw 1 676 0a7 02a movwf motor0_off 677 ; if { motor0_mode } body end 678 ; if exp=`motor0_mode' generic 679 label307__0end: 680 ; Other expression=`{ motor0_mode }' delay=-1 681 ; if { motor0_mode } end 682 ; motor0_on := motor0b_mask 683 0a8 c02 movlw 2 684 ; 1 instructions found for sharing 685 0a9 ab1 goto label305__0end 686 label305__0false: 687 ; else body start 688 ; Direction = 0 < Forward > : 689 ; if { motor0_mode } start 690 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 691 0aa 61e btfsc motor0_mode__byte,motor0_mode__bit 692 0ab aae goto label317__0true 693 label317__0false: 694 ; else body start 695 ; Mode = 0 < Pulsed > : 696 ; motor0_off := 0 697 0ac 06a clrf motor0_off 698 ; else body end 699 0ad ab0 goto label317__0end 700 label317__0true: 701 ; if { motor0_mode } body start 702 ; Mode = 1 < Continuous > : 703 ; motor0_off := motor0b_mask 704 0ae c02 movlw 2 705 0af 02a movwf motor0_off 706 ; if { motor0_mode } body end 707 ; if exp=`motor0_mode' generic 708 label317__0end: 709 ; Other expression=`{ motor0_mode }' delay=-1 710 ; if { motor0_mode } end 711 ; motor0_on := motor0a_mask 712 0b0 c01 movlw 1 713 ; 1 instructions found for sharing 714 ; if exp=`motor0_direction' generic 715 label305__0end: 716 ; Other expression=`{ motor0_direction }' delay=-1 717 ; 1 shared instructions follow 718 0b1 02b movwf motor0_on 719 ; if { motor0_direction } end 720 ; Motor1 : 721 ; if { ramp1 = 0 } start 722 0b2 211 movf ramp1,w 723 ; expression=`{ ramp1 = 0 }' exp_delay=1 true_delay=4 false_delay=7 true_size=4 false_size=7 724 0b3 743 btfss z___byte,z___bit 725 0b4 aba goto label328__0false 726 label328__0true: 727 ; if { ramp1 = 0 } body start 728 ; No ramping : 729 ; actual_speed1 := desired_speed1 730 0b5 20f movf desired_speed1,w 731 0b6 029 movwf actual_speed1 732 ; ramp1_delay := 0 733 0b7 073 clrf ramp1_delay 734 ; ramp1_offset := 0 735 0b8 075 clrf ramp1_offset 736 ; if { ramp1 = 0 } body end 737 0b9 ac1 goto label328__0end 738 label328__0false: 739 ; else body start 740 ; Ramping : 741 ; if { desired_speed1 < actual_speed1 } start 742 0ba 209 movf actual_speed1,w 743 0bb 08f subwf desired_speed1,w 744 ; expression=`{ desired_speed1 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 745 0bc 703 btfss c___byte,c___bit 746 ; if { desired_speed1 < actual_speed1 } body start 747 ; ramp1_offset := 0xff 748 0bd cff movlw 255 749 ; 1 instructions found for sharing 750 0be 603 btfsc c___byte,c___bit 751 ; else body start 752 ; ramp1_offset := 1 753 0bf c01 movlw 1 754 ; 1 instructions found for sharing 755 ; if exp=` desired_speed1 < actual_speed1 ' single true and false skip delay=6 756 ; Other expression=`{ desired_speed1 < actual_speed1 }' delay=6 757 ; 1 shared instructions follow 758 0c0 035 movwf ramp1_offset 759 ; if { desired_speed1 < actual_speed1 } end 760 ; else body end 761 ; if exp=` ramp1 = 0 ' generic 762 label328__0end: 763 ; Other expression=`{ ramp1 = 0 }' delay=-1 764 ; if { ramp1 = 0 } end 765 ; FIXME : do a motor1 := 0 here and delete the appropriate statements below : 766 ; if { motor1_direction } start 767 ; expression=`{ motor1_direction }' exp_delay=0 true_delay=-2 false_delay=-2 true_size=7 false_size=7 768 0c1 77e btfss motor1_direction__byte,motor1_direction__bit 769 0c2 acb goto label342__0false 770 label342__0true: 771 ; if { motor1_direction } body start 772 ; Direction = 1 < Backward > : 773 ; if { motor1_mode } start 774 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 775 0c3 63e btfsc motor1_mode__byte,motor1_mode__bit 776 0c4 ac7 goto label344__0true 777 label344__0false: 778 ; else body start 779 ; Mode = 1 < Pulsed > 780 ; motor1_off := 0 781 0c5 06c clrf motor1_off 782 ; else body end 783 0c6 ac9 goto label344__0end 784 label344__0true: 785 ; if { motor1_mode } body start 786 ; Mode = 1 < Continuous > : 787 ; motor1_off := motor1a_mask 788 0c7 c10 movlw 16 789 0c8 02c movwf motor1_off 790 ; if { motor1_mode } body end 791 ; if exp=`motor1_mode' generic 792 label344__0end: 793 ; Other expression=`{ motor1_mode }' delay=-1 794 ; if { motor1_mode } end 795 ; motor1_on := motor1b_mask 796 0c9 c20 movlw 32 797 ; 1 instructions found for sharing 798 0ca ad2 goto label342__0end 799 label342__0false: 800 ; else body start 801 ; Direction = 0 < Forward > : 802 ; if { motor1_mode } start 803 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=2 false_delay=1 true_size=2 false_size=1 804 0cb 63e btfsc motor1_mode__byte,motor1_mode__bit 805 0cc acf goto label354__0true 806 label354__0false: 807 ; else body start 808 ; Mode = 0 < Pulsed > : 809 ; motor1_off := 0 810 0cd 06c clrf motor1_off 811 ; else body end 812 0ce ad1 goto label354__0end 813 label354__0true: 814 ; if { motor1_mode } body start 815 ; Mode = 1 < Continuous > : 816 ; motor1_off := motor1b_mask 817 0cf c20 movlw 32 818 0d0 02c movwf motor1_off 819 ; if { motor1_mode } body end 820 ; if exp=`motor1_mode' generic 821 label354__0end: 822 ; Other expression=`{ motor1_mode }' delay=-1 823 ; if { motor1_mode } end 824 ; motor1_on := motor1a_mask 825 0d1 c10 movlw 16 826 ; 1 instructions found for sharing 827 ; if exp=`motor1_direction' generic 828 label342__0end: 829 ; Other expression=`{ motor1_direction }' delay=-1 830 ; 1 shared instructions follow 831 0d2 02d movwf motor1_on 832 ; if { motor1_direction } end 833 ; procedure set_up end 834 0d3 800 retlw 0 835 ; bank 1 836 ; Default register bank is now 1 837 ; comment {This is kind of ugly . The main routine pretty much fills up all} 838 ; comment {of code bank 1 . We need a little extra space . So we push global} 839 ; comment {variable initialization off to this little chunk of code in code} 840 ; comment {bank 0 . Not pretty .} 841 842 ; procedure reset start 843 reset: 844 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 845 ; Procedure must be called with PCLATH set to code bank 0 846 003a reset__variables__base equ global__variables__bank1+10 847 003a reset__bytes__base equ reset__variables__base+0 848 003a reset__bits__base equ reset__variables__base+0 849 0000 reset__total__bytes equ 0 850 ; arguments_none 851 ; FIXME : By a little careful global rearrangement , it should be possible 852 ; to use a loop to initialize everything . It is quite likely that it is 853 ; OK to just zero out all veriables < except option . > 854 ; Totally blast bank 0 : 855 ; Initialize everything else : 856 ; motor0e := 1 857 0d4 547 bsf motor0e__byte,motor0e__bit 858 ; motor1e := 1 859 0d5 567 bsf motor1e__byte,motor1e__bit 860 ; actual_speed0 := 0 861 0d6 068 clrf actual_speed0 862 ; actual_speed1 := 0 863 0d7 069 clrf actual_speed1 864 ; motor0_off := 0 865 0d8 06a clrf motor0_off 866 ; motor0_on := 0 867 0d9 06b clrf motor0_on 868 ; motor1_off := 0 869 0da 06c clrf motor1_off 870 ; motor1_on := 0 871 0db 06d clrf motor1_on 872 ; desired_speed0 := 0 873 0dc 06e clrf desired_speed0 874 ; desired_speed1 := 0 875 0dd 06f clrf desired_speed1 876 ; ramp0 := 0 877 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 878 0de 4a4 bcf rp0___byte,rp0___bit 879 ; Register bank is now 0 880 0df 070 clrf ramp0 881 ; ramp1 := 0 882 0e0 071 clrf ramp1 883 ; ramp0_delay := 0 884 0e1 072 clrf ramp0_delay 885 ; ramp1_delay := 0 886 0e2 073 clrf ramp1_delay 887 ; ramp0_offset := 0 888 0e3 074 clrf ramp0_offset 889 ; ramp1_offset := 0 890 0e4 075 clrf ramp1_offset 891 ; motor0_direction := 0 892 0e5 45e bcf motor0_direction__byte,motor0_direction__bit 893 ; motor1_direction := 0 894 0e6 47e bcf motor1_direction__byte,motor1_direction__bit 895 ; motor0_mode := 0 896 0e7 41e bcf motor0_mode__byte,motor0_mode__bit 897 ; motor1_mode := 0 898 0e8 43e bcf motor1_mode__byte,motor1_mode__bit 899 ; fail_safe := 0 900 0e9 076 clrf fail_safe 901 ; fail_safe_errors := 0 902 0ea 077 clrf fail_safe_errors 903 ; fail_safe_high_counter := 0 904 0eb 078 clrf fail_safe_high_counter 905 ; fail_safe_low_counter := 0 906 0ec 079 clrf fail_safe_low_counter 907 ; glitch := 0 908 ; Switch from register bank 0 to register bank 1 (which contains glitch) 909 0ed 5a4 bsf rp0___byte,rp0___bit 910 ; Register bank is now 1 911 0ee 070 clrf glitch 912 ; id_index := 0 913 0ef 071 clrf id_index 914 ; Initialize the OPTION register : 915 ; option := option_mask 916 0f0 cc0 movlw 192 917 0f1 032 movwf option 918 ; Now option_mask is in W : 919 ; inline assembly statements begin 920 0f2 002 option 921 ; inline assembly statements end 922 ; procedure reset end 923 0f3 800 retlw 0 924 ; bank 0 925 ; Default register bank is now 0 926 927 ; procedure delay start 928 ; optimize 0 929 delay: 930 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 931 ; Procedure must be called with PCLATH set to code bank 0 932 001b delay__variables__base equ global__variables__bank0+19 933 001b delay__bytes__base equ delay__variables__base+0 934 001e delay__bits__base equ delay__variables__base+3 935 0003 delay__total__bytes equ 3 936 001d delay__504byte2 equ delay__bytes__base+2 937 001d delay__449byte2 equ delay__bytes__base+2 938 001d delay__421byte1 equ delay__bytes__base+2 939 001d delay__482byte2 equ delay__bytes__base+2 940 001d delay__451byte2 equ delay__bytes__base+2 941 001d delay__452byte2 equ delay__bytes__base+2 942 ; arguments_none 943 ; uniform_delay delay_instructions 944 ; Uniform delay remaining = 130 Accumulated Delay = 0 945 ; Uniform delay remaining = 130 Accumulated Delay = 0 946 ; Delay for 1 / 3 of a bit time . 947 ; Uniform delay remaining = 130 Accumulated Delay = 0 948 ; Uniform delay remaining = 130 Accumulated Delay = 0 949 001b delay__motor0 equ delay__bytes__base+0 950 ; Uniform delay remaining = 130 Accumulated Delay = 0 951 001c delay__motor1 equ delay__bytes__base+1 952 ; Uniform delay remaining = 130 Accumulated Delay = 0 953 ; Uniform delay remaining = 130 Accumulated Delay = 0 954 ; Kick the dog : 955 ; Uniform delay remaining = 130 Accumulated Delay = 0 956 ; watch_dog_reset 957 0f4 004 clrwdt 958 ; Uniform delay remaining = 129 Accumulated Delay = 1 959 ; Uniform delay remaining = 129 Accumulated Delay = 1 960 ; This is the first probe of TMR0 : 961 ; Uniform delay remaining = 129 Accumulated Delay = 1 962 ; if { tmr0 < actual_speed0 } start 963 0f5 208 movf actual_speed0,w 964 0f6 081 subwf tmr0,w 965 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 966 0f7 703 btfss c___byte,c___bit 967 ; if { tmr0 < actual_speed0 } body start 968 ; Uniform delay remaining = 129 Accumulated Delay = 0 969 ; motor0 := motor0_on 970 0f8 20b movf motor0_on,w 971 ; 1 instructions found for sharing 972 ; Uniform delay remaining = 127 Accumulated Delay = 2 973 ; if { tmr0 < actual_speed0 } body end 974 0f9 603 btfsc c___byte,c___bit 975 ; else body start 976 ; Uniform delay remaining = 129 Accumulated Delay = 0 977 ; motor0 := motor0_off 978 0fa 20a movf motor0_off,w 979 ; 1 instructions found for sharing 980 ; Uniform delay remaining = 127 Accumulated Delay = 2 981 ; else body end 982 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 983 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 984 ; 1 shared instructions follow 985 0fb 03b movwf delay__motor0 986 ; if { tmr0 < actual_speed0 } end 987 ; Uniform delay remaining = 122 Accumulated Delay = 8 988 ; if { tmr0 < actual_speed1 } start 989 0fc 209 movf actual_speed1,w 990 0fd 081 subwf tmr0,w 991 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 992 0fe 703 btfss c___byte,c___bit 993 ; if { tmr0 < actual_speed1 } body start 994 ; Uniform delay remaining = 122 Accumulated Delay = 0 995 ; motor1 := motor1_on 996 0ff 20d movf motor1_on,w 997 ; 1 instructions found for sharing 998 ; Uniform delay remaining = 120 Accumulated Delay = 2 999 ; if { tmr0 < actual_speed1 } body end 1000 100 603 btfsc c___byte,c___bit 1001 ; else body start 1002 ; Uniform delay remaining = 122 Accumulated Delay = 0 1003 ; motor1 := motor1_off 1004 101 20c movf motor1_off,w 1005 ; 1 instructions found for sharing 1006 ; Uniform delay remaining = 120 Accumulated Delay = 2 1007 ; else body end 1008 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1009 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1010 ; 1 shared instructions follow 1011 102 03c movwf delay__motor1 1012 ; if { tmr0 < actual_speed1 } end 1013 ; Uniform delay remaining = 115 Accumulated Delay = 15 1014 ; portb := motor1 | motor0 1015 103 21c movf delay__motor1,w 1016 104 11b iorwf delay__motor0,w 1017 105 026 movwf portb 1018 ; Uniform delay remaining = 112 Accumulated Delay = 18 1019 ; Uniform delay remaining = 112 Accumulated Delay = 18 1020 ; First check out < fail_safe_counter > : 1021 ; Uniform delay remaining = 112 Accumulated Delay = 18 1022 ; fail_safe_low_counter := fail_safe_low_counter - 1 1023 106 0f9 decf fail_safe_low_counter,f 1024 ; Uniform delay remaining = 111 Accumulated Delay = 19 1025 ; if { z } start 1026 ; expression=`{ z }' exp_delay=0 true_delay=17 false_delay=0 true_size=28 false_size=0 1027 107 643 btfsc z__byte,z__bit 1028 108 b0e goto label449__0true 1029 label449__0false: 1030 ; Delay 16 cycles 1031 109 c05 movlw 5 1032 10a 03d movwf delay__449byte2 1033 delay__449delay1: 1034 10b 2fd decfsz delay__449byte2,f 1035 10c b0b goto delay__449delay1 1036 10d b2a goto label449__0end 1037 label449__0true: 1038 ; if { z } body start 1039 ; Uniform delay remaining = 111 Accumulated Delay = 0 1040 ; fail_safe_high_counter := fail_safe_high_counter - 1 1041 10e 0f8 decf fail_safe_high_counter,f 1042 ; Uniform delay remaining = 110 Accumulated Delay = 1 1043 ; if { z } start 1044 ; expression=`{ z }' exp_delay=0 true_delay=13 false_delay=0 true_size=18 false_size=0 1045 10f 643 btfsc z__byte,z__bit 1046 110 b18 goto label451__0true 1047 label451__0false: 1048 ; Delay 12 cycles 1049 111 c03 movlw 3 1050 112 03d movwf delay__451byte2 1051 delay__451delay1: 1052 113 2fd decfsz delay__451byte2,f 1053 114 b13 goto delay__451delay1 1054 115 000 nop 1055 116 000 nop 1056 117 b2a goto label451__0end 1057 label451__0true: 1058 ; if { z } body start 1059 ; Uniform delay remaining = 110 Accumulated Delay = 0 1060 ; if { fail_safe != 0 } start 1061 118 216 movf fail_safe,w 1062 ; expression=`{ fail_safe != 0 }' exp_delay=1 true_delay=9 false_delay=0 true_size=9 false_size=0 1063 119 743 btfss z___byte,z___bit 1064 11a b21 goto label452__0true 1065 label452__0false: 1066 ; Delay 8 cycles 1067 11b c02 movlw 2 1068 11c 03d movwf delay__452byte2 1069 delay__452delay1: 1070 11d 2fd decfsz delay__452byte2,f 1071 11e b1d goto delay__452delay1 1072 11f 000 nop 1073 120 b2a goto label452__0end 1074 label452__0true: 1075 ; if { fail_safe != 0 } body start 1076 ; Uniform delay remaining = 110 Accumulated Delay = 0 1077 ; Turn the motors off : 1078 ; Uniform delay remaining = 110 Accumulated Delay = 0 1079 ; motor0_on := 0 1080 121 06b clrf motor0_on 1081 ; Uniform delay remaining = 109 Accumulated Delay = 1 1082 ; motor0_off := 0 1083 122 06a clrf motor0_off 1084 ; Uniform delay remaining = 108 Accumulated Delay = 2 1085 ; motor1_on := 0 1086 123 06d clrf motor1_on 1087 ; Uniform delay remaining = 107 Accumulated Delay = 3 1088 ; motor1_off := 0 1089 124 06c clrf motor1_off 1090 ; Uniform delay remaining = 106 Accumulated Delay = 4 1091 ; desired_speed0 := 0 1092 125 06e clrf desired_speed0 1093 ; Uniform delay remaining = 105 Accumulated Delay = 5 1094 ; desired_speed1 := 0 1095 126 06f clrf desired_speed1 1096 ; Uniform delay remaining = 104 Accumulated Delay = 6 1097 ; actual_speed0 := 0 1098 127 068 clrf actual_speed0 1099 ; Uniform delay remaining = 103 Accumulated Delay = 7 1100 ; actual_speed0 := 0 1101 128 068 clrf actual_speed0 1102 ; Uniform delay remaining = 102 Accumulated Delay = 8 1103 ; fail_safe_errors := fail_safe_errors + 1 1104 129 2b7 incf fail_safe_errors,f 1105 ; Uniform delay remaining = 101 Accumulated Delay = 9 1106 ; Uniform delay remaining = 101 Accumulated Delay = 9 1107 ; if { fail_safe != 0 } body end 1108 ; if exp=` fail_safe != 0 ' total delay=13 1109 ; if exp=` fail_safe != 0 ' generic 1110 label452__0end: 1111 ; Other expression=`{ fail_safe != 0 }' delay=13 1112 ; if { fail_safe != 0 } end 1113 ; Uniform delay remaining = 97 Accumulated Delay = 13 1114 ; Uniform delay remaining = 97 Accumulated Delay = 13 1115 ; if { z } body end 1116 ; if exp=`z' total delay=16 1117 ; if exp=`z' generic 1118 label451__0end: 1119 ; Other expression=`{ z }' delay=16 1120 ; if { z } end 1121 ; Uniform delay remaining = 94 Accumulated Delay = 17 1122 ; Uniform delay remaining = 94 Accumulated Delay = 17 1123 ; if { z } body end 1124 ; if exp=`z' total delay=20 1125 ; if exp=`z' generic 1126 label449__0end: 1127 ; Other expression=`{ z }' delay=20 1128 ; if { z } end 1129 ; Uniform delay remaining = 91 Accumulated Delay = 39 1130 ; Uniform delay remaining = 91 Accumulated Delay = 39 1131 ; This is the second probe of TMR0 : 1132 ; Uniform delay remaining = 91 Accumulated Delay = 39 1133 ; if { tmr0 < actual_speed0 } start 1134 12a 208 movf actual_speed0,w 1135 12b 081 subwf tmr0,w 1136 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1137 12c 703 btfss c___byte,c___bit 1138 ; if { tmr0 < actual_speed0 } body start 1139 ; Uniform delay remaining = 91 Accumulated Delay = 0 1140 ; motor0 := motor0_on 1141 12d 20b movf motor0_on,w 1142 ; 1 instructions found for sharing 1143 ; Uniform delay remaining = 89 Accumulated Delay = 2 1144 ; if { tmr0 < actual_speed0 } body end 1145 12e 603 btfsc c___byte,c___bit 1146 ; else body start 1147 ; Uniform delay remaining = 91 Accumulated Delay = 0 1148 ; motor0 := motor0_off 1149 12f 20a movf motor0_off,w 1150 ; 1 instructions found for sharing 1151 ; Uniform delay remaining = 89 Accumulated Delay = 2 1152 ; else body end 1153 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1154 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1155 ; 1 shared instructions follow 1156 130 03b movwf delay__motor0 1157 ; if { tmr0 < actual_speed0 } end 1158 ; Uniform delay remaining = 84 Accumulated Delay = 46 1159 ; if { tmr0 < actual_speed1 } start 1160 131 209 movf actual_speed1,w 1161 132 081 subwf tmr0,w 1162 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1163 133 703 btfss c___byte,c___bit 1164 ; if { tmr0 < actual_speed1 } body start 1165 ; Uniform delay remaining = 84 Accumulated Delay = 0 1166 ; motor1 := motor1_on 1167 134 20d movf motor1_on,w 1168 ; 1 instructions found for sharing 1169 ; Uniform delay remaining = 82 Accumulated Delay = 2 1170 ; if { tmr0 < actual_speed1 } body end 1171 135 603 btfsc c___byte,c___bit 1172 ; else body start 1173 ; Uniform delay remaining = 84 Accumulated Delay = 0 1174 ; motor1 := motor1_off 1175 136 20c movf motor1_off,w 1176 ; 1 instructions found for sharing 1177 ; Uniform delay remaining = 82 Accumulated Delay = 2 1178 ; else body end 1179 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1180 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1181 ; 1 shared instructions follow 1182 137 03c movwf delay__motor1 1183 ; if { tmr0 < actual_speed1 } end 1184 ; Uniform delay remaining = 77 Accumulated Delay = 53 1185 ; portb := motor1 | motor0 1186 138 21c movf delay__motor1,w 1187 139 11b iorwf delay__motor0,w 1188 13a 026 movwf portb 1189 ; Uniform delay remaining = 74 Accumulated Delay = 56 1190 ; Uniform delay remaining = 74 Accumulated Delay = 56 1191 ; Do < ramp0 > management : 1192 ; Uniform delay remaining = 74 Accumulated Delay = 56 1193 ; ramp0_delay := ramp0_delay - 1 1194 13b 0f2 decf ramp0_delay,f 1195 ; Uniform delay remaining = 73 Accumulated Delay = 57 1196 ; if { z } start 1197 ; expression=`{ z }' exp_delay=0 true_delay=9 false_delay=0 true_size=10 false_size=0 1198 13c 643 btfsc z__byte,z__bit 1199 13d b44 goto label482__0true 1200 label482__0false: 1201 ; Delay 8 cycles 1202 13e c02 movlw 2 1203 13f 03d movwf delay__482byte2 1204 delay__482delay1: 1205 140 2fd decfsz delay__482byte2,f 1206 141 b40 goto delay__482delay1 1207 142 000 nop 1208 143 b4e goto label482__0end 1209 label482__0true: 1210 ; if { z } body start 1211 ; Uniform delay remaining = 73 Accumulated Delay = 0 1212 ; ramp0_delay := ramp0 1213 144 210 movf ramp0,w 1214 145 032 movwf ramp0_delay 1215 ; Uniform delay remaining = 71 Accumulated Delay = 2 1216 ; if { actual_speed0 != desired_speed0 } start 1217 146 208 movf actual_speed0,w 1218 147 08e subwf desired_speed0,w 1219 ; expression=`{ actual_speed0 != desired_speed0 }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1220 148 743 btfss z___byte,z___bit 1221 149 b4c goto label484__0true 1222 label484__0false: 1223 ; Delay 1 cycles 1224 14a 000 nop 1225 14b b4e goto label484__0end 1226 label484__0true: 1227 ; if { actual_speed0 != desired_speed0 } body start 1228 ; Uniform delay remaining = 71 Accumulated Delay = 0 1229 ; actual_speed0 := actual_speed0 + ramp0_offset 1230 14c 214 movf ramp0_offset,w 1231 14d 1e8 addwf actual_speed0,f 1232 ; Uniform delay remaining = 69 Accumulated Delay = 2 1233 ; Uniform delay remaining = 69 Accumulated Delay = 2 1234 ; if { actual_speed0 != desired_speed0 } body end 1235 ; if exp=` actual_speed0 != desired_speed0 ' total delay=7 1236 ; if exp=` actual_speed0 != desired_speed0 ' generic 1237 label484__0end: 1238 ; Other expression=`{ actual_speed0 != desired_speed0 }' delay=7 1239 ; if { actual_speed0 != desired_speed0 } end 1240 ; Uniform delay remaining = 64 Accumulated Delay = 9 1241 ; Uniform delay remaining = 64 Accumulated Delay = 9 1242 ; if { z } body end 1243 ; if exp=`z' total delay=12 1244 ; if exp=`z' generic 1245 label482__0end: 1246 ; Other expression=`{ z }' delay=12 1247 ; if { z } end 1248 ; Uniform delay remaining = 61 Accumulated Delay = 69 1249 ; Uniform delay remaining = 61 Accumulated Delay = 69 1250 ; This is the third probe of TMR0 : 1251 ; Uniform delay remaining = 61 Accumulated Delay = 69 1252 ; if { tmr0 < actual_speed0 } start 1253 14e 208 movf actual_speed0,w 1254 14f 081 subwf tmr0,w 1255 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1256 150 703 btfss c___byte,c___bit 1257 ; if { tmr0 < actual_speed0 } body start 1258 ; Uniform delay remaining = 61 Accumulated Delay = 0 1259 ; motor0 := motor0_on 1260 151 20b movf motor0_on,w 1261 ; 1 instructions found for sharing 1262 ; Uniform delay remaining = 59 Accumulated Delay = 2 1263 ; if { tmr0 < actual_speed0 } body end 1264 152 603 btfsc c___byte,c___bit 1265 ; else body start 1266 ; Uniform delay remaining = 61 Accumulated Delay = 0 1267 ; motor0 := motor0_off 1268 153 20a movf motor0_off,w 1269 ; 1 instructions found for sharing 1270 ; Uniform delay remaining = 59 Accumulated Delay = 2 1271 ; else body end 1272 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1273 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1274 ; 1 shared instructions follow 1275 154 03b movwf delay__motor0 1276 ; if { tmr0 < actual_speed0 } end 1277 ; Uniform delay remaining = 54 Accumulated Delay = 76 1278 ; if { tmr0 < actual_speed1 } start 1279 155 209 movf actual_speed1,w 1280 156 081 subwf tmr0,w 1281 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1282 157 703 btfss c___byte,c___bit 1283 ; if { tmr0 < actual_speed1 } body start 1284 ; Uniform delay remaining = 54 Accumulated Delay = 0 1285 ; motor1 := motor1_on 1286 158 20d movf motor1_on,w 1287 ; 1 instructions found for sharing 1288 ; Uniform delay remaining = 52 Accumulated Delay = 2 1289 ; if { tmr0 < actual_speed1 } body end 1290 159 603 btfsc c___byte,c___bit 1291 ; else body start 1292 ; Uniform delay remaining = 54 Accumulated Delay = 0 1293 ; motor1 := motor1_off 1294 15a 20c movf motor1_off,w 1295 ; 1 instructions found for sharing 1296 ; Uniform delay remaining = 52 Accumulated Delay = 2 1297 ; else body end 1298 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1299 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1300 ; 1 shared instructions follow 1301 15b 03c movwf delay__motor1 1302 ; if { tmr0 < actual_speed1 } end 1303 ; Uniform delay remaining = 47 Accumulated Delay = 83 1304 ; portb := motor1 | motor0 1305 15c 21c movf delay__motor1,w 1306 15d 11b iorwf delay__motor0,w 1307 15e 026 movwf portb 1308 ; Uniform delay remaining = 44 Accumulated Delay = 86 1309 ; Uniform delay remaining = 44 Accumulated Delay = 86 1310 ; Do < ramp1 > management : 1311 ; Uniform delay remaining = 44 Accumulated Delay = 86 1312 ; ramp1_delay := ramp1_delay - 1 1313 15f 0f3 decf ramp1_delay,f 1314 ; Uniform delay remaining = 43 Accumulated Delay = 87 1315 ; if { z } start 1316 ; expression=`{ z }' exp_delay=0 true_delay=9 false_delay=0 true_size=10 false_size=0 1317 160 643 btfsc z__byte,z__bit 1318 161 b68 goto label504__0true 1319 label504__0false: 1320 ; Delay 8 cycles 1321 162 c02 movlw 2 1322 163 03d movwf delay__504byte2 1323 delay__504delay1: 1324 164 2fd decfsz delay__504byte2,f 1325 165 b64 goto delay__504delay1 1326 166 000 nop 1327 167 b72 goto label504__0end 1328 label504__0true: 1329 ; if { z } body start 1330 ; Uniform delay remaining = 43 Accumulated Delay = 0 1331 ; ramp1_delay := ramp1 1332 168 211 movf ramp1,w 1333 169 033 movwf ramp1_delay 1334 ; Uniform delay remaining = 41 Accumulated Delay = 2 1335 ; if { actual_speed1 != desired_speed1 } start 1336 16a 209 movf actual_speed1,w 1337 16b 08f subwf desired_speed1,w 1338 ; expression=`{ actual_speed1 != desired_speed1 }' exp_delay=2 true_delay=2 false_delay=0 true_size=2 false_size=0 1339 16c 743 btfss z___byte,z___bit 1340 16d b70 goto label506__0true 1341 label506__0false: 1342 ; Delay 1 cycles 1343 16e 000 nop 1344 16f b72 goto label506__0end 1345 label506__0true: 1346 ; if { actual_speed1 != desired_speed1 } body start 1347 ; Uniform delay remaining = 41 Accumulated Delay = 0 1348 ; actual_speed1 := actual_speed1 + ramp1_offset 1349 170 215 movf ramp1_offset,w 1350 171 1e9 addwf actual_speed1,f 1351 ; Uniform delay remaining = 39 Accumulated Delay = 2 1352 ; Uniform delay remaining = 39 Accumulated Delay = 2 1353 ; if { actual_speed1 != desired_speed1 } body end 1354 ; if exp=` actual_speed1 != desired_speed1 ' total delay=7 1355 ; if exp=` actual_speed1 != desired_speed1 ' generic 1356 label506__0end: 1357 ; Other expression=`{ actual_speed1 != desired_speed1 }' delay=7 1358 ; if { actual_speed1 != desired_speed1 } end 1359 ; Uniform delay remaining = 34 Accumulated Delay = 9 1360 ; Uniform delay remaining = 34 Accumulated Delay = 9 1361 ; if { z } body end 1362 ; if exp=`z' total delay=12 1363 ; if exp=`z' generic 1364 label504__0end: 1365 ; Other expression=`{ z }' delay=12 1366 ; if { z } end 1367 ; Uniform delay remaining = 31 Accumulated Delay = 99 1368 ; Uniform delay remaining = 31 Accumulated Delay = 99 1369 ; This is the forth probe of TMR0 : 1370 ; Uniform delay remaining = 31 Accumulated Delay = 99 1371 ; if { tmr0 < actual_speed0 } start 1372 172 208 movf actual_speed0,w 1373 173 081 subwf tmr0,w 1374 ; expression=`{ tmr0 < actual_speed0 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1375 174 703 btfss c___byte,c___bit 1376 ; if { tmr0 < actual_speed0 } body start 1377 ; Uniform delay remaining = 31 Accumulated Delay = 0 1378 ; motor0 := motor0_on 1379 175 20b movf motor0_on,w 1380 ; 1 instructions found for sharing 1381 ; Uniform delay remaining = 29 Accumulated Delay = 2 1382 ; if { tmr0 < actual_speed0 } body end 1383 176 603 btfsc c___byte,c___bit 1384 ; else body start 1385 ; Uniform delay remaining = 31 Accumulated Delay = 0 1386 ; motor0 := motor0_off 1387 177 20a movf motor0_off,w 1388 ; 1 instructions found for sharing 1389 ; Uniform delay remaining = 29 Accumulated Delay = 2 1390 ; else body end 1391 ; if exp=` tmr0 < actual_speed0 ' single true and false skip delay=6 1392 ; Other expression=`{ tmr0 < actual_speed0 }' delay=6 1393 ; 1 shared instructions follow 1394 178 03b movwf delay__motor0 1395 ; if { tmr0 < actual_speed0 } end 1396 ; Uniform delay remaining = 24 Accumulated Delay = 106 1397 ; if { tmr0 < actual_speed1 } start 1398 179 209 movf actual_speed1,w 1399 17a 081 subwf tmr0,w 1400 ; expression=`{ tmr0 < actual_speed1 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 1401 17b 703 btfss c___byte,c___bit 1402 ; if { tmr0 < actual_speed1 } body start 1403 ; Uniform delay remaining = 24 Accumulated Delay = 0 1404 ; motor1 := motor1_on 1405 17c 20d movf motor1_on,w 1406 ; 1 instructions found for sharing 1407 ; Uniform delay remaining = 22 Accumulated Delay = 2 1408 ; if { tmr0 < actual_speed1 } body end 1409 17d 603 btfsc c___byte,c___bit 1410 ; else body start 1411 ; Uniform delay remaining = 24 Accumulated Delay = 0 1412 ; motor1 := motor1_off 1413 17e 20c movf motor1_off,w 1414 ; 1 instructions found for sharing 1415 ; Uniform delay remaining = 22 Accumulated Delay = 2 1416 ; else body end 1417 ; if exp=` tmr0 < actual_speed1 ' single true and false skip delay=6 1418 ; Other expression=`{ tmr0 < actual_speed1 }' delay=6 1419 ; 1 shared instructions follow 1420 17f 03c movwf delay__motor1 1421 ; if { tmr0 < actual_speed1 } end 1422 ; Uniform delay remaining = 17 Accumulated Delay = 113 1423 ; portb := motor1 | motor0 1424 180 21c movf delay__motor1,w 1425 181 11b iorwf delay__motor0,w 1426 182 026 movwf portb 1427 ; Uniform delay remaining = 14 Accumulated Delay = 116 1428 ; Uniform delay remaining = 14 Accumulated Delay = 116 1429 ; Soak up remaining 14 cycles 1430 ; Delay 14 cycles 1431 183 c04 movlw 4 1432 184 03d movwf delay__421byte1 1433 delay__421delay0: 1434 185 2fd decfsz delay__421byte1,f 1435 186 b85 goto delay__421delay0 1436 187 000 nop 1437 ; procedure delay end 1438 188 800 retlw 0 1439 ; optimize 1 1440 ; origin 0x200 1441 org 512 1442 ; bank 1 1443 ; Default register bank is now 1 1444 1445 ; procedure main start 1446 switch__576block_start: 1447 200 1e2 addwf pcl___register,f 1448 201 aab goto switch__576block577 1449 202 aab goto switch__576block577 1450 203 ac1 goto switch__576block587 1451 204 acb goto switch__576block593 1452 205 ad1 goto switch__576block598 1453 206 ad1 goto switch__576block598 1454 207 ad1 goto switch__576block598 1455 208 ad1 goto switch__576block598 1456 switch__576block_end: 1457 ; switch_check 576 switch__576block_start switch__576block_end 1458 switch__647block_start: 1459 209 1e2 addwf pcl___register,f 1460 20a b37 goto switch__647block648 1461 20b b3f goto switch__647block652 1462 20c b46 goto switch__647block656 1463 20d b46 goto switch__647block656 1464 20e b4f goto switch__647block664 1465 20f b4f goto switch__647block664 1466 210 b69 goto switch__647block686 1467 211 b69 goto switch__647block686 1468 switch__647block_end: 1469 ; switch_check 647 switch__647block_start switch__647block_end 1470 switch__699block_start: 1471 212 1e2 addwf pcl___register,f 1472 213 b80 goto switch__699block700 1473 214 b8b goto switch__699block705 1474 215 b93 goto switch__699block709 1475 216 b99 goto switch__699block713 1476 217 b9f goto switch__699block717 1477 218 b9f goto switch__699block717 1478 219 b9f goto switch__699block717 1479 21a b9f goto switch__699block717 1480 switch__699block_end: 1481 ; switch_check 699 switch__699block_start switch__699block_end 1482 switch__731block_start: 1483 21b 1e2 addwf pcl___register,f 1484 21c bae goto switch__731block732 1485 21d bb2 goto switch__731block736 1486 21e bbd goto switch__731default747 1487 21f bbd goto switch__731default747 1488 220 bbd goto switch__731default747 1489 221 bbd goto switch__731default747 1490 222 bbd goto switch__731default747 1491 223 bbd goto switch__731default747 1492 switch__731block_end: 1493 ; switch_check 731 switch__731block_start switch__731block_end 1494 switch__573block_start: 1495 224 1e2 addwf pcl___register,f 1496 225 aa8 goto switch__573block574 1497 226 af7 goto switch__573block614 1498 227 b2e goto switch__573block637 1499 228 b34 goto switch__573block645 1500 229 b7d goto switch__573block697 1501 22a bab goto switch__573block729 1502 22b bbe goto switch__573default752 1503 22c bbe goto switch__573default752 1504 switch__573block_end: 1505 ; switch_check 573 switch__573block_start switch__573block_end 1506 switch__762block_start: 1507 22d 1e2 addwf pcl___register,f 1508 22e bc8 goto switch__762block763 1509 22f bcb goto switch__762block767 1510 230 bce goto switch__762block771 1511 231 bd4 goto switch__762block775 1512 232 bd9 goto switch__762block779 1513 233 be9 goto switch__762block790 1514 234 beb goto switch__762block794 1515 235 bf2 goto switch__762block799 1516 switch__762block_end: 1517 ; switch_check 762 switch__762block_start switch__762block_end 1518 switch__759block_start: 1519 236 1e2 addwf pcl___register,f 1520 237 bf5 goto switch__759end 1521 238 bf5 goto switch__759end 1522 239 bf5 goto switch__759end 1523 23a bf5 goto switch__759end 1524 23b bf5 goto switch__759end 1525 23c bf5 goto switch__759end 1526 23d bf5 goto switch__759end 1527 23e bc5 goto switch__759block760 1528 switch__759block_end: 1529 ; switch_check 759 switch__759block_start switch__759block_end 1530 switch__543block_start: 1531 23f 1e2 addwf pcl___register,f 1532 240 a52 goto switch__543block544 1533 241 a78 goto switch__543block557 1534 242 aa2 goto switch__543block571 1535 243 bbf goto switch__543block757 1536 switch__543block_end: 1537 ; switch_check 543 switch__543block_start switch__543block_end 1538 main: 1539 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1540 ; Procedure must be called with PCLATH set to code bank 0 1541 003a main__variables__base equ global__variables__bank1+10 1542 003a main__bytes__base equ main__variables__base+0 1543 003d main__bits__base equ main__variables__base+3 1544 0003 main__total__bytes equ 3 1545 003c main__759byte0 equ main__bytes__base+2 1546 003c main__573byte0 equ main__bytes__base+2 1547 003c main__559byte0 equ main__bytes__base+2 1548 003c main__546byte0 equ main__bytes__base+2 1549 003c main__543byte0 equ main__bytes__base+2 1550 ; arguments_none 1551 003a main__command equ main__bytes__base+0 1552 003b main__temp equ main__bytes__base+1 1553 ; call reset {{ }} 1554 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1555 244 4a3 bcf pa0___byte,pa0___bit 1556 245 9d4 call reset 1557 ; Loop waiting for commands : 1558 ; loop_forever ... start 1559 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1560 246 5a3 bsf pa0___byte,pa0___bit 1561 main__538loop__forever: 1562 ; Get a command byte : 1563 ; command := get_byte {{ }} 1564 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1565 247 4a3 bcf pa0___byte,pa0___bit 1566 248 93c call get_byte 1567 249 213 movf get_byte__0return__byte,w 1568 24a 03a movwf main__command 1569 ; Dispatch on command : 1570 ; switch { command >> 6 } 1571 24b 39a swapf main__command,w 1572 24c 03c movwf main__543byte0 1573 24d 33c rrf main__543byte0,f 1574 24e 31c rrf main__543byte0,w 1575 24f e03 andlw 3 1576 ; case 0 1577 ; case 1 1578 ; case 2 1579 ; case 3 1580 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1581 250 5a3 bsf pa0___byte,pa0___bit 1582 251 a3f goto switch__543block_start 1583 switch__543block544: 1584 ; Set Quick < Command = 00 hh hhdm > : 1585 ; temp := {{ command << 2 }} & 0xf0 1586 252 35a rlf main__command,w 1587 253 03c movwf main__546byte0 1588 254 35c rlf main__546byte0,w 1589 255 ef0 andlw 240 1590 256 03b movwf main__temp 1591 ; if { command @ 0 } start 1592 ; Alias variable for select command @ 0 1593 003a main__command__547select0 equ main__command+0 1594 003a main__command__547select0__byte equ main__command+0 1595 0000 main__command__547select0__bit equ 0 1596 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=5 false_delay=5 true_size=5 false_size=5 1597 257 71a btfss main__command__547select0__byte,main__command__547select0__bit 1598 258 a66 goto label547__1false 1599 label547__1true: 1600 ; if { command @ 0 } body start 1601 ; Motor : 1602 ; desired_speed1 := temp 1603 259 21b movf main__temp,w 1604 25a 02f movwf desired_speed1 1605 ; motor1_direction := command @ 1 1606 ; Alias variable for select command @ 1 1607 003a main__command__550select0 equ main__command+0 1608 003a main__command__550select0__byte equ main__command+0 1609 0001 main__command__550select0__bit equ 1 1610 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1611 25b 4a4 bcf rp0___byte,rp0___bit 1612 ; Register bank is now 0 1613 25c 47e bcf motor1_direction__byte,motor1_direction__bit 1614 ; Switch from register bank 0 to register bank 1 (which contains main__command__550select0__byte) 1615 25d 5a4 bsf rp0___byte,rp0___bit 1616 ; Register bank is now 1 1617 25e 443 bcf z___byte,z___bit 1618 25f 63a btfsc main__command__550select0__byte,main__command__550select0__bit 1619 260 543 bsf z___byte,z___bit 1620 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1621 261 4a4 bcf rp0___byte,rp0___bit 1622 ; Register bank is now 0 1623 262 643 btfsc z___byte,z___bit 1624 263 57e bsf motor1_direction__byte,motor1_direction__bit 1625 ; if { command @ 0 } body end 1626 ; Switch from register bank 0 to register bank 1 1627 264 5a4 bsf rp0___byte,rp0___bit 1628 ; Register bank is now 1 1629 265 a72 goto label547__1end 1630 label547__1false: 1631 ; else body start 1632 ; desired_speed0 := temp 1633 266 21b movf main__temp,w 1634 267 02e movwf desired_speed0 1635 ; motor0_direction := command @ 1 1636 ; Alias variable for select command @ 1 1637 003a main__command__553select0 equ main__command+0 1638 003a main__command__553select0__byte equ main__command+0 1639 0001 main__command__553select0__bit equ 1 1640 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1641 268 4a4 bcf rp0___byte,rp0___bit 1642 ; Register bank is now 0 1643 269 45e bcf motor0_direction__byte,motor0_direction__bit 1644 ; Switch from register bank 0 to register bank 1 (which contains main__command__553select0__byte) 1645 26a 5a4 bsf rp0___byte,rp0___bit 1646 ; Register bank is now 1 1647 26b 443 bcf z___byte,z___bit 1648 26c 63a btfsc main__command__553select0__byte,main__command__553select0__bit 1649 26d 543 bsf z___byte,z___bit 1650 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1651 26e 4a4 bcf rp0___byte,rp0___bit 1652 ; Register bank is now 0 1653 26f 643 btfsc z___byte,z___bit 1654 270 55e bsf motor0_direction__byte,motor0_direction__bit 1655 ; else body end 1656 ; if exp=` command @ 0 ' generic 1657 ; Switch from register bank 0 to register bank 1 1658 271 5a4 bsf rp0___byte,rp0___bit 1659 ; Register bank is now 1 1660 label547__1end: 1661 ; Other expression=`{ command @ 0 }' delay=-1 1662 ; if { command @ 0 } end 1663 ; call set_up {{ }} 1664 ; Switch from register bank 1 to register bank 0 1665 272 4a4 bcf rp0___byte,rp0___bit 1666 ; Register bank is now 0 1667 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1668 273 4a3 bcf pa0___byte,pa0___bit 1669 274 98e call set_up 1670 ; Switch from register bank 0 to register bank 1 1671 275 5a4 bsf rp0___byte,rp0___bit 1672 ; Register bank is now 1 1673 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1674 276 5a3 bsf pa0___byte,pa0___bit 1675 277 bf5 goto switch__543end 1676 switch__543block557: 1677 ; Set Low < Command = 01 ll lldm > : 1678 ; temp := {{ command >> 2 }} & 0xf 1679 278 31a rrf main__command,w 1680 279 03c movwf main__559byte0 1681 27a 31c rrf main__559byte0,w 1682 27b e0f andlw 15 1683 27c 03b movwf main__temp 1684 ; if { command @ 0 } start 1685 ; Alias variable for select command @ 0 1686 003a main__command__560select0 equ main__command+0 1687 003a main__command__560select0__byte equ main__command+0 1688 0000 main__command__560select0__bit equ 0 1689 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=7 false_delay=7 true_size=7 false_size=7 1690 27d 71a btfss main__command__560select0__byte,main__command__560select0__bit 1691 27e a8e goto label560__1false 1692 label560__1true: 1693 ; if { command @ 0 } body start 1694 ; Motor 1 : 1695 ; desired_speed1 := desired_speed1 & 0xf0 | temp 1696 27f cf0 movlw 240 1697 280 14f andwf desired_speed1,w 1698 281 11b iorwf main__temp,w 1699 282 02f movwf desired_speed1 1700 ; motor1_direction := command @ 1 1701 ; Alias variable for select command @ 1 1702 003a main__command__563select0 equ main__command+0 1703 003a main__command__563select0__byte equ main__command+0 1704 0001 main__command__563select0__bit equ 1 1705 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1706 283 4a4 bcf rp0___byte,rp0___bit 1707 ; Register bank is now 0 1708 284 47e bcf motor1_direction__byte,motor1_direction__bit 1709 ; Switch from register bank 0 to register bank 1 (which contains main__command__563select0__byte) 1710 285 5a4 bsf rp0___byte,rp0___bit 1711 ; Register bank is now 1 1712 286 443 bcf z___byte,z___bit 1713 287 63a btfsc main__command__563select0__byte,main__command__563select0__bit 1714 288 543 bsf z___byte,z___bit 1715 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1716 289 4a4 bcf rp0___byte,rp0___bit 1717 ; Register bank is now 0 1718 28a 643 btfsc z___byte,z___bit 1719 28b 57e bsf motor1_direction__byte,motor1_direction__bit 1720 ; if { command @ 0 } body end 1721 ; Switch from register bank 0 to register bank 1 1722 28c 5a4 bsf rp0___byte,rp0___bit 1723 ; Register bank is now 1 1724 28d a9c goto label560__1end 1725 label560__1false: 1726 ; else body start 1727 ; Motor 0 : 1728 ; desired_speed0 := desired_speed0 & 0xf0 | temp 1729 28e cf0 movlw 240 1730 28f 14e andwf desired_speed0,w 1731 290 11b iorwf main__temp,w 1732 291 02e movwf desired_speed0 1733 ; motor0_direction := command @ 1 1734 ; Alias variable for select command @ 1 1735 003a main__command__567select0 equ main__command+0 1736 003a main__command__567select0__byte equ main__command+0 1737 0001 main__command__567select0__bit equ 1 1738 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1739 292 4a4 bcf rp0___byte,rp0___bit 1740 ; Register bank is now 0 1741 293 45e bcf motor0_direction__byte,motor0_direction__bit 1742 ; Switch from register bank 0 to register bank 1 (which contains main__command__567select0__byte) 1743 294 5a4 bsf rp0___byte,rp0___bit 1744 ; Register bank is now 1 1745 295 443 bcf z___byte,z___bit 1746 296 63a btfsc main__command__567select0__byte,main__command__567select0__bit 1747 297 543 bsf z___byte,z___bit 1748 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1749 298 4a4 bcf rp0___byte,rp0___bit 1750 ; Register bank is now 0 1751 299 643 btfsc z___byte,z___bit 1752 29a 55e bsf motor0_direction__byte,motor0_direction__bit 1753 ; else body end 1754 ; if exp=` command @ 0 ' generic 1755 ; Switch from register bank 0 to register bank 1 1756 29b 5a4 bsf rp0___byte,rp0___bit 1757 ; Register bank is now 1 1758 label560__1end: 1759 ; Other expression=`{ command @ 0 }' delay=-1 1760 ; if { command @ 0 } end 1761 ; call set_up {{ }} 1762 ; Switch from register bank 1 to register bank 0 1763 29c 4a4 bcf rp0___byte,rp0___bit 1764 ; Register bank is now 0 1765 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1766 29d 4a3 bcf pa0___byte,pa0___bit 1767 29e 98e call set_up 1768 ; Switch from register bank 0 to register bank 1 1769 29f 5a4 bsf rp0___byte,rp0___bit 1770 ; Register bank is now 1 1771 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1772 2a0 5a3 bsf pa0___byte,pa0___bit 1773 2a1 bf5 goto switch__543end 1774 switch__543block571: 1775 ; Command = 10 xx xxxx : 1776 ; switch { {{ command >> 3 }} & 7 } 1777 2a2 31a rrf main__command,w 1778 2a3 03c movwf main__573byte0 1779 2a4 33c rrf main__573byte0,f 1780 2a5 31c rrf main__573byte0,w 1781 2a6 e07 andlw 7 1782 ; case 0 1783 ; case 1 1784 ; case 2 1785 ; case 3 1786 ; case 4 1787 ; case 5 1788 2a7 a24 goto switch__573block_start 1789 switch__573block574: 1790 ; Command = 1000 0 xxx : 1791 ; switch { command & 7 } 1792 2a8 c07 movlw 7 1793 2a9 15a andwf main__command,w 1794 ; case 0 1 1795 ; case 2 1796 ; case 3 1797 ; case 4 5 6 7 1798 2aa a00 goto switch__576block_start 1799 switch__576block577: 1800 ; Set Ramp < Command = 1000 000 m > : 1801 ; temp := get_byte {{ }} 1802 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1803 2ab 4a3 bcf pa0___byte,pa0___bit 1804 2ac 93c call get_byte 1805 2ad 213 movf get_byte__0return__byte,w 1806 2ae 03b movwf main__temp 1807 ; if { command @ 0 } start 1808 ; Alias variable for select command @ 0 1809 003a main__command__580select0 equ main__command+0 1810 003a main__command__580select0__byte equ main__command+0 1811 0000 main__command__580select0__bit equ 0 1812 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=2 1813 ; Switch from code bank 0 to code bank 1 before possible transfer (btfss) 1814 2af 5a3 bsf pa0___byte,pa0___bit 1815 2b0 71a btfss main__command__580select0__byte,main__command__580select0__bit 1816 2b1 ab7 goto label580__1false 1817 label580__1true: 1818 ; if { command @ 0 } body start 1819 ; ramp1 := temp 1820 2b2 21b movf main__temp,w 1821 ; Switch from register bank 1 to register bank 0 (which contains ramp1) 1822 2b3 4a4 bcf rp0___byte,rp0___bit 1823 ; Register bank is now 0 1824 2b4 031 movwf ramp1 1825 ; if { command @ 0 } body end 1826 ; Switch from register bank 0 to register bank 1 1827 2b5 5a4 bsf rp0___byte,rp0___bit 1828 ; Register bank is now 1 1829 2b6 abb goto label580__1end 1830 label580__1false: 1831 ; else body start 1832 ; ramp0 := temp 1833 2b7 21b movf main__temp,w 1834 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 1835 2b8 4a4 bcf rp0___byte,rp0___bit 1836 ; Register bank is now 0 1837 2b9 030 movwf ramp0 1838 ; else body end 1839 ; if exp=` command @ 0 ' generic 1840 ; Switch from register bank 0 to register bank 1 1841 2ba 5a4 bsf rp0___byte,rp0___bit 1842 ; Register bank is now 1 1843 label580__1end: 1844 ; Other expression=`{ command @ 0 }' delay=-1 1845 ; if { command @ 0 } end 1846 ; call set_up {{ }} 1847 ; Switch from register bank 1 to register bank 0 1848 2bb 4a4 bcf rp0___byte,rp0___bit 1849 ; Register bank is now 0 1850 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1851 2bc 4a3 bcf pa0___byte,pa0___bit 1852 2bd 98e call set_up 1853 ; Switch from register bank 0 to register bank 1 1854 2be 5a4 bsf rp0___byte,rp0___bit 1855 ; Register bank is now 1 1856 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1857 2bf 5a3 bsf pa0___byte,pa0___bit 1858 2c0 af6 goto switch__576end 1859 switch__576block587: 1860 ; Set Failsafe < Command = 1000 0010 > : 1861 ; fail_safe := get_byte {{ }} 1862 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1863 2c1 4a3 bcf pa0___byte,pa0___bit 1864 2c2 93c call get_byte 1865 2c3 213 movf get_byte__0return__byte,w 1866 ; Switch from register bank 1 to register bank 0 (which contains fail_safe) 1867 2c4 4a4 bcf rp0___byte,rp0___bit 1868 ; Register bank is now 0 1869 2c5 036 movwf fail_safe 1870 ; fail_safe_high_counter := fail_safe 1871 2c6 038 movwf fail_safe_high_counter 1872 ; fail_safe_low_counter := 0 1873 2c7 079 clrf fail_safe_low_counter 1874 ; Switch from register bank 0 to register bank 1 1875 2c8 5a4 bsf rp0___byte,rp0___bit 1876 ; Register bank is now 1 1877 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1878 2c9 5a3 bsf pa0___byte,pa0___bit 1879 2ca af6 goto switch__576end 1880 switch__576block593: 1881 ; Reset Failsafe < Command = 1000 0011 > : 1882 ; fail_safe_low_counter := 0 1883 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_low_counter) 1884 2cb 4a4 bcf rp0___byte,rp0___bit 1885 ; Register bank is now 0 1886 2cc 079 clrf fail_safe_low_counter 1887 ; fail_safe_high_counter := fail_safe 1888 2cd 216 movf fail_safe,w 1889 2ce 038 movwf fail_safe_high_counter 1890 ; Switch from register bank 0 to register bank 1 1891 2cf 5a4 bsf rp0___byte,rp0___bit 1892 ; Register bank is now 1 1893 2d0 af6 goto switch__576end 1894 switch__576block598: 1895 ; Set Speed < Command = 1000 01 dm > : 1896 ; temp := get_byte {{ }} 1897 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1898 2d1 4a3 bcf pa0___byte,pa0___bit 1899 2d2 93c call get_byte 1900 2d3 213 movf get_byte__0return__byte,w 1901 2d4 03b movwf main__temp 1902 ; if { command @ 0 } start 1903 ; Alias variable for select command @ 0 1904 003a main__command__601select0 equ main__command+0 1905 003a main__command__601select0__byte equ main__command+0 1906 0000 main__command__601select0__bit equ 0 1907 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=5 false_delay=5 true_size=5 false_size=5 1908 ; Switch from code bank 0 to code bank 1 before possible transfer (btfss) 1909 2d5 5a3 bsf pa0___byte,pa0___bit 1910 2d6 71a btfss main__command__601select0__byte,main__command__601select0__bit 1911 2d7 ae5 goto label601__1false 1912 label601__1true: 1913 ; if { command @ 0 } body start 1914 ; Motor 1 : 1915 ; desired_speed1 := temp 1916 2d8 21b movf main__temp,w 1917 2d9 02f movwf desired_speed1 1918 ; motor1_direction := command @ 1 1919 ; Alias variable for select command @ 1 1920 003a main__command__604select0 equ main__command+0 1921 003a main__command__604select0__byte equ main__command+0 1922 0001 main__command__604select0__bit equ 1 1923 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1924 2da 4a4 bcf rp0___byte,rp0___bit 1925 ; Register bank is now 0 1926 2db 47e bcf motor1_direction__byte,motor1_direction__bit 1927 ; Switch from register bank 0 to register bank 1 (which contains main__command__604select0__byte) 1928 2dc 5a4 bsf rp0___byte,rp0___bit 1929 ; Register bank is now 1 1930 2dd 443 bcf z___byte,z___bit 1931 2de 63a btfsc main__command__604select0__byte,main__command__604select0__bit 1932 2df 543 bsf z___byte,z___bit 1933 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 1934 2e0 4a4 bcf rp0___byte,rp0___bit 1935 ; Register bank is now 0 1936 2e1 643 btfsc z___byte,z___bit 1937 2e2 57e bsf motor1_direction__byte,motor1_direction__bit 1938 ; if { command @ 0 } body end 1939 ; Switch from register bank 0 to register bank 1 1940 2e3 5a4 bsf rp0___byte,rp0___bit 1941 ; Register bank is now 1 1942 2e4 af1 goto label601__1end 1943 label601__1false: 1944 ; else body start 1945 ; Motor 0 : 1946 ; desired_speed0 := temp 1947 2e5 21b movf main__temp,w 1948 2e6 02e movwf desired_speed0 1949 ; motor0_direction := command @ 1 1950 ; Alias variable for select command @ 1 1951 003a main__command__608select0 equ main__command+0 1952 003a main__command__608select0__byte equ main__command+0 1953 0001 main__command__608select0__bit equ 1 1954 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1955 2e7 4a4 bcf rp0___byte,rp0___bit 1956 ; Register bank is now 0 1957 2e8 45e bcf motor0_direction__byte,motor0_direction__bit 1958 ; Switch from register bank 0 to register bank 1 (which contains main__command__608select0__byte) 1959 2e9 5a4 bsf rp0___byte,rp0___bit 1960 ; Register bank is now 1 1961 2ea 443 bcf z___byte,z___bit 1962 2eb 63a btfsc main__command__608select0__byte,main__command__608select0__bit 1963 2ec 543 bsf z___byte,z___bit 1964 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 1965 2ed 4a4 bcf rp0___byte,rp0___bit 1966 ; Register bank is now 0 1967 2ee 643 btfsc z___byte,z___bit 1968 2ef 55e bsf motor0_direction__byte,motor0_direction__bit 1969 ; else body end 1970 ; if exp=` command @ 0 ' generic 1971 ; Switch from register bank 0 to register bank 1 1972 2f0 5a4 bsf rp0___byte,rp0___bit 1973 ; Register bank is now 1 1974 label601__1end: 1975 ; Other expression=`{ command @ 0 }' delay=-1 1976 ; if { command @ 0 } end 1977 ; call set_up {{ }} 1978 ; Switch from register bank 1 to register bank 0 1979 2f1 4a4 bcf rp0___byte,rp0___bit 1980 ; Register bank is now 0 1981 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1982 2f2 4a3 bcf pa0___byte,pa0___bit 1983 2f3 98e call set_up 1984 ; Switch from register bank 0 to register bank 1 1985 2f4 5a4 bsf rp0___byte,rp0___bit 1986 ; Register bank is now 1 1987 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1988 2f5 5a3 bsf pa0___byte,pa0___bit 1989 switch__576end: 1990 2f6 bbe goto switch__573end 1991 switch__573block614: 1992 ; Command = 1000 1 xxx : 1993 ; if { command @ 2 } start 1994 ; Alias variable for select command @ 2 1995 003a main__command__616select0 equ main__command+0 1996 003a main__command__616select0__byte equ main__command+0 1997 0002 main__command__616select0__bit equ 2 1998 ; expression=`{ command @ 2 }' exp_delay=0 true_delay=-1 false_delay=-1 true_size=9 false_size=9 1999 2f7 75a btfss main__command__616select0__byte,main__command__616select0__bit 2000 2f8 b11 goto label616__1false 2001 label616__1true: 2002 ; if { command @ 2 } body start 2003 ; Set direction < Command = 1000 11 dm > : 2004 ; if { command @ 0 } start 2005 ; Alias variable for select command @ 0 2006 003a main__command__618select0 equ main__command+0 2007 003a main__command__618select0__byte equ main__command+0 2008 0000 main__command__618select0__bit equ 0 2009 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=3 true_size=3 false_size=3 2010 2f9 71a btfss main__command__618select0__byte,main__command__618select0__bit 2011 2fa b06 goto label618__1false 2012 label618__1true: 2013 ; if { command @ 0 } body start 2014 ; Motor 1 : 2015 ; motor1_direction := command @ 1 2016 ; Alias variable for select command @ 1 2017 003a main__command__620select0 equ main__command+0 2018 003a main__command__620select0__byte equ main__command+0 2019 0001 main__command__620select0__bit equ 1 2020 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2021 2fb 4a4 bcf rp0___byte,rp0___bit 2022 ; Register bank is now 0 2023 2fc 47e bcf motor1_direction__byte,motor1_direction__bit 2024 ; Switch from register bank 0 to register bank 1 (which contains main__command__620select0__byte) 2025 2fd 5a4 bsf rp0___byte,rp0___bit 2026 ; Register bank is now 1 2027 2fe 443 bcf z___byte,z___bit 2028 2ff 63a btfsc main__command__620select0__byte,main__command__620select0__bit 2029 300 543 bsf z___byte,z___bit 2030 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2031 301 4a4 bcf rp0___byte,rp0___bit 2032 ; Register bank is now 0 2033 302 643 btfsc z___byte,z___bit 2034 303 57e bsf motor1_direction__byte,motor1_direction__bit 2035 ; if { command @ 0 } body end 2036 ; Switch from register bank 0 to register bank 1 2037 304 5a4 bsf rp0___byte,rp0___bit 2038 ; Register bank is now 1 2039 305 b10 goto label618__1end 2040 label618__1false: 2041 ; else body start 2042 ; Motor 0 : 2043 ; motor0_direction := command @ 1 2044 ; Alias variable for select command @ 1 2045 003a main__command__623select0 equ main__command+0 2046 003a main__command__623select0__byte equ main__command+0 2047 0001 main__command__623select0__bit equ 1 2048 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2049 306 4a4 bcf rp0___byte,rp0___bit 2050 ; Register bank is now 0 2051 307 45e bcf motor0_direction__byte,motor0_direction__bit 2052 ; Switch from register bank 0 to register bank 1 (which contains main__command__623select0__byte) 2053 308 5a4 bsf rp0___byte,rp0___bit 2054 ; Register bank is now 1 2055 309 443 bcf z___byte,z___bit 2056 30a 63a btfsc main__command__623select0__byte,main__command__623select0__bit 2057 30b 543 bsf z___byte,z___bit 2058 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2059 30c 4a4 bcf rp0___byte,rp0___bit 2060 ; Register bank is now 0 2061 30d 643 btfsc z___byte,z___bit 2062 30e 55e bsf motor0_direction__byte,motor0_direction__bit 2063 ; else body end 2064 ; if exp=` command @ 0 ' generic 2065 ; Switch from register bank 0 to register bank 1 2066 30f 5a4 bsf rp0___byte,rp0___bit 2067 ; Register bank is now 1 2068 label618__1end: 2069 ; Other expression=`{ command @ 0 }' delay=-1 2070 ; if { command @ 0 } end 2071 ; if { command @ 2 } body end 2072 310 b28 goto label616__1end 2073 label616__1false: 2074 ; else body start 2075 ; Set mode < Command = 1000 10 xm > : 2076 ; if { command @ 0 } start 2077 ; Alias variable for select command @ 0 2078 003a main__command__627select0 equ main__command+0 2079 003a main__command__627select0__byte equ main__command+0 2080 0000 main__command__627select0__bit equ 0 2081 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=3 true_size=3 false_size=3 2082 311 71a btfss main__command__627select0__byte,main__command__627select0__bit 2083 312 b1e goto label627__1false 2084 label627__1true: 2085 ; if { command @ 0 } body start 2086 ; Motor 1 : 2087 ; motor1_mode := command @ 1 2088 ; Alias variable for select command @ 1 2089 003a main__command__629select0 equ main__command+0 2090 003a main__command__629select0__byte equ main__command+0 2091 0001 main__command__629select0__bit equ 1 2092 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2093 313 4a4 bcf rp0___byte,rp0___bit 2094 ; Register bank is now 0 2095 314 43e bcf motor1_mode__byte,motor1_mode__bit 2096 ; Switch from register bank 0 to register bank 1 (which contains main__command__629select0__byte) 2097 315 5a4 bsf rp0___byte,rp0___bit 2098 ; Register bank is now 1 2099 316 443 bcf z___byte,z___bit 2100 317 63a btfsc main__command__629select0__byte,main__command__629select0__bit 2101 318 543 bsf z___byte,z___bit 2102 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2103 319 4a4 bcf rp0___byte,rp0___bit 2104 ; Register bank is now 0 2105 31a 643 btfsc z___byte,z___bit 2106 31b 53e bsf motor1_mode__byte,motor1_mode__bit 2107 ; if { command @ 0 } body end 2108 ; Switch from register bank 0 to register bank 1 2109 31c 5a4 bsf rp0___byte,rp0___bit 2110 ; Register bank is now 1 2111 31d b28 goto label627__1end 2112 label627__1false: 2113 ; else body start 2114 ; Motor 0 : 2115 ; motor0_mode := command @ 1 2116 ; Alias variable for select command @ 1 2117 003a main__command__632select0 equ main__command+0 2118 003a main__command__632select0__byte equ main__command+0 2119 0001 main__command__632select0__bit equ 1 2120 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2121 31e 4a4 bcf rp0___byte,rp0___bit 2122 ; Register bank is now 0 2123 31f 41e bcf motor0_mode__byte,motor0_mode__bit 2124 ; Switch from register bank 0 to register bank 1 (which contains main__command__632select0__byte) 2125 320 5a4 bsf rp0___byte,rp0___bit 2126 ; Register bank is now 1 2127 321 443 bcf z___byte,z___bit 2128 322 63a btfsc main__command__632select0__byte,main__command__632select0__bit 2129 323 543 bsf z___byte,z___bit 2130 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2131 324 4a4 bcf rp0___byte,rp0___bit 2132 ; Register bank is now 0 2133 325 643 btfsc z___byte,z___bit 2134 326 51e bsf motor0_mode__byte,motor0_mode__bit 2135 ; else body end 2136 ; if exp=` command @ 0 ' generic 2137 ; Switch from register bank 0 to register bank 1 2138 327 5a4 bsf rp0___byte,rp0___bit 2139 ; Register bank is now 1 2140 label627__1end: 2141 ; Other expression=`{ command @ 0 }' delay=-1 2142 ; if { command @ 0 } end 2143 ; else body end 2144 ; if exp=` command @ 2 ' generic 2145 label616__1end: 2146 ; Other expression=`{ command @ 2 }' delay=-1 2147 ; if { command @ 2 } end 2148 ; call set_up {{ }} 2149 ; Switch from register bank 1 to register bank 0 2150 328 4a4 bcf rp0___byte,rp0___bit 2151 ; Register bank is now 0 2152 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2153 329 4a3 bcf pa0___byte,pa0___bit 2154 32a 98e call set_up 2155 ; Switch from register bank 0 to register bank 1 2156 32b 5a4 bsf rp0___byte,rp0___bit 2157 ; Register bank is now 1 2158 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2159 32c 5a3 bsf pa0___byte,pa0___bit 2160 32d bbe goto switch__573end 2161 switch__573block637: 2162 ; Set Prescaler < Command = 1001 0 ppp > : 2163 ; option := option_mask | {{ command & 7 }} 2164 32e c07 movlw 7 2165 32f 15a andwf main__command,w 2166 330 dc0 iorlw 192 2167 331 032 movwf option 2168 ; Option is in W register : 2169 ; inline assembly statements begin 2170 332 002 option 2171 ; inline assembly statements end 2172 333 bbe goto switch__573end 2173 switch__573block645: 2174 ; Command = 1001 1 xxx : 2175 ; switch { command & 7 } 2176 334 c07 movlw 7 2177 335 15a andwf main__command,w 2178 ; case 0 2179 ; case 1 2180 ; case 2 3 2181 ; case 4 5 2182 ; case 6 7 2183 336 a09 goto switch__647block_start 2184 switch__647block648: 2185 ; Read Failsafe < Command = 1001 1000 > : 2186 ; call send_byte {{ fail_safe }} 2187 ; Switch from register bank 1 to register bank 0 (which contains fail_safe) 2188 337 4a4 bcf rp0___byte,rp0___bit 2189 ; Register bank is now 0 2190 338 216 movf fail_safe,w 2191 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2192 339 5a4 bsf rp0___byte,rp0___bit 2193 ; Register bank is now 1 2194 33a 037 movwf send_byte__char 2195 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2196 33b 4a3 bcf pa0___byte,pa0___bit 2197 33c 960 call send_byte 2198 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2199 33d 5a3 bsf pa0___byte,pa0___bit 2200 33e b7c goto switch__647end 2201 switch__647block652: 2202 ; Read Prescaler < Command = 1001 1001 > : 2203 ; call send_byte {{ option & 7 }} 2204 33f c07 movlw 7 2205 340 152 andwf option,w 2206 341 037 movwf send_byte__char 2207 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2208 342 4a3 bcf pa0___byte,pa0___bit 2209 343 960 call send_byte 2210 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2211 344 5a3 bsf pa0___byte,pa0___bit 2212 345 b7c goto switch__647end 2213 switch__647block656: 2214 ; Read Speed < Command = 1001 101 m > : 2215 ; if { command @ 0 } start 2216 ; Alias variable for select command @ 0 2217 003a main__command__658select0 equ main__command+0 2218 003a main__command__658select0__byte equ main__command+0 2219 0000 main__command__658select0__bit equ 0 2220 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=-1 false_delay=-1 true_size=1 false_size=1 2221 346 61a btfsc main__command__658select0__byte,main__command__658select0__bit 2222 ; if { command @ 0 } body start 2223 ; call send_byte {{ actual_speed1 }} 2224 347 209 movf actual_speed1,w 2225 ; 2 instructions found for sharing 2226 348 71a btfss main__command__658select0__byte,main__command__658select0__bit 2227 ; else body start 2228 ; call send_byte {{ actual_speed0 }} 2229 349 208 movf actual_speed0,w 2230 ; 2 instructions found for sharing 2231 ; if exp=` command @ 0 ' single true and false skip delay=4 2232 ; Other expression=`{ command @ 0 }' delay=4 2233 ; 2 shared instructions follow 2234 34a 037 movwf send_byte__char 2235 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2236 34b 4a3 bcf pa0___byte,pa0___bit 2237 34c 960 call send_byte 2238 ; if { command @ 0 } end 2239 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2240 34d 5a3 bsf pa0___byte,pa0___bit 2241 34e b7c goto switch__647end 2242 switch__647block664: 2243 ; Read Mode / Direction < Command = 1001 110 m > : 2244 ; temp := 0 2245 34f 07b clrf main__temp 2246 ; if { command @ 0 } start 2247 ; Alias variable for select command @ 0 2248 003a main__command__667select0 equ main__command+0 2249 003a main__command__667select0__byte equ main__command+0 2250 0000 main__command__667select0__bit equ 0 2251 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 2252 350 71a btfss main__command__667select0__byte,main__command__667select0__bit 2253 351 b5b goto label667__1false 2254 label667__1true: 2255 ; if { command @ 0 } body start 2256 ; Motor 1 : 2257 ; if { motor1_direction } start 2258 ; expression=`{ motor1_direction }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2259 ; Switch from register bank 1 to register bank 0 (which contains motor1_direction__byte) 2260 352 4a4 bcf rp0___byte,rp0___bit 2261 ; Register bank is now 0 2262 353 67e btfsc motor1_direction__byte,motor1_direction__bit 2263 ; if { motor1_direction } body start 2264 ; temp @ 1 := 1 2265 ; Select temp @ 1 2266 003b main__temp__670select0 equ main__temp+0 2267 003b main__temp__670select0__byte equ main__temp+0 2268 0001 main__temp__670select0__bit equ 1 2269 ; Switch from register bank 0 to register bank 1 (which contains main__temp__670select0__byte) 2270 354 5a4 bsf rp0___byte,rp0___bit 2271 ; Register bank is now 1 2272 355 53b bsf main__temp__670select0__byte,main__temp__670select0__bit 2273 ; if { motor1_direction } body end 2274 ; if exp=`motor1_direction' false skip delay=2 2275 ; Other expression=`{ motor1_direction }' delay=2 2276 ; if { motor1_direction } end 2277 ; if { motor1_mode } start 2278 ; expression=`{ motor1_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2279 ; Switch from register bank 1 to register bank 0 (which contains motor1_mode__byte) 2280 356 4a4 bcf rp0___byte,rp0___bit 2281 ; Register bank is now 0 2282 357 63e btfsc motor1_mode__byte,motor1_mode__bit 2283 ; if { motor1_mode } body start 2284 ; temp @ 0 := 1 2285 ; Select temp @ 0 2286 003b main__temp__673select0 equ main__temp+0 2287 003b main__temp__673select0__byte equ main__temp+0 2288 0000 main__temp__673select0__bit equ 0 2289 ; Switch from register bank 0 to register bank 1 (which contains main__temp__673select0__byte) 2290 358 5a4 bsf rp0___byte,rp0___bit 2291 ; Register bank is now 1 2292 359 51b bsf main__temp__673select0__byte,main__temp__673select0__bit 2293 ; if { motor1_mode } body end 2294 ; if exp=`motor1_mode' false skip delay=2 2295 ; Other expression=`{ motor1_mode }' delay=2 2296 ; if { motor1_mode } end 2297 ; if { command @ 0 } body end 2298 35a b63 goto label667__1end 2299 label667__1false: 2300 ; else body start 2301 ; Motor 0 : 2302 ; if { motor0_direction } start 2303 ; expression=`{ motor0_direction }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2304 ; Switch from register bank 1 to register bank 0 (which contains motor0_direction__byte) 2305 35b 4a4 bcf rp0___byte,rp0___bit 2306 ; Register bank is now 0 2307 35c 65e btfsc motor0_direction__byte,motor0_direction__bit 2308 ; if { motor0_direction } body start 2309 ; temp @ 1 := 1 2310 ; Select temp @ 1 2311 003b main__temp__678select0 equ main__temp+0 2312 003b main__temp__678select0__byte equ main__temp+0 2313 0001 main__temp__678select0__bit equ 1 2314 ; Switch from register bank 0 to register bank 1 (which contains main__temp__678select0__byte) 2315 35d 5a4 bsf rp0___byte,rp0___bit 2316 ; Register bank is now 1 2317 35e 53b bsf main__temp__678select0__byte,main__temp__678select0__bit 2318 ; if { motor0_direction } body end 2319 ; if exp=`motor0_direction' false skip delay=2 2320 ; Other expression=`{ motor0_direction }' delay=2 2321 ; if { motor0_direction } end 2322 ; if { motor0_mode } start 2323 ; expression=`{ motor0_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2324 ; Switch from register bank 1 to register bank 0 (which contains motor0_mode__byte) 2325 35f 4a4 bcf rp0___byte,rp0___bit 2326 ; Register bank is now 0 2327 360 61e btfsc motor0_mode__byte,motor0_mode__bit 2328 ; if { motor0_mode } body start 2329 ; temp @ 0 := 1 2330 ; Select temp @ 0 2331 003b main__temp__681select0 equ main__temp+0 2332 003b main__temp__681select0__byte equ main__temp+0 2333 0000 main__temp__681select0__bit equ 0 2334 ; Switch from register bank 0 to register bank 1 (which contains main__temp__681select0__byte) 2335 361 5a4 bsf rp0___byte,rp0___bit 2336 ; Register bank is now 1 2337 362 51b bsf main__temp__681select0__byte,main__temp__681select0__bit 2338 ; if { motor0_mode } body end 2339 ; if exp=`motor0_mode' false skip delay=2 2340 ; Other expression=`{ motor0_mode }' delay=2 2341 ; if { motor0_mode } end 2342 ; else body end 2343 ; if exp=` command @ 0 ' generic 2344 label667__1end: 2345 ; Other expression=`{ command @ 0 }' delay=-1 2346 ; if { command @ 0 } end 2347 ; call send_byte {{ temp }} 2348 363 21b movf main__temp,w 2349 364 037 movwf send_byte__char 2350 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2351 365 4a3 bcf pa0___byte,pa0___bit 2352 366 960 call send_byte 2353 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2354 367 5a3 bsf pa0___byte,pa0___bit 2355 368 b7c goto switch__647end 2356 switch__647block686: 2357 ; Read Ramp < Command = 1001 101 m > : 2358 ; if { command @ 0 } start 2359 ; Alias variable for select command @ 0 2360 003a main__command__688select0 equ main__command+0 2361 003a main__command__688select0__byte equ main__command+0 2362 0000 main__command__688select0__bit equ 0 2363 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 2364 369 443 bcf z___byte,z___bit 2365 36a 61a btfsc main__command__688select0__byte,main__command__688select0__bit 2366 36b 543 bsf z___byte,z___bit 2367 ; if { command @ 0 } body start 2368 ; temp := ramp1 2369 ; Switch from register bank 1 to register bank 0 (which contains ramp1) 2370 36c 4a4 bcf rp0___byte,rp0___bit 2371 ; Register bank is now 0 2372 36d 643 btfsc z___byte,z___bit 2373 36e 211 movf ramp1,w 2374 ; 1 instructions found for sharing 2375 ; Switch from register bank 0 to register bank 1 (which contains main__command__688select0__byte) 2376 36f 5a4 bsf rp0___byte,rp0___bit 2377 ; Register bank is now 1 2378 370 443 bcf z___byte,z___bit 2379 371 61a btfsc main__command__688select0__byte,main__command__688select0__bit 2380 372 543 bsf z___byte,z___bit 2381 ; else body start 2382 ; temp := ramp0 2383 ; Switch from register bank 1 to register bank 0 (which contains ramp0) 2384 373 4a4 bcf rp0___byte,rp0___bit 2385 ; Register bank is now 0 2386 374 743 btfss z___byte,z___bit 2387 375 210 movf ramp0,w 2388 ; 1 instructions found for sharing 2389 ; if exp=` command @ 0 ' single true and false skip delay=4 2390 ; Other expression=`{ command @ 0 }' delay=4 2391 ; 1 shared instructions follow 2392 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 2393 376 5a4 bsf rp0___byte,rp0___bit 2394 ; Register bank is now 1 2395 377 03b movwf main__temp 2396 ; if { command @ 0 } end 2397 ; call send_byte {{ temp }} 2398 378 037 movwf send_byte__char 2399 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2400 379 4a3 bcf pa0___byte,pa0___bit 2401 37a 960 call send_byte 2402 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2403 37b 5a3 bsf pa0___byte,pa0___bit 2404 switch__647end: 2405 37c bbe goto switch__573end 2406 switch__573block697: 2407 ; Command = 0110 0 xxx : 2408 ; switch { command & 7 } 2409 37d c07 movlw 7 2410 37e 15a andwf main__command,w 2411 ; case 0 2412 ; case 1 2413 ; case 2 2414 ; case 3 2415 ; case 4 5 6 7 2416 37f a12 goto switch__699block_start 2417 switch__699block700: 2418 ; Read Failsafe Errors < Command = 1010 0000 > : 2419 ; call send_byte {{ fail_safe_errors }} 2420 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_errors) 2421 380 4a4 bcf rp0___byte,rp0___bit 2422 ; Register bank is now 0 2423 381 217 movf fail_safe_errors,w 2424 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2425 382 5a4 bsf rp0___byte,rp0___bit 2426 ; Register bank is now 1 2427 383 037 movwf send_byte__char 2428 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2429 384 4a3 bcf pa0___byte,pa0___bit 2430 385 960 call send_byte 2431 ; fail_safe_errors := 0 2432 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_errors) 2433 386 4a4 bcf rp0___byte,rp0___bit 2434 ; Register bank is now 0 2435 387 077 clrf fail_safe_errors 2436 ; Switch from register bank 0 to register bank 1 2437 388 5a4 bsf rp0___byte,rp0___bit 2438 ; Register bank is now 1 2439 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2440 389 5a3 bsf pa0___byte,pa0___bit 2441 38a baa goto switch__699end 2442 switch__699block705: 2443 ; Read Failsafe Counter < Command = 1010 0001 > : 2444 ; call send_byte {{ fail_safe_high_counter }} 2445 ; Switch from register bank 1 to register bank 0 (which contains fail_safe_high_counter) 2446 38b 4a4 bcf rp0___byte,rp0___bit 2447 ; Register bank is now 0 2448 38c 218 movf fail_safe_high_counter,w 2449 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2450 38d 5a4 bsf rp0___byte,rp0___bit 2451 ; Register bank is now 1 2452 38e 037 movwf send_byte__char 2453 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2454 38f 4a3 bcf pa0___byte,pa0___bit 2455 390 960 call send_byte 2456 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2457 391 5a3 bsf pa0___byte,pa0___bit 2458 392 baa goto switch__699end 2459 switch__699block709: 2460 ; Read Actual Speed 0 < Command = 1010 0010 > : 2461 ; call send_byte {{ actual_speed0 }} 2462 393 208 movf actual_speed0,w 2463 394 037 movwf send_byte__char 2464 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2465 395 4a3 bcf pa0___byte,pa0___bit 2466 396 960 call send_byte 2467 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2468 397 5a3 bsf pa0___byte,pa0___bit 2469 398 baa goto switch__699end 2470 switch__699block713: 2471 ; Read Actual Speed < Command = 1010 001 m > : 2472 ; call send_byte {{ actual_speed1 }} 2473 399 209 movf actual_speed1,w 2474 39a 037 movwf send_byte__char 2475 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2476 39b 4a3 bcf pa0___byte,pa0___bit 2477 39c 960 call send_byte 2478 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2479 39d 5a3 bsf pa0___byte,pa0___bit 2480 39e baa goto switch__699end 2481 switch__699block717: 2482 ; Reset everything < Command = 1010 01 om > : 2483 ; if { command @ 0 } start 2484 ; Alias variable for select command @ 0 2485 003a main__command__719select0 equ main__command+0 2486 003a main__command__719select0__byte equ main__command+0 2487 0000 main__command__719select0__bit equ 0 2488 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 2489 39f 71a btfss main__command__719select0__byte,main__command__719select0__bit 2490 3a0 ba6 goto label719__1false 2491 label719__1true: 2492 ; if { command @ 0 } body start 2493 ; Motor 1 : 2494 ; motor1e := command @ 1 2495 ; Alias variable for select command @ 1 2496 003a main__command__721select0 equ main__command+0 2497 003a main__command__721select0__byte equ main__command+0 2498 0001 main__command__721select0__bit equ 1 2499 3a1 73a btfss main__command__721select0__byte,main__command__721select0__bit 2500 3a2 467 bcf motor1e__byte,motor1e__bit 2501 3a3 63a btfsc main__command__721select0__byte,main__command__721select0__bit 2502 3a4 567 bsf motor1e__byte,motor1e__bit 2503 ; if { command @ 0 } body end 2504 3a5 baa goto label719__1end 2505 label719__1false: 2506 ; else body start 2507 ; Motor 0 : 2508 ; motor0e := command @ 1 2509 ; Alias variable for select command @ 1 2510 003a main__command__724select0 equ main__command+0 2511 003a main__command__724select0__byte equ main__command+0 2512 0001 main__command__724select0__bit equ 1 2513 3a6 73a btfss main__command__724select0__byte,main__command__724select0__bit 2514 3a7 447 bcf motor0e__byte,motor0e__bit 2515 3a8 63a btfsc main__command__724select0__byte,main__command__724select0__bit 2516 3a9 547 bsf motor0e__byte,motor0e__bit 2517 ; else body end 2518 ; if exp=` command @ 0 ' generic 2519 label719__1end: 2520 ; Other expression=`{ command @ 0 }' delay=-1 2521 ; if { command @ 0 } end 2522 switch__699end: 2523 3aa bbe goto switch__573end 2524 switch__573block729: 2525 ; Command = 1010 1 xxx : 2526 ; switch { command & 3 } 2527 3ab c03 movlw 3 2528 3ac 15a andwf main__command,w 2529 ; case 0 2530 ; case 1 2531 3ad a1b goto switch__731block_start 2532 switch__731block732: 2533 ; Reset < Command = 1010 1000 > : 2534 ; call reset {{ }} 2535 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2536 3ae 4a3 bcf pa0___byte,pa0___bit 2537 3af 9d4 call reset 2538 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2539 3b0 5a3 bsf pa0___byte,pa0___bit 2540 3b1 bbd goto switch__731end 2541 switch__731block736: 2542 ; Read On / Off < Command = 1010 1001 > : 2543 ; temp := 0 2544 3b2 07b clrf main__temp 2545 ; if { motor0e } start 2546 ; expression=`{ motor0e }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2547 3b3 647 btfsc motor0e__byte,motor0e__bit 2548 ; if { motor0e } body start 2549 ; temp @ 0 := 1 2550 ; Select temp @ 0 2551 003b main__temp__740select0 equ main__temp+0 2552 003b main__temp__740select0__byte equ main__temp+0 2553 0000 main__temp__740select0__bit equ 0 2554 3b4 51b bsf main__temp__740select0__byte,main__temp__740select0__bit 2555 ; if { motor0e } body end 2556 ; if exp=`motor0e' false skip delay=2 2557 ; Other expression=`{ motor0e }' delay=2 2558 ; if { motor0e } end 2559 ; if { motor1e } start 2560 ; expression=`{ motor1e }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2561 3b5 667 btfsc motor1e__byte,motor1e__bit 2562 ; if { motor1e } body start 2563 ; temp @ 1 := 1 2564 ; Select temp @ 1 2565 003b main__temp__743select0 equ main__temp+0 2566 003b main__temp__743select0__byte equ main__temp+0 2567 0001 main__temp__743select0__bit equ 1 2568 3b6 53b bsf main__temp__743select0__byte,main__temp__743select0__bit 2569 ; if { motor1e } body end 2570 ; if exp=`motor1e' false skip delay=2 2571 ; Other expression=`{ motor1e }' delay=2 2572 ; if { motor1e } end 2573 ; call send_byte {{ temp }} 2574 3b7 21b movf main__temp,w 2575 3b8 037 movwf send_byte__char 2576 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2577 3b9 4a3 bcf pa0___byte,pa0___bit 2578 3ba 960 call send_byte 2579 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2580 3bb 5a3 bsf pa0___byte,pa0___bit 2581 3bc bbd goto switch__731end 2582 switch__731default747: 2583 ; Do nothing : 2584 switch__731end: 2585 3bd bbe goto switch__573end 2586 switch__573default752: 2587 ; Do nothing : 2588 switch__573end: 2589 3be bf5 goto switch__543end 2590 switch__543block757: 2591 ; Command = 11 xx xxxx : 2592 ; switch { {{ command >> 3 }} & 7 } 2593 3bf 31a rrf main__command,w 2594 3c0 03c movwf main__759byte0 2595 3c1 33c rrf main__759byte0,f 2596 3c2 31c rrf main__759byte0,w 2597 3c3 e07 andlw 7 2598 ; case 7 2599 3c4 a36 goto switch__759block_start 2600 switch__759block760: 2601 ; Shared commands < Command = 1111 1 ccc > : 2602 ; switch { command & 7 } 2603 3c5 c07 movlw 7 2604 3c6 15a andwf main__command,w 2605 ; case 0 2606 ; case 1 2607 ; case 2 2608 ; case 3 2609 ; case 4 2610 ; case 5 2611 ; case 6 2612 ; case 7 2613 3c7 a2d goto switch__762block_start 2614 switch__762block763: 2615 ; Clock Decrement < Command = 1111 1000 > : 2616 ; osccal := osccal - osccal_unit 2617 3c8 cfc movlw 252 2618 3c9 1e5 addwf osccal,f 2619 3ca bf5 goto switch__762end 2620 switch__762block767: 2621 ; Clock Increment < Command = 1111 1001 > : 2622 ; osccal := osccal + osccal_unit 2623 3cb c04 movlw 4 2624 3cc 1e5 addwf osccal,f 2625 3cd bf5 goto switch__762end 2626 switch__762block771: 2627 ; Clock Read < Command = 1111 1010 > : 2628 ; call send_byte {{ osccal }} 2629 3ce 205 movf osccal,w 2630 3cf 037 movwf send_byte__char 2631 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2632 3d0 4a3 bcf pa0___byte,pa0___bit 2633 3d1 960 call send_byte 2634 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2635 3d2 5a3 bsf pa0___byte,pa0___bit 2636 3d3 bf5 goto switch__762end 2637 switch__762block775: 2638 ; Clock Pulse < Command = 1111 1011 > : 2639 ; call send_byte {{ 0 }} 2640 3d4 077 clrf send_byte__char 2641 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2642 3d5 4a3 bcf pa0___byte,pa0___bit 2643 3d6 960 call send_byte 2644 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2645 3d7 5a3 bsf pa0___byte,pa0___bit 2646 3d8 bf5 goto switch__762end 2647 switch__762block779: 2648 ; ID Next < Command = 1111 1100 > : 2649 ; if { id_index >= id . size } start 2650 3d9 c30 movlw 48 2651 3da 091 subwf id_index,w 2652 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2653 3db 603 btfsc c___byte,c___bit 2654 ; if { id_index >= id . size } body start 2655 ; id_index := 0 2656 3dc 071 clrf id_index 2657 ; if { id_index >= id . size } body end 2658 ; if exp=` id_index >= id . size ' false skip delay=4 2659 ; Other expression=`{ id_index >= id . size }' delay=4 2660 ; if { id_index >= id . size } end 2661 ; call send_byte {{ id ~~ {{ id_index }} }} 2662 3dd 291 incf id_index,w 2663 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2664 3de 4a3 bcf pa0___byte,pa0___bit 2665 3df 90a call id 2666 3e0 037 movwf send_byte__char 2667 3e1 960 call send_byte 2668 ; id_index := id_index + 1 2669 3e2 2b1 incf id_index,f 2670 ; if { id_index >= id . size } start 2671 3e3 c30 movlw 48 2672 3e4 091 subwf id_index,w 2673 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2674 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) 2675 3e5 5a3 bsf pa0___byte,pa0___bit 2676 3e6 603 btfsc c___byte,c___bit 2677 ; if { id_index >= id . size } body start 2678 ; id_index := 0 2679 3e7 071 clrf id_index 2680 ; if { id_index >= id . size } body end 2681 ; if exp=` id_index >= id . size ' false skip delay=4 2682 ; Other expression=`{ id_index >= id . size }' delay=4 2683 ; if { id_index >= id . size } end 2684 3e8 bf5 goto switch__762end 2685 switch__762block790: 2686 ; ID Reset < Command = 1111 1101 > : 2687 ; id_index := 0 2688 3e9 071 clrf id_index 2689 3ea bf5 goto switch__762end 2690 switch__762block794: 2691 ; Glitch Read < Command = 1111 1110 > : 2692 ; call send_byte {{ glitch }} 2693 3eb 210 movf glitch,w 2694 3ec 037 movwf send_byte__char 2695 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2696 3ed 4a3 bcf pa0___byte,pa0___bit 2697 3ee 960 call send_byte 2698 ; glitch := 0 2699 3ef 070 clrf glitch 2700 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2701 3f0 5a3 bsf pa0___byte,pa0___bit 2702 3f1 bf5 goto switch__762end 2703 switch__762block799: 2704 ; Glitch < Command = 1111 1111 > : 2705 ; if { glitch != 0xff } start 2706 3f2 290 incf glitch,w 2707 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 2708 3f3 743 btfss z___byte,z___bit 2709 ; if { glitch != 0xff } body start 2710 ; glitch := glitch + 1 2711 3f4 2b0 incf glitch,f 2712 ; if { glitch != 0xff } body end 2713 ; if exp=` glitch != 0xff ' false skip delay=3 2714 ; Other expression=`{ glitch != 0xff }' delay=3 2715 ; if { glitch != 0xff } end 2716 switch__762end: 2717 switch__759end: 2718 switch__543end: 2719 3f5 a47 goto main__538loop__forever 2720 ; loop_forever ... end 2721 ; procedure main end 2722 2723 ; Register bank 0 used 22 bytes of 24 available bytes 2724 ; Register bank 1 used 13 bytes of 16 available bytes 2725 ; Register bank 2 used 0 bytes of 16 available bytes 2726 ; Register bank 3 used 0 bytes of 16 available bytes 2727 2728 end