1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0049 global__bit__variables__bank0 equ 73 5 00a0 global__bit__variables__bank1 equ 160 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 0003 rp0___byte equ 3 13 0005 rp0___bit equ 5 14 0003 rp1___byte equ 3 15 0006 rp1___bit equ 6 16 0003 irp___byte equ 3 17 0007 irp___bit equ 7 18 0085 trisa___register equ 0x85 19 0086 trisb___register equ 0x86 20 0004 fsr___register equ 4 21 000a pclath___register equ 10 22 org 0 23 start: 24 000 0000 nop 25 001 0000 nop 26 002 0000 nop 27 003 2805 goto skip___interrupt 28 interrupt___vector: 29 004 0009 retfie 30 skip___interrupt: 31 ; Use oscillator calibration stored in high memory 32 005 27ff call 2047 33 ; Switch from register bank 0 to register bank 1 (which contains 143) 34 006 1683 bsf rp0___byte,rp0___bit 35 ; Register bank is now 1 36 007 008f movwf 143 37 ; Initialize A/D system to allow digital I/O 38 008 3007 movlw 7 39 009 009f movwf 159 40 ; Switch from register bank 1 to register bank 0 (which contains 31) 41 00a 1283 bcf rp0___byte,rp0___bit 42 ; Register bank is now 0 43 00b 019f clrf 31 44 ; Initialize TRIS registers 45 00c 30df movlw 223 46 00d 0065 tris 5 47 00e 018a clrf pclath___register 48 00f 2843 goto main 49 ; comment ############################################################################# 50 ; comment {} 51 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 52 ; comment {All rights reserved .} 53 ; comment {} 54 ; comment {Permission to use , copy , modify , distribute , and sell this software} 55 ; comment {for any purpose is hereby granted without fee provided that the above} 56 ; comment {copyright notice and this permission are retained . The author makes} 57 ; comment {no representations about the suitability of this software for any purpose .} 58 ; comment {It is provided { as is } without express or implied warranty .} 59 ; comment {} 60 ; comment {This is the code that implements the AnalogIn4 RoboBrick . Basically} 61 ; comment {it just waits for commands that come in at 2400 baud and responds} 62 ; comment {to them . See} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / robobricks / analogin4 / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment ############################################################################# 69 ; processor pic12ce674 cp = off pwrte = off wdte = off mclre = off fosc = intrc_no_clock 70 ; 16244=0x3f74 8199=0x2007 71 __config 16244 72 2007 configuration___address equ 8199 73 ; comment {define processor constants} 74 ; constant clock_rate 4000000 75 3d0900 clock_rate equ 4000000 76 ; constant clocks_per_instruction 4 77 0004 clocks_per_instruction equ 4 78 ; constant instruction_rate clock_rate / clocks_per_instruction 79 f4240 instruction_rate equ 1000000 80 ; comment {define serial communication control constants} 81 ; constant baud_rate 2400 82 0960 baud_rate equ 2400 83 ; constant instructions_per_bit instruction_rate / baud_rate 84 01a0 instructions_per_bit equ 416 85 ; constant delays_per_bit 3 86 0003 delays_per_bit equ 3 87 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 88 008a instructions_per_delay equ 138 89 ; constant extra_instructions_per_bit 9 90 0009 extra_instructions_per_bit equ 9 91 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 92 0003 extra_instructions_per_delay equ 3 93 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 94 0087 delay_instructions equ 135 95 ; comment {Oscillator Mask :} 96 008f osccal equ 143 97 ; constant osccal_unit 0x10 98 0010 osccal_unit equ 16 99 ; comment {Analog to digital conversion result register :} 100 001e addres equ 30 101 ; comment {Analog to digital conversion register 0 :} 102 001f addcon0 equ 31 103 ; bind adon addcon0 @ 0 104 001f adon equ addcon0+0 105 001f adon__byte equ addcon0+0 106 0000 adon__bit equ 0 107 ; bind go_done addcon0 @ 2 108 001f go_done equ addcon0+0 109 001f go_done__byte equ addcon0+0 110 0002 go_done__bit equ 2 111 ; bind chs0 addcon0 @ 3 112 001f chs0 equ addcon0+0 113 001f chs0__byte equ addcon0+0 114 0003 chs0__bit equ 3 115 ; bind chs1 addcon0 @ 4 116 001f chs1 equ addcon0+0 117 001f chs1__byte equ addcon0+0 118 0004 chs1__bit equ 4 119 ; bind adcs0 addcon0 @ 6 120 001f adcs0 equ addcon0+0 121 001f adcs0__byte equ addcon0+0 122 0006 adcs0__bit equ 6 123 ; bind adcs1 addcon0 @ 7 124 001f adcs1 equ addcon0+0 125 001f adcs1__byte equ addcon0+0 126 0007 adcs1__bit equ 7 127 ; comment {Interrupt Control Register :} 128 000b intcon equ 11 129 ; bind gpif intcon @ 0 130 000b gpif equ intcon+0 131 000b gpif__byte equ intcon+0 132 0000 gpif__bit equ 0 133 ; bind intf intcon @ 1 134 000b intf equ intcon+0 135 000b intf__byte equ intcon+0 136 0001 intf__bit equ 1 137 ; bind toif intcon @ 2 138 000b toif equ intcon+0 139 000b toif__byte equ intcon+0 140 0002 toif__bit equ 2 141 ; bind gpie intcon @ 3 142 000b gpie equ intcon+0 143 000b gpie__byte equ intcon+0 144 0003 gpie__bit equ 3 145 ; bind inte intcon @ 4 146 000b inte equ intcon+0 147 000b inte__byte equ intcon+0 148 0004 inte__bit equ 4 149 ; bind toie intcon @ 5 150 000b toie equ intcon+0 151 000b toie__byte equ intcon+0 152 0005 toie__bit equ 5 153 ; bind peie intcon @ 6 154 000b peie equ intcon+0 155 000b peie__byte equ intcon+0 156 0006 peie__bit equ 6 157 ; bind gie intcon @ 7 158 000b gie equ intcon+0 159 000b gie__byte equ intcon+0 160 0007 gie__bit equ 7 161 000c pir1 equ 12 162 ; bind adif pir1 @ 6 163 000c adif equ pir1+0 164 000c adif__byte equ pir1+0 165 0006 adif__bit equ 6 166 008c pie1 equ 140 167 ; bind adie pie1 @ 6 168 008c adie equ pie1+0 169 008c adie__byte equ pie1+0 170 0006 adie__bit equ 6 171 ; comment {Analog to digital conversion register 1 :} 172 009f addcon1 equ 159 173 ; bind pcfg0 addcon1 @ 0 174 009f pcfg0 equ addcon1+0 175 009f pcfg0__byte equ addcon1+0 176 0000 pcfg0__bit equ 0 177 ; bind pcfg1 addcon1 @ 1 178 009f pcfg1 equ addcon1+0 179 009f pcfg1__byte equ addcon1+0 180 0001 pcfg1__bit equ 1 181 ; bind pcfg2 addcon1 @ 2 182 009f pcfg2 equ addcon1+0 183 009f pcfg2__byte equ addcon1+0 184 0002 pcfg2__bit equ 2 185 ; constant ain_bit0 0 186 0000 ain_bit0 equ 0 187 ; constant ain_bit1 1 188 0001 ain_bit1 equ 1 189 ; constant ain_bit2 2 190 0002 ain_bit2 equ 2 191 ; constant serial_in_bit 3 192 0003 serial_in_bit equ 3 193 ; constant ain_bit3 4 194 0004 ain_bit3 equ 4 195 ; constant serial_out_bit 5 196 0005 serial_out_bit equ 5 197 ; constant ain_mask0 {{ 1 << ain_bit0 }} 198 0001 ain_mask0 equ 1 199 ; constant ain_mask1 {{ 1 << ain_bit1 }} 200 0002 ain_mask1 equ 2 201 ; constant ain_mask2 {{ 1 << ain_bit2 }} 202 0004 ain_mask2 equ 4 203 ; constant ain_mask3 {{ 1 << ain_bit3 }} 204 0010 ain_mask3 equ 16 205 ; constant serial_in_mask {{ 1 << serial_in_bit }} 206 0008 serial_in_mask equ 8 207 ; constant serial_out_mask {{ 1 << serial_out_bit }} 208 0020 serial_out_mask equ 32 209 ; constant io_mask 0xf 210 000f io_mask equ 15 211 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} 212 0017 ain_mask equ 23 213 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} 214 0028 serial_mask equ 40 215 ; comment {define port bit assignments} 216 0005 porta equ 5 217 0005 ain0__byte equ 5 218 0000 ain0__bit equ 0 219 0005 ain1__byte equ 5 220 0001 ain1__bit equ 1 221 0005 ain2__byte equ 5 222 0002 ain2__bit equ 2 223 0005 ain3__byte equ 5 224 0004 ain3__bit equ 4 225 0005 serial_in__byte equ 5 226 0003 serial_in__bit equ 3 227 0005 serial_out__byte equ 5 228 0005 serial_out__bit equ 5 229 ; constant analogs_size 4 230 0004 analogs_size equ 4 231 ; string_constants Start 232 string___fetch: 233 010 0082 movwf pcl___register 234 ; id = 1 , 0 , 25 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'Light4A' , 15 , 0s'Gramlich&Benson' 235 0000 id___string equ 0 236 id: 237 011 0782 addwf pcl___register,f 238 ; Length = 48 239 012 3430 retlw 48 240 ; 1 241 013 3401 retlw 1 242 ; 0 243 014 3400 retlw 0 244 ; 25 245 015 3419 retlw 25 246 ; 0 247 016 3400 retlw 0 248 ; 0 249 017 3400 retlw 0 250 ; 0 251 018 3400 retlw 0 252 ; 0 253 019 3400 retlw 0 254 ; 0 255 01a 3400 retlw 0 256 ; 0r'16' 257 01b 3480 retlw 128 ; random number 258 01c 34a5 retlw 165 ; random number 259 01d 34c6 retlw 198 ; random number 260 01e 34eb retlw 235 ; random number 261 01f 349e retlw 158 ; random number 262 020 344e retlw 78 ; random number 263 021 344b retlw 75 ; random number 264 022 345e retlw 94 ; random number 265 023 3489 retlw 137 ; random number 266 024 34f9 retlw 249 ; random number 267 025 342c retlw 44 ; random number 268 026 34f7 retlw 247 ; random number 269 027 34cf retlw 207 ; random number 270 028 34fd retlw 253 ; random number 271 029 34f0 retlw 240 ; random number 272 02a 340a retlw 10 ; random number 273 ; 7 274 02b 3407 retlw 7 275 ; `Light4A' 276 02c 344c retlw 76 277 02d 3469 retlw 105 278 02e 3467 retlw 103 279 02f 3468 retlw 104 280 030 3474 retlw 116 281 031 3434 retlw 52 282 032 3441 retlw 65 283 ; 15 284 033 340f retlw 15 285 ; `Gramlich&Benson' 286 034 3447 retlw 71 287 035 3472 retlw 114 288 036 3461 retlw 97 289 037 346d retlw 109 290 038 346c retlw 108 291 039 3469 retlw 105 292 03a 3463 retlw 99 293 03b 3468 retlw 104 294 03c 3426 retlw 38 295 03d 3442 retlw 66 296 03e 3465 retlw 101 297 03f 346e retlw 110 298 040 3473 retlw 115 299 041 346f retlw 111 300 042 346e retlw 110 301 ; string__constants End 302 ; bank 0 303 ; Default register bank is now 0 304 0020 analogs equ global__variables__bank0+0 305 0024 thresholds_low equ global__variables__bank0+4 306 0028 thresholds_high equ global__variables__bank0+8 307 002c inputs equ global__variables__bank0+12 308 002d complement equ global__variables__bank0+13 309 002e glitch equ global__variables__bank0+14 310 002f id_index equ global__variables__bank0+15 311 ; comment {Interrupt masks :} 312 0049 interrupt_enable equ global__bit__variables__bank0+0 313 0049 interrupt_enable__byte equ global__bit__variables__bank0+0 314 0000 interrupt_enable__bit equ 0 315 0049 interrupt_pending equ global__bit__variables__bank0+0 316 0049 interrupt_pending__byte equ global__bit__variables__bank0+0 317 0001 interrupt_pending__bit equ 1 318 0049 receiving equ global__bit__variables__bank0+0 319 0049 receiving__byte equ global__bit__variables__bank0+0 320 0002 receiving__bit equ 2 321 0030 falling equ global__variables__bank0+16 322 0031 high equ global__variables__bank0+17 323 0032 low equ global__variables__bank0+18 324 0033 raising equ global__variables__bank0+19 325 326 ; procedure main start 327 main: 328 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 329 0034 main__variables__base equ global__variables__bank0+20 330 0034 main__bytes__base equ main__variables__base+0 331 0038 main__bits__base equ main__variables__base+4 332 0005 main__total__bytes equ 5 333 0037 main__274byte0 equ main__bytes__base+3 334 0037 main__212byte0 equ main__bytes__base+3 335 0037 main__153byte0 equ main__bytes__base+3 336 0037 main__267byte0 equ main__bytes__base+3 337 0037 main__227byte0 equ main__bytes__base+3 338 0037 main__223byte0 equ main__bytes__base+3 339 0037 main__156byte0 equ main__bytes__base+3 340 ; arguments_none 341 0034 main__bit equ main__bytes__base+0 342 0035 main__command equ main__bytes__base+1 343 0036 main__temporary equ main__bytes__base+2 344 ; Initialize the A / D module : 345 ; addcon1 := 0 346 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 347 043 1683 bsf rp0___byte,rp0___bit 348 ; Register bank is now 1 349 044 019f clrf addcon1 350 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : 351 ; addcon0 := 0x41 352 045 3041 movlw 65 353 ; Switch from register bank 1 to register bank 0 (which contains addcon0) 354 046 1283 bcf rp0___byte,rp0___bit 355 ; Register bank is now 0 356 047 009f movwf addcon0 357 ; adif := 0 358 048 130c bcf adif__byte,adif__bit 359 ; adie := 0 360 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) 361 049 1683 bsf rp0___byte,rp0___bit 362 ; Register bank is now 1 363 04a 130c bcf adie__byte,adie__bit 364 ; gie := 0 365 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) 366 04b 1283 bcf rp0___byte,rp0___bit 367 ; Register bank is now 0 368 04c 138b bcf gie__byte,gie__bit 369 ; call reset {{ }} 370 04d 2233 call reset 371 ; Set the direction : 372 ; loop_forever ... start 373 main__148loop__forever: 374 ; Wait for a command : 375 ; command := get_byte {{ }} 376 04e 21ec call get_byte 377 04f 0842 movf get_byte__0return__byte,w 378 050 00b5 movwf main__command 379 ; Dispatch on command : 380 ; switch { command >> 6 } 381 051 3000 movlw HIGH switch__153block_start 382 052 008a movwf pclath___register 383 053 0e35 swapf main__command,w 384 054 00b7 movwf main__153byte0 385 055 0cb7 rrf main__153byte0,f 386 056 0c37 rrf main__153byte0,w 387 057 3903 andlw 3 388 ; case 0 389 ; case 1 390 ; case 2 391 ; case 3 392 switch__153block_start: 393 058 0782 addwf pcl___register,f 394 059 285d goto switch__153block154 395 05a 28e2 goto switch__153block240 396 05b 28fa goto switch__153block262 397 05c 28fb goto switch__153block265 398 switch__153block_end: 399 ; switch_check 153 switch__153block_start switch__153block_end 400 switch__153block154: 401 ; Command = 00 xx xxxx : 402 ; switch { command >> 3 } 403 05d 3000 movlw HIGH switch__156block_start 404 05e 008a movwf pclath___register 405 05f 0c35 rrf main__command,w 406 060 00b7 movwf main__156byte0 407 061 0cb7 rrf main__156byte0,f 408 062 0c37 rrf main__156byte0,w 409 063 391f andlw 31 410 ; case 0 411 ; case 1 412 ; case 2 3 413 ; case 4 5 414 switch__156block_start: 415 064 0782 addwf pcl___register,f 416 065 286d goto switch__156block157 417 066 288d goto switch__156block181 418 067 28af goto switch__156block209 419 068 28af goto switch__156block209 420 069 28dd goto switch__156block231 421 06a 28dd goto switch__156block231 422 06b 28e1 goto switch__156default235 423 06c 28e1 goto switch__156default235 424 switch__156block_end: 425 ; switch_check 156 switch__156block_start switch__156block_end 426 switch__156block157: 427 ; Command = 0000 0 xxx : 428 ; switch { command & 7 } 429 06d 3000 movlw HIGH switch__159block_start 430 06e 008a movwf pclath___register 431 06f 3007 movlw 7 432 070 0535 andwf main__command,w 433 ; case 0 1 2 3 434 ; case 4 435 ; case 5 436 ; case 6 437 switch__159block_start: 438 071 0782 addwf pcl___register,f 439 072 287a goto switch__159block160 440 073 287a goto switch__159block160 441 074 287a goto switch__159block160 442 075 287a goto switch__159block160 443 076 2881 goto switch__159block164 444 077 2886 goto switch__159block168 445 078 288a goto switch__159block172 446 079 288c goto switch__159default176 447 switch__159block_end: 448 ; switch_check 159 switch__159block_start switch__159block_end 449 switch__159block160: 450 ; Read Pin < Command = 0000 00 bb > : 451 ; call send_byte {{ analogs ~~ {{ command }} }} 452 07a 3020 movlw LOW analogs 453 07b 0735 addwf main__command,w 454 07c 0084 movwf fsr___register 455 07d 0800 movf indf___register,w 456 07e 00c5 movwf send_byte__char 457 07f 220d call send_byte 458 080 288c goto switch__159end 459 switch__159block164: 460 ; Read Binary Values < Command = 0000 0100 > : 461 ; call send_byte {{ inputs ^ complement }} 462 081 082c movf inputs,w 463 082 062d xorwf complement,w 464 083 00c5 movwf send_byte__char 465 084 220d call send_byte 466 085 288c goto switch__159end 467 switch__159block168: 468 ; Read Raw Binary < Command = 0000 0101 > : 469 ; call send_byte {{ inputs }} 470 086 082c movf inputs,w 471 087 00c5 movwf send_byte__char 472 088 220d call send_byte 473 089 288c goto switch__159end 474 switch__159block172: 475 ; Reset < Command = 0000 0110 > : 476 ; call reset {{ }} 477 08a 2233 call reset 478 08b 288c goto switch__159end 479 switch__159default176: 480 ; Undefined command : 481 switch__159end: 482 08c 28e1 goto switch__156end 483 switch__156block181: 484 ; Command = 0000 1 xxx : 485 ; switch { command & 7 } 486 08d 3000 movlw HIGH switch__183block_start 487 08e 008a movwf pclath___register 488 08f 3007 movlw 7 489 090 0535 andwf main__command,w 490 ; case 0 491 ; case 1 492 ; case 2 493 ; case 3 494 ; case 4 495 switch__183block_start: 496 091 0782 addwf pcl___register,f 497 092 289a goto switch__183block184 498 093 289e goto switch__183block188 499 094 28a2 goto switch__183block192 500 095 28a6 goto switch__183block196 501 096 28aa goto switch__183block200 502 097 28ae goto switch__183default204 503 098 28ae goto switch__183default204 504 099 28ae goto switch__183default204 505 switch__183block_end: 506 ; switch_check 183 switch__183block_start switch__183block_end 507 switch__183block184: 508 ; Read Complement Mask < Command = 0000 1000 > : 509 ; call send_byte {{ complement }} 510 09a 082d movf complement,w 511 09b 00c5 movwf send_byte__char 512 09c 220d call send_byte 513 09d 28ae goto switch__183end 514 switch__183block188: 515 ; Read High Mask < Command = 0000 1001 > : 516 ; call send_byte {{ high }} 517 09e 0831 movf high,w 518 09f 00c5 movwf send_byte__char 519 0a0 220d call send_byte 520 0a1 28ae goto switch__183end 521 switch__183block192: 522 ; Read Low Mask < Command = 0000 1010 > : 523 ; call send_byte {{ low }} 524 0a2 0832 movf low,w 525 0a3 00c5 movwf send_byte__char 526 0a4 220d call send_byte 527 0a5 28ae goto switch__183end 528 switch__183block196: 529 ; Read Raising Mask < Command = 0000 1011 > : 530 ; call send_byte {{ raising }} 531 0a6 0833 movf raising,w 532 0a7 00c5 movwf send_byte__char 533 0a8 220d call send_byte 534 0a9 28ae goto switch__183end 535 switch__183block200: 536 ; Read Falling Mask < Command = 0000 1100 > : 537 ; call send_byte {{ falling }} 538 0aa 0830 movf falling,w 539 0ab 00c5 movwf send_byte__char 540 0ac 220d call send_byte 541 0ad 28ae goto switch__183end 542 switch__183default204: 543 ; Undefined command : 544 switch__183end: 545 0ae 28e1 goto switch__156end 546 switch__156block209: 547 ; Command = 0001 xxxx : 548 ; bit := command & 3 549 0af 3003 movlw 3 550 0b0 0535 andwf main__command,w 551 0b1 00b4 movwf main__bit 552 ; switch { {{ command >> 2 }} & 3 } 553 0b2 3000 movlw HIGH switch__212block_start 554 0b3 008a movwf pclath___register 555 0b4 0c35 rrf main__command,w 556 0b5 00b7 movwf main__212byte0 557 0b6 0c37 rrf main__212byte0,w 558 0b7 3903 andlw 3 559 ; case 0 560 ; case 1 561 ; case 2 562 ; case 3 563 switch__212block_start: 564 0b8 0782 addwf pcl___register,f 565 0b9 28bd goto switch__212block213 566 0ba 28c4 goto switch__212block217 567 0bb 28cb goto switch__212block221 568 0bc 28d4 goto switch__212block225 569 switch__212block_end: 570 ; switch_check 212 switch__212block_start switch__212block_end 571 switch__212block213: 572 ; Read High Threshold < Command = 0001 00 bb > : 573 ; call send_byte {{ thresholds_high ~~ {{ bit }} }} 574 0bd 3028 movlw LOW thresholds_high 575 0be 0734 addwf main__bit,w 576 0bf 0084 movwf fsr___register 577 0c0 0800 movf indf___register,w 578 0c1 00c5 movwf send_byte__char 579 0c2 220d call send_byte 580 0c3 28dc goto switch__212end 581 switch__212block217: 582 ; Read Low Threshold < Command = 0001 01 bb > : 583 ; call send_byte {{ thresholds_low ~~ {{ bit }} }} 584 0c4 3024 movlw LOW thresholds_low 585 0c5 0734 addwf main__bit,w 586 0c6 0084 movwf fsr___register 587 0c7 0800 movf indf___register,w 588 0c8 00c5 movwf send_byte__char 589 0c9 220d call send_byte 590 0ca 28dc goto switch__212end 591 switch__212block221: 592 ; Set High Threshold < Command = 0001 10 bb > : 593 ; thresholds_high ~~ {{ bit }} := get_byte {{ }} 594 0cb 21ec call get_byte 595 0cc 0842 movf get_byte__0return__byte,w 596 0cd 00b7 movwf main__223byte0 597 0ce 3028 movlw LOW thresholds_high 598 0cf 0734 addwf main__bit,w 599 0d0 0084 movwf fsr___register 600 0d1 0837 movf main__223byte0,w 601 0d2 0080 movwf indf___register 602 0d3 28dc goto switch__212end 603 switch__212block225: 604 ; Set Low Threshold < Command = 0001 11 bb > : 605 ; thresholds_low ~~ {{ bit }} := get_byte {{ }} 606 0d4 21ec call get_byte 607 0d5 0842 movf get_byte__0return__byte,w 608 0d6 00b7 movwf main__227byte0 609 0d7 3024 movlw LOW thresholds_low 610 0d8 0734 addwf main__bit,w 611 0d9 0084 movwf fsr___register 612 0da 0837 movf main__227byte0,w 613 0db 0080 movwf indf___register 614 switch__212end: 615 0dc 28e1 goto switch__156end 616 switch__156block231: 617 ; Set Complement Mask < Command = 0010 cccc > : 618 ; complement := command & io_mask 619 0dd 300f movlw 15 620 0de 0535 andwf main__command,w 621 0df 00ad movwf complement 622 0e0 28e1 goto switch__156end 623 switch__156default235: 624 ; Do nothing : 625 switch__156end: 626 0e1 296d goto switch__153end 627 switch__153block240: 628 ; Command = 01 xx xxxx : 629 ; temporary := command & io_mask 630 0e2 300f movlw 15 631 0e3 0535 andwf main__command,w 632 0e4 00b6 movwf main__temporary 633 ; switch { {{ command >> 4 }} & 3 } 634 0e5 3000 movlw HIGH switch__243block_start 635 0e6 008a movwf pclath___register 636 0e7 0e35 swapf main__command,w 637 0e8 3903 andlw 3 638 ; case 0 639 ; case 1 640 ; case 2 641 ; case 3 642 switch__243block_start: 643 0e9 0782 addwf pcl___register,f 644 0ea 28ee goto switch__243block244 645 0eb 28f1 goto switch__243block248 646 0ec 28f4 goto switch__243block252 647 0ed 28f7 goto switch__243block256 648 switch__243block_end: 649 ; switch_check 243 switch__243block_start switch__243block_end 650 switch__243block244: 651 ; Set High Mask < Command = 0100 hhhh > : 652 ; high := temporary 653 0ee 0836 movf main__temporary,w 654 0ef 00b1 movwf high 655 0f0 28f9 goto switch__243end 656 switch__243block248: 657 ; Set Low Mask < Command = 0101 llll > : 658 ; low := temporary 659 0f1 0836 movf main__temporary,w 660 0f2 00b2 movwf low 661 0f3 28f9 goto switch__243end 662 switch__243block252: 663 ; Set Raising Mask < Command = 0110 rrrr > : 664 ; raising := temporary 665 0f4 0836 movf main__temporary,w 666 0f5 00b3 movwf raising 667 0f6 28f9 goto switch__243end 668 switch__243block256: 669 ; Set Falling Mask < Command = 0111 ffff > : 670 ; falling := temporary 671 0f7 0836 movf main__temporary,w 672 0f8 00b0 movwf falling 673 switch__243end: 674 0f9 296d goto switch__153end 675 switch__153block262: 676 ; Do nothing < Command = 10 xx xxxx > : 677 0fa 296d goto switch__153end 678 switch__153block265: 679 ; Command = 11 xx xxxx : 680 ; switch { {{ command >> 3 }} & 7 } 681 0fb 3001 movlw HIGH switch__267block_start 682 0fc 008a movwf pclath___register 683 0fd 0c35 rrf main__command,w 684 0fe 00b7 movwf main__267byte0 685 0ff 0cb7 rrf main__267byte0,f 686 100 0c37 rrf main__267byte0,w 687 101 3907 andlw 7 688 ; case 0 1 2 3 4 689 ; case 5 690 ; case 6 691 ; case 7 692 switch__267block_start: 693 102 0782 addwf pcl___register,f 694 103 290b goto switch__267block268 695 104 290b goto switch__267block268 696 105 290b goto switch__267block268 697 106 290b goto switch__267block268 698 107 290b goto switch__267block268 699 108 290c goto switch__267block272 700 109 291c goto switch__267block286 701 10a 2938 goto switch__267block304 702 switch__267block_end: 703 ; switch_check 267 switch__267block_start switch__267block_end 704 switch__267block268: 705 ; Command = 1100 xxxx or 1110 0 xxx : 706 ; Do nothing : 707 10b 296d goto switch__267end 708 switch__267block272: 709 ; Read Interrupt Bits < Command = 1110 1111 > : 710 ; if { {{ command & 7 }} = 7 } start 711 10c 3007 movlw 7 712 10d 0535 andwf main__command,w 713 10e 00b7 movwf main__274byte0 714 10f 3007 movlw 7 715 110 0237 subwf main__274byte0,w 716 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 717 111 1d03 btfss z___byte,z___bit 718 112 291b goto label274__1end 719 ; if { {{ command & 7 }} = 7 } body start 720 ; Return Interrupt Bits : 721 ; temporary := 0 722 113 01b6 clrf main__temporary 723 ; if { interrupt_enable } start 724 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 725 114 1849 btfsc interrupt_enable__byte,interrupt_enable__bit 726 ; if { interrupt_enable } body start 727 ; temporary @ 1 := 1 728 ; Select temporary @ 1 729 0036 main__temporary__278select0 equ main__temporary+0 730 0036 main__temporary__278select0__byte equ main__temporary+0 731 0001 main__temporary__278select0__bit equ 1 732 115 14b6 bsf main__temporary__278select0__byte,main__temporary__278select0__bit 733 ; if { interrupt_enable } body end 734 ; if exp=`interrupt_enable' false skip delay=2 735 ; Other expression=`{ interrupt_enable }' delay=2 736 ; if { interrupt_enable } end 737 ; if { interrupt_pending } start 738 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 739 116 18c9 btfsc interrupt_pending__byte,interrupt_pending__bit 740 ; if { interrupt_pending } body start 741 ; temporary @ 0 := 1 742 ; Select temporary @ 0 743 0036 main__temporary__281select0 equ main__temporary+0 744 0036 main__temporary__281select0__byte equ main__temporary+0 745 0000 main__temporary__281select0__bit equ 0 746 117 1436 bsf main__temporary__281select0__byte,main__temporary__281select0__bit 747 ; if { interrupt_pending } body end 748 ; if exp=`interrupt_pending' false skip delay=2 749 ; Other expression=`{ interrupt_pending }' delay=2 750 ; if { interrupt_pending } end 751 ; call send_byte {{ temporary }} 752 118 0836 movf main__temporary,w 753 119 00c5 movwf send_byte__char 754 11a 220d call send_byte 755 ; if { {{ command & 7 }} = 7 } body end 756 label274__1end: 757 ; if exp=` {{ command & 7 }} = 7 ' empty false 758 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 759 ; if { {{ command & 7 }} = 7 } end 760 11b 296d goto switch__267end 761 switch__267block286: 762 ; Shared Interrupt commands < Command = 1111 0 xxx > : 763 ; switch { command & 7 } 764 11c 3001 movlw HIGH switch__288block_start 765 11d 008a movwf pclath___register 766 11e 3007 movlw 7 767 11f 0535 andwf main__command,w 768 ; case 0 1 2 3 769 ; case 4 5 770 ; case 6 7 771 switch__288block_start: 772 120 0782 addwf pcl___register,f 773 121 2929 goto switch__288block289 774 122 2929 goto switch__288block289 775 123 2929 goto switch__288block289 776 124 2929 goto switch__288block289 777 125 2930 goto switch__288block294 778 126 2930 goto switch__288block294 779 127 2934 goto switch__288block298 780 128 2934 goto switch__288block298 781 switch__288block_end: 782 ; switch_check 288 switch__288block_start switch__288block_end 783 switch__288block289: 784 ; Set interrupt bits < Command = 1111 10 ep > : 785 ; interrupt_enable := command @ 1 786 ; Alias variable for select command @ 1 787 0035 main__command__291select0 equ main__command+0 788 0035 main__command__291select0__byte equ main__command+0 789 0001 main__command__291select0__bit equ 1 790 129 1049 bcf interrupt_enable__byte,interrupt_enable__bit 791 12a 18b5 btfsc main__command__291select0__byte,main__command__291select0__bit 792 12b 1449 bsf interrupt_enable__byte,interrupt_enable__bit 793 ; interrupt_pending := command @ 0 794 ; Alias variable for select command @ 0 795 0035 main__command__292select0 equ main__command+0 796 0035 main__command__292select0__byte equ main__command+0 797 0000 main__command__292select0__bit equ 0 798 12c 10c9 bcf interrupt_pending__byte,interrupt_pending__bit 799 12d 1835 btfsc main__command__292select0__byte,main__command__292select0__bit 800 12e 14c9 bsf interrupt_pending__byte,interrupt_pending__bit 801 12f 2937 goto switch__288end 802 switch__288block294: 803 ; Set Interrupt Pending < Command = 1111 110 p > : 804 ; interrupt_pending := command @ 0 805 ; Alias variable for select command @ 0 806 0035 main__command__296select0 equ main__command+0 807 0035 main__command__296select0__byte equ main__command+0 808 0000 main__command__296select0__bit equ 0 809 130 10c9 bcf interrupt_pending__byte,interrupt_pending__bit 810 131 1835 btfsc main__command__296select0__byte,main__command__296select0__bit 811 132 14c9 bsf interrupt_pending__byte,interrupt_pending__bit 812 133 2937 goto switch__288end 813 switch__288block298: 814 ; Set Interrupt Enable < Command = 1110 111 e > : 815 ; interrupt_enable := command @ 0 816 ; Alias variable for select command @ 0 817 0035 main__command__300select0 equ main__command+0 818 0035 main__command__300select0__byte equ main__command+0 819 0000 main__command__300select0__bit equ 0 820 134 1049 bcf interrupt_enable__byte,interrupt_enable__bit 821 135 1835 btfsc main__command__300select0__byte,main__command__300select0__bit 822 136 1449 bsf interrupt_enable__byte,interrupt_enable__bit 823 switch__288end: 824 137 296d goto switch__267end 825 switch__267block304: 826 ; Shared commands < Command = 1111 1 xxx > : 827 ; switch { command & 7 } 828 138 3001 movlw HIGH switch__306block_start 829 139 008a movwf pclath___register 830 13a 3007 movlw 7 831 13b 0535 andwf main__command,w 832 ; case 0 833 ; case 1 834 ; case 2 835 ; case 3 836 ; case 4 837 ; case 5 838 ; case 6 839 ; case 7 840 switch__306block_start: 841 13c 0782 addwf pcl___register,f 842 13d 2945 goto switch__306block307 843 13e 294a goto switch__306block311 844 13f 294f goto switch__306block315 845 140 2955 goto switch__306block319 846 141 2958 goto switch__306block323 847 142 2963 goto switch__306block331 848 143 2965 goto switch__306block335 849 144 296a goto switch__306block340 850 switch__306block_end: 851 ; switch_check 306 switch__306block_start switch__306block_end 852 switch__306block307: 853 ; Clock Decrement < Command = 1111 1000 > : 854 ; osccal := osccal - osccal_unit 855 145 30f0 movlw 240 856 ; Switch from register bank 0 to register bank 1 (which contains osccal) 857 146 1683 bsf rp0___byte,rp0___bit 858 ; Register bank is now 1 859 147 078f addwf osccal,f 860 ; Switch from register bank 1 to register bank 0 861 148 1283 bcf rp0___byte,rp0___bit 862 ; Register bank is now 0 863 149 296d goto switch__306end 864 switch__306block311: 865 ; Clock Increment < Command = 1111 1001 > : 866 ; osccal := osccal + osccal_unit 867 14a 3010 movlw 16 868 ; Switch from register bank 0 to register bank 1 (which contains osccal) 869 14b 1683 bsf rp0___byte,rp0___bit 870 ; Register bank is now 1 871 14c 078f addwf osccal,f 872 ; Switch from register bank 1 to register bank 0 873 14d 1283 bcf rp0___byte,rp0___bit 874 ; Register bank is now 0 875 14e 296d goto switch__306end 876 switch__306block315: 877 ; Clock Read < Command = 1111 1010 > : 878 ; call send_byte {{ osccal }} 879 ; Switch from register bank 0 to register bank 1 (which contains osccal) 880 14f 1683 bsf rp0___byte,rp0___bit 881 ; Register bank is now 1 882 150 080f movf osccal,w 883 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 884 151 1283 bcf rp0___byte,rp0___bit 885 ; Register bank is now 0 886 152 00c5 movwf send_byte__char 887 153 220d call send_byte 888 154 296d goto switch__306end 889 switch__306block319: 890 ; Clock Pulse < Command = 1111 1011 > : 891 ; call send_byte {{ 0 }} 892 155 01c5 clrf send_byte__char 893 156 220d call send_byte 894 157 296d goto switch__306end 895 switch__306block323: 896 ; ID Next < Command = 1111 1100 > : 897 ; call send_byte {{ id ~~ {{ id_index }} }} 898 158 0a2f incf id_index,w 899 159 018a clrf pclath___register 900 15a 2011 call id 901 15b 00c5 movwf send_byte__char 902 15c 220d call send_byte 903 ; id_index := id_index + 1 904 15d 0aaf incf id_index,f 905 ; if { id_index >= id . size } start 906 15e 3030 movlw 48 907 15f 022f subwf id_index,w 908 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 909 160 1803 btfsc c___byte,c___bit 910 ; if { id_index >= id . size } body start 911 ; id_index := 0 912 161 01af clrf id_index 913 ; if { id_index >= id . size } body end 914 ; if exp=` id_index >= id . size ' false skip delay=4 915 ; Other expression=`{ id_index >= id . size }' delay=4 916 ; if { id_index >= id . size } end 917 162 296d goto switch__306end 918 switch__306block331: 919 ; ID Reset < Command = 1111 1101 > : 920 ; id_index := 0 921 163 01af clrf id_index 922 164 296d goto switch__306end 923 switch__306block335: 924 ; Glitch Read < Command = 1111 1110 > : 925 ; call send_byte {{ glitch }} 926 165 082e movf glitch,w 927 166 00c5 movwf send_byte__char 928 167 220d call send_byte 929 ; glitch := 0 930 168 01ae clrf glitch 931 169 296d goto switch__306end 932 switch__306block340: 933 ; Glitch < Command = 1111 1111 > : 934 ; if { glitch != 0xff } start 935 16a 0a2e incf glitch,w 936 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 937 16b 1d03 btfss z___byte,z___bit 938 ; if { glitch != 0xff } body start 939 ; glitch := glitch + 1 940 16c 0aae incf glitch,f 941 ; if { glitch != 0xff } body end 942 ; if exp=` glitch != 0xff ' false skip delay=3 943 ; Other expression=`{ glitch != 0xff }' delay=3 944 ; if { glitch != 0xff } end 945 switch__306end: 946 switch__267end: 947 switch__153end: 948 16d 284e goto main__148loop__forever 949 ; loop_forever ... end 950 ; procedure main end 951 952 ; procedure delay start 953 ; optimize 0 954 delay: 955 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 956 0039 delay__variables__base equ global__variables__bank0+25 957 0039 delay__bytes__base equ delay__variables__base+0 958 0042 delay__bits__base equ delay__variables__base+9 959 0009 delay__total__bytes equ 9 960 0041 delay__376byte3 equ delay__bytes__base+8 961 0041 delay__416byte1 equ delay__bytes__base+8 962 0041 delay__354byte1 equ delay__bytes__base+8 963 0041 delay__418byte0 equ delay__bytes__base+8 964 0041 delay__387byte0 equ delay__bytes__base+8 965 0041 delay__378byte0 equ delay__bytes__base+8 966 ; arguments_none 967 ; uniform_delay delay_instructions 968 ; Uniform delay remaining = 131 Accumulated Delay = 0 969 ; Uniform delay remaining = 131 Accumulated Delay = 0 970 ; This procedure will delay for one third of a bit time . 971 ; Uniform delay remaining = 131 Accumulated Delay = 0 972 ; Uniform delay remaining = 131 Accumulated Delay = 0 973 ; Uniform delay remaining = 131 Accumulated Delay = 0 974 0039 delay__channel equ delay__bytes__base+0 975 ; Uniform delay remaining = 131 Accumulated Delay = 0 976 003a delay__current equ delay__bytes__base+1 977 ; Uniform delay remaining = 131 Accumulated Delay = 0 978 003b delay__changed equ delay__bytes__base+2 979 ; Uniform delay remaining = 131 Accumulated Delay = 0 980 003c delay__previous equ delay__bytes__base+3 981 ; Uniform delay remaining = 131 Accumulated Delay = 0 982 003d delay__not_current equ delay__bytes__base+4 983 ; Uniform delay remaining = 131 Accumulated Delay = 0 984 003e delay__counter equ delay__bytes__base+5 985 ; Uniform delay remaining = 131 Accumulated Delay = 0 986 003f delay__mask equ delay__bytes__base+6 987 ; Uniform delay remaining = 131 Accumulated Delay = 0 988 0040 delay__result equ delay__bytes__base+7 989 ; Uniform delay remaining = 131 Accumulated Delay = 0 990 ; Uniform delay remaining = 131 Accumulated Delay = 0 991 ; Kick the dog : 992 ; Uniform delay remaining = 131 Accumulated Delay = 0 993 ; watch_dog_reset 994 16e 0064 clrwdt 995 ; Uniform delay remaining = 130 Accumulated Delay = 1 996 ; Uniform delay remaining = 130 Accumulated Delay = 1 997 ; channel := {{ counter >> 1 }} & 3 998 16f 1003 bcf c___byte,c___bit 999 170 0c3e rrf delay__counter,w 1000 171 3903 andlw 3 1001 172 00b9 movwf delay__channel 1002 ; Uniform delay remaining = 126 Accumulated Delay = 5 1003 ; counter := counter + 1 1004 173 0abe incf delay__counter,f 1005 ; Uniform delay remaining = 125 Accumulated Delay = 6 1006 ; if { counter @ 0 } start 1007 ; Alias variable for select counter @ 0 1008 003e delay__counter__376select0 equ delay__counter+0 1009 003e delay__counter__376select0__byte equ delay__counter+0 1010 0000 delay__counter__376select0__bit equ 0 1011 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=44 false_delay=104 true_size=48 false_size=57 1012 174 1c3e btfss delay__counter__376select0__byte,delay__counter__376select0__bit 1013 175 29ac goto label376__1false 1014 label376__1true: 1015 ; if { counter @ 0 } body start 1016 ; Uniform delay remaining = 125 Accumulated Delay = 0 1017 ; Set up and wait for acquistion : 1018 ; Uniform delay remaining = 125 Accumulated Delay = 0 1019 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 1020 176 0d39 rlf delay__channel,w 1021 177 00c1 movwf delay__378byte0 1022 178 0dc1 rlf delay__378byte0,f 1023 179 0d41 rlf delay__378byte0,w 1024 17a 39f8 andlw 248 1025 17b 3918 andlw 24 1026 17c 3841 iorlw 65 1027 17d 009f movwf addcon0 1028 ; Uniform delay remaining = 117 Accumulated Delay = 8 1029 ; Setup for interrupts : 1030 ; Uniform delay remaining = 117 Accumulated Delay = 8 1031 ; previous := current 1032 17e 083a movf delay__current,w 1033 17f 00bc movwf delay__previous 1034 ; Uniform delay remaining = 115 Accumulated Delay = 10 1035 ; Read the I / O port once : 1036 ; Uniform delay remaining = 115 Accumulated Delay = 10 1037 ; current := inputs ^ complement 1038 180 082c movf inputs,w 1039 181 062d xorwf complement,w 1040 182 00ba movwf delay__current 1041 ; Uniform delay remaining = 112 Accumulated Delay = 13 1042 ; not_current := current ^ 0xf 1043 183 300f movlw 15 1044 184 063a xorwf delay__current,w 1045 185 00bd movwf delay__not_current 1046 ; Uniform delay remaining = 109 Accumulated Delay = 16 1047 ; changed := current ^ previous 1048 186 083a movf delay__current,w 1049 187 063c xorwf delay__previous,w 1050 188 00bb movwf delay__changed 1051 ; Uniform delay remaining = 106 Accumulated Delay = 19 1052 ; Uniform delay remaining = 106 Accumulated Delay = 19 1053 ; See about triggering the interrupt_pending flag : 1054 ; Uniform delay remaining = 106 Accumulated Delay = 19 1055 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start 1056 189 0832 movf low,w 1057 18a 053d andwf delay__not_current,w 1058 18b 00c1 movwf delay__387byte0 1059 18c 0831 movf high,w 1060 18d 053a andwf delay__current,w 1061 18e 04c1 iorwf delay__387byte0,f 1062 18f 083b movf delay__changed,w 1063 190 053a andwf delay__current,w 1064 191 0533 andwf raising,w 1065 192 04c1 iorwf delay__387byte0,f 1066 193 083b movf delay__changed,w 1067 194 053d andwf delay__not_current,w 1068 195 0530 andwf falling,w 1069 196 0441 iorwf delay__387byte0,w 1070 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 1071 197 1d03 btfss z___byte,z___bit 1072 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start 1073 ; Uniform delay remaining = 106 Accumulated Delay = 0 1074 ; interrupt_pending := 1 1075 198 14c9 bsf interrupt_pending__byte,interrupt_pending__bit 1076 ; Uniform delay remaining = 105 Accumulated Delay = 1 1077 ; Uniform delay remaining = 105 Accumulated Delay = 1 1078 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end 1079 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 1080 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 1081 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end 1082 ; Uniform delay remaining = 90 Accumulated Delay = 35 1083 ; Uniform delay remaining = 90 Accumulated Delay = 35 1084 ; Send an interrupt if interrupts are enabled : 1085 ; Uniform delay remaining = 90 Accumulated Delay = 35 1086 ; if { interrupt_pending && interrupt_enable } start 1087 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1088 199 18c9 btfsc interrupt_pending__byte,interrupt_pending__bit 1089 19a 299e goto label392__2true 1090 label392__2false: 1091 ; Delay 2 cycles 1092 19b 0000 nop 1093 19c 0000 nop 1094 19d 29a6 goto and392__0false 1095 label392__2true: 1096 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1097 19e 1c49 btfss interrupt_enable__byte,interrupt_enable__bit 1098 19f 29a3 goto label392__1false 1099 label392__1true: 1100 and392__0true: 1101 ; if { interrupt_pending && interrupt_enable } body start 1102 ; Uniform delay remaining = 90 Accumulated Delay = 0 1103 ; Shove serial out to low : 1104 ; Uniform delay remaining = 90 Accumulated Delay = 0 1105 ; interrupt_enable := 0 1106 1a0 1049 bcf interrupt_enable__byte,interrupt_enable__bit 1107 ; Uniform delay remaining = 89 Accumulated Delay = 1 1108 ; serial_out := 0 1109 1a1 1285 bcf serial_out__byte,serial_out__bit 1110 ; Uniform delay remaining = 88 Accumulated Delay = 2 1111 ; Uniform delay remaining = 88 Accumulated Delay = 2 1112 ; if { interrupt_pending && interrupt_enable } body end 1113 1a2 29a6 goto label392__1end 1114 label392__1false: 1115 ; Delay 3 cycles 1116 1a3 0000 nop 1117 1a4 0000 nop 1118 1a5 0000 nop 1119 ; if exp=`interrupt_enable' total delay=6 1120 ; if exp=`interrupt_enable' generic 1121 label392__1end: 1122 ; Other expression=`interrupt_enable' delay=6 1123 ; if exp=`interrupt_pending' total delay=9 1124 ; if exp=`interrupt_pending' generic 1125 label392__2end: 1126 ; Other expression=`interrupt_pending' delay=9 1127 and392__0false: 1128 and392__0end: 1129 ; if { interrupt_pending && interrupt_enable } end 1130 ; Uniform delay remaining = 81 Accumulated Delay = 44 1131 ; Uniform delay remaining = 81 Accumulated Delay = 44 1132 ; if { counter @ 0 } body end 1133 ; Delay 59 cycles 1134 1a6 3013 movlw 19 1135 1a7 00c1 movwf delay__376byte3 1136 delay__376delay2: 1137 1a8 0bc1 decfsz delay__376byte3,f 1138 1a9 29a8 goto delay__376delay2 1139 1aa 0000 nop 1140 1ab 29e5 goto label376__1end 1141 label376__1false: 1142 ; else body start 1143 ; Uniform delay remaining = 125 Accumulated Delay = 0 1144 ; Start the conversion : 1145 ; Uniform delay remaining = 125 Accumulated Delay = 0 1146 ; go_done := 1 1147 1ac 151f bsf go_done__byte,go_done__bit 1148 ; Uniform delay remaining = 124 Accumulated Delay = 1 1149 ; mask := 0 1150 1ad 01bf clrf delay__mask 1151 ; Uniform delay remaining = 123 Accumulated Delay = 2 1152 ; if { channel @ 1 } start 1153 ; Alias variable for select channel @ 1 1154 0039 delay__channel__401select0 equ delay__channel+0 1155 0039 delay__channel__401select0__byte equ delay__channel+0 1156 0001 delay__channel__401select0__bit equ 1 1157 ; expression=`{ channel @ 1 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 1158 1ae 1cb9 btfss delay__channel__401select0__byte,delay__channel__401select0__bit 1159 1af 29b5 goto label401__1false 1160 label401__1true: 1161 ; if { channel @ 1 } body start 1162 ; Uniform delay remaining = 123 Accumulated Delay = 0 1163 ; if { channel @ 0 } start 1164 ; Alias variable for select channel @ 0 1165 0039 delay__channel__402select0 equ delay__channel+0 1166 0039 delay__channel__402select0__byte equ delay__channel+0 1167 0000 delay__channel__402select0__bit equ 0 1168 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1169 1b0 1839 btfsc delay__channel__402select0__byte,delay__channel__402select0__bit 1170 ; if { channel @ 0 } body start 1171 ; Uniform delay remaining = 123 Accumulated Delay = 0 1172 ; mask @ 3 := 1 1173 ; Select mask @ 3 1174 003f delay__mask__403select0 equ delay__mask+0 1175 003f delay__mask__403select0__byte equ delay__mask+0 1176 0003 delay__mask__403select0__bit equ 3 1177 1b1 15bf bsf delay__mask__403select0__byte,delay__mask__403select0__bit 1178 ; Uniform delay remaining = 122 Accumulated Delay = 1 1179 ; Uniform delay remaining = 122 Accumulated Delay = 1 1180 ; if { channel @ 0 } body end 1181 1b2 1c39 btfss delay__channel__402select0__byte,delay__channel__402select0__bit 1182 ; else body start 1183 ; Uniform delay remaining = 123 Accumulated Delay = 0 1184 ; mask @ 2 := 1 1185 ; Select mask @ 2 1186 003f delay__mask__405select0 equ delay__mask+0 1187 003f delay__mask__405select0__byte equ delay__mask+0 1188 0002 delay__mask__405select0__bit equ 2 1189 1b3 153f bsf delay__mask__405select0__byte,delay__mask__405select0__bit 1190 ; Uniform delay remaining = 122 Accumulated Delay = 1 1191 ; Uniform delay remaining = 122 Accumulated Delay = 1 1192 ; else body end 1193 ; if exp=` channel @ 0 ' single true and false skip delay=4 1194 ; Other expression=`{ channel @ 0 }' delay=4 1195 ; if { channel @ 0 } end 1196 ; Uniform delay remaining = 119 Accumulated Delay = 4 1197 ; Uniform delay remaining = 119 Accumulated Delay = 4 1198 ; if { channel @ 1 } body end 1199 1b4 29ba goto label401__1end 1200 label401__1false: 1201 ; else body start 1202 ; Uniform delay remaining = 123 Accumulated Delay = 0 1203 ; if { channel @ 0 } start 1204 ; Alias variable for select channel @ 0 1205 0039 delay__channel__408select0 equ delay__channel+0 1206 0039 delay__channel__408select0__byte equ delay__channel+0 1207 0000 delay__channel__408select0__bit equ 0 1208 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1209 1b5 1839 btfsc delay__channel__408select0__byte,delay__channel__408select0__bit 1210 ; if { channel @ 0 } body start 1211 ; Uniform delay remaining = 123 Accumulated Delay = 0 1212 ; mask @ 1 := 1 1213 ; Select mask @ 1 1214 003f delay__mask__409select0 equ delay__mask+0 1215 003f delay__mask__409select0__byte equ delay__mask+0 1216 0001 delay__mask__409select0__bit equ 1 1217 1b6 14bf bsf delay__mask__409select0__byte,delay__mask__409select0__bit 1218 ; Uniform delay remaining = 122 Accumulated Delay = 1 1219 ; Uniform delay remaining = 122 Accumulated Delay = 1 1220 ; if { channel @ 0 } body end 1221 1b7 1c39 btfss delay__channel__408select0__byte,delay__channel__408select0__bit 1222 ; else body start 1223 ; Uniform delay remaining = 123 Accumulated Delay = 0 1224 ; mask @ 0 := 1 1225 ; Select mask @ 0 1226 003f delay__mask__411select0 equ delay__mask+0 1227 003f delay__mask__411select0__byte equ delay__mask+0 1228 0000 delay__mask__411select0__bit equ 0 1229 1b8 143f bsf delay__mask__411select0__byte,delay__mask__411select0__bit 1230 ; Uniform delay remaining = 122 Accumulated Delay = 1 1231 ; Uniform delay remaining = 122 Accumulated Delay = 1 1232 ; else body end 1233 ; if exp=` channel @ 0 ' single true and false skip delay=4 1234 ; Other expression=`{ channel @ 0 }' delay=4 1235 ; if { channel @ 0 } end 1236 ; Uniform delay remaining = 119 Accumulated Delay = 4 1237 ; Uniform delay remaining = 119 Accumulated Delay = 4 1238 ; else body end 1239 ; Delay 1 cycles 1240 1b9 0000 nop 1241 ; if exp=` channel @ 1 ' total delay=8 1242 ; if exp=` channel @ 1 ' generic 1243 label401__1end: 1244 ; Other expression=`{ channel @ 1 }' delay=8 1245 ; if { channel @ 1 } end 1246 ; Uniform delay remaining = 115 Accumulated Delay = 10 1247 ; Delaying 60 uS is way longer than necessary for the conversion 1248 ; Uniform delay remaining = 115 Accumulated Delay = 10 1249 ; to complete . 1250 ; Uniform delay remaining = 115 Accumulated Delay = 10 1251 ; nop 60 1252 ; Delay 60 cycles 1253 1ba 3013 movlw 19 1254 1bb 00c1 movwf delay__416byte1 1255 delay__416delay0: 1256 1bc 0bc1 decfsz delay__416byte1,f 1257 1bd 29bc goto delay__416delay0 1258 1be 0000 nop 1259 1bf 0000 nop 1260 ; Uniform delay remaining = 55 Accumulated Delay = 70 1261 ; result := addres 1262 1c0 081e movf addres,w 1263 1c1 00c0 movwf delay__result 1264 ; Uniform delay remaining = 53 Accumulated Delay = 72 1265 ; analogs ~~ {{ channel }} := result 1266 1c2 0840 movf delay__result,w 1267 1c3 00c1 movwf delay__418byte0 1268 1c4 3020 movlw LOW analogs 1269 1c5 0739 addwf delay__channel,w 1270 1c6 0084 movwf fsr___register 1271 1c7 0841 movf delay__418byte0,w 1272 1c8 0080 movwf indf___register 1273 ; Uniform delay remaining = 46 Accumulated Delay = 79 1274 ; if { result <= thresholds_low ~~ {{ channel }} } start 1275 1c9 3024 movlw LOW thresholds_low 1276 1ca 0739 addwf delay__channel,w 1277 1cb 0084 movwf fsr___register 1278 1cc 0800 movf indf___register,w 1279 1cd 0240 subwf delay__result,w 1280 1ce 1903 btfsc z___byte,z___bit 1281 1cf 1003 bcf c___byte,c___bit 1282 ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 1283 1d0 1c03 btfss c___byte,c___bit 1284 1d1 29d5 goto label419__0true 1285 label419__0false: 1286 ; Delay 2 cycles 1287 1d2 0000 nop 1288 1d3 0000 nop 1289 1d4 29d8 goto label419__0end 1290 label419__0true: 1291 ; if { result <= thresholds_low ~~ {{ channel }} } body start 1292 ; Uniform delay remaining = 46 Accumulated Delay = 0 1293 ; inputs := inputs & {{ mask ^ io_mask }} 1294 1d5 300f movlw 15 1295 1d6 063f xorwf delay__mask,w 1296 1d7 05ac andwf inputs,f 1297 ; Uniform delay remaining = 43 Accumulated Delay = 3 1298 ; Uniform delay remaining = 43 Accumulated Delay = 3 1299 ; if { result <= thresholds_low ~~ {{ channel }} } body end 1300 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 1301 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic 1302 label419__0end: 1303 ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 1304 ; if { result <= thresholds_low ~~ {{ channel }} } end 1305 ; Uniform delay remaining = 33 Accumulated Delay = 92 1306 ; if { result >= thresholds_high ~~ {{ channel }} } start 1307 1d8 3028 movlw LOW thresholds_high 1308 1d9 0739 addwf delay__channel,w 1309 1da 0084 movwf fsr___register 1310 1db 0800 movf indf___register,w 1311 1dc 0240 subwf delay__result,w 1312 ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 1313 1dd 1803 btfsc c___byte,c___bit 1314 1de 29e1 goto label422__0true 1315 label422__0false: 1316 ; Delay 1 cycles 1317 1df 0000 nop 1318 1e0 29e3 goto label422__0end 1319 label422__0true: 1320 ; if { result >= thresholds_high ~~ {{ channel }} } body start 1321 ; Uniform delay remaining = 33 Accumulated Delay = 0 1322 ; inputs := inputs | mask 1323 1e1 083f movf delay__mask,w 1324 1e2 04ac iorwf inputs,f 1325 ; Uniform delay remaining = 31 Accumulated Delay = 2 1326 ; Uniform delay remaining = 31 Accumulated Delay = 2 1327 ; if { result >= thresholds_high ~~ {{ channel }} } body end 1328 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 1329 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic 1330 label422__0end: 1331 ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 1332 ; if { result >= thresholds_high ~~ {{ channel }} } end 1333 ; Uniform delay remaining = 23 Accumulated Delay = 102 1334 ; inputs := inputs & io_mask 1335 1e3 300f movlw 15 1336 1e4 05ac andwf inputs,f 1337 ; Uniform delay remaining = 21 Accumulated Delay = 104 1338 ; Uniform delay remaining = 21 Accumulated Delay = 104 1339 ; else body end 1340 ; if exp=` counter @ 0 ' total delay=107 1341 ; if exp=` counter @ 0 ' generic 1342 label376__1end: 1343 ; Other expression=`{ counter @ 0 }' delay=107 1344 ; if { counter @ 0 } end 1345 ; Uniform delay remaining = 18 Accumulated Delay = 113 1346 ; Uniform delay remaining = 18 Accumulated Delay = 113 1347 ; Soak up remaining 18 cycles 1348 ; Delay 18 cycles 1349 1e5 3005 movlw 5 1350 1e6 00c1 movwf delay__354byte1 1351 delay__354delay0: 1352 1e7 0bc1 decfsz delay__354byte1,f 1353 1e8 29e7 goto delay__354delay0 1354 1e9 0000 nop 1355 1ea 0000 nop 1356 ; procedure delay end 1357 1eb 3400 retlw 0 1358 ; optimize 1 1359 1360 ; procedure get_byte start 1361 get_byte: 1362 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1363 0042 get_byte__variables__base equ global__variables__bank0+34 1364 0042 get_byte__bytes__base equ get_byte__variables__base+0 1365 0045 get_byte__bits__base equ get_byte__variables__base+3 1366 0003 get_byte__total__bytes equ 3 1367 ; arguments_none 1368 0042 get_byte__0return__byte equ get_byte__bytes__base+0 1369 ; Wait for a character and return it . 1370 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 1371 ; way the next call to get_byte < > will sychronize on the start 1372 ; bit instead of possibly starting a little later . 1373 0043 get_byte__count equ get_byte__bytes__base+1 1374 0044 get_byte__char equ get_byte__bytes__base+2 1375 ; Wait for start bit : 1376 ; receiving := 1 1377 1ec 1549 bsf receiving__byte,receiving__bit 1378 ; `while serial_in ...' start 1379 get_byte__445while__continue: 1380 ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 1381 1ed 1d85 btfss serial_in__byte,serial_in__bit 1382 1ee 29f1 goto get_byte__445while__break 1383 ; call delay {{ }} 1384 1ef 216e call delay 1385 1f0 29ed goto get_byte__445while__continue 1386 ; if exp=`serial_in' false goto 1387 ; Other expression=`serial_in' delay=-1 1388 get_byte__445while__break: 1389 ; `while serial_in ...' end 1390 ; Clear interrupts and interrupt pending : 1391 ; 1 cycle : 1392 ; serial_out := 1 1393 1f1 1685 bsf serial_out__byte,serial_out__bit 1394 ; Skip over start bit : 1395 ; call delay {{ }} 1396 1f2 216e call delay 1397 ; call delay {{ }} 1398 1f3 216e call delay 1399 ; call delay {{ }} 1400 1f4 216e call delay 1401 ; Sample in the middle third of each data bit : 1402 ; 1 cycle : 1403 ; char := 0 1404 1f5 01c4 clrf get_byte__char 1405 ; 2 cycles to set up loop : 1406 ; 1 + 1 + 2 = 4 1407 ; nop extra_instructions_per_bit - 4 1408 ; Delay 5 cycles 1409 1f6 0000 nop 1410 1f7 0000 nop 1411 1f8 0000 nop 1412 1f9 0000 nop 1413 1fa 0000 nop 1414 ; `count_down count 8 ...' start 1415 1fb 3008 movlw 8 1416 1fc 00c3 movwf get_byte__count 1417 get_byte__464_loop: 1418 ; call delay {{ }} 1419 1fd 216e call delay 1420 ; 2 cycles : 1421 ; char := char >> 1 1422 1fe 1003 bcf c___byte,c___bit 1423 1ff 0cc4 rrf get_byte__char,f 1424 ; 2 cycles : 1425 ; if { serial_in } start 1426 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1427 200 1985 btfsc serial_in__byte,serial_in__bit 1428 ; if { serial_in } body start 1429 ; char @ 7 := 1 1430 ; Select char @ 7 1431 0044 get_byte__char__470select0 equ get_byte__char+0 1432 0044 get_byte__char__470select0__byte equ get_byte__char+0 1433 0007 get_byte__char__470select0__bit equ 7 1434 201 17c4 bsf get_byte__char__470select0__byte,get_byte__char__470select0__bit 1435 ; if { serial_in } body end 1436 ; if exp=`serial_in' false skip delay=2 1437 ; Other expression=`{ serial_in }' delay=2 1438 ; if { serial_in } end 1439 ; call delay {{ }} 1440 202 216e call delay 1441 ; call delay {{ }} 1442 203 216e call delay 1443 ; 3 cycles at end of loop : 1444 ; 2 + 2 + 3 = 7 1445 ; nop extra_instructions_per_bit - 7 1446 ; Delay 2 cycles 1447 204 0000 nop 1448 205 0000 nop 1449 206 0bc3 decfsz get_byte__count,f 1450 207 29fd goto get_byte__464_loop 1451 get_byte__464_done: 1452 ; `count_down count 8 ...' end 1453 ; Skip over 2 / 3 ' s of stop bit : 1454 ; call delay {{ }} 1455 208 216e call delay 1456 ; call delay {{ }} 1457 209 216e call delay 1458 ; return char 1459 20a 0844 movf get_byte__char,w 1460 20b 00c2 movwf get_byte__0return__byte 1461 20c 3400 retlw 0 1462 ; procedure get_byte end 1463 1464 ; procedure send_byte start 1465 send_byte: 1466 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1467 0045 send_byte__variables__base equ global__variables__bank0+37 1468 0045 send_byte__bytes__base equ send_byte__variables__base+0 1469 0047 send_byte__bits__base equ send_byte__variables__base+2 1470 0002 send_byte__total__bytes equ 2 1471 0045 send_byte__char equ send_byte__bytes__base+0 1472 ; Send < char > to < tx > : 1473 0046 send_byte__count equ send_byte__bytes__base+1 1474 ; < receiving > will be 1 if the last get / put routine was a get . 1475 ; Before we start transmitting a response back , we want to ensure 1476 ; that there has been enough time to turn the line line around . 1477 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 1478 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 1479 ; for good measure . Technically , the second call to delay < > 1480 ; is not really needed . 1481 ; if { receiving } start 1482 ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 1483 20d 1d49 btfss receiving__byte,receiving__bit 1484 20e 2a12 goto label501__0end 1485 ; if { receiving } body start 1486 ; receiving := 0 1487 20f 1149 bcf receiving__byte,receiving__bit 1488 ; call delay {{ }} 1489 210 216e call delay 1490 ; call delay {{ }} 1491 211 216e call delay 1492 ; if { receiving } body end 1493 label501__0end: 1494 ; if exp=`receiving' empty false 1495 ; Other expression=`{ receiving }' delay=-1 1496 ; if { receiving } end 1497 ; Send the start bit : 1498 ; 1 cycle : 1499 ; serial_out := 0 1500 212 1285 bcf serial_out__byte,serial_out__bit 1501 ; call delay {{ }} 1502 213 216e call delay 1503 ; call delay {{ }} 1504 214 216e call delay 1505 ; call delay {{ }} 1506 215 216e call delay 1507 ; 2 cycles for loop setup : 1508 ; 1 + 2 = 3 1509 ; nop extra_instructions_per_bit - 3 1510 ; Delay 6 cycles 1511 216 0000 nop 1512 217 0000 nop 1513 218 0000 nop 1514 219 0000 nop 1515 21a 0000 nop 1516 21b 0000 nop 1517 ; Send the data : 1518 ; `count_down count 8 ...' start 1519 21c 3008 movlw 8 1520 21d 00c6 movwf send_byte__count 1521 send_byte__518_loop: 1522 ; 4 cycles : 1523 ; serial_out := char @ 0 1524 ; Alias variable for select char @ 0 1525 0045 send_byte__char__520select0 equ send_byte__char+0 1526 0045 send_byte__char__520select0__byte equ send_byte__char+0 1527 0000 send_byte__char__520select0__bit equ 0 1528 21e 1c45 btfss send_byte__char__520select0__byte,send_byte__char__520select0__bit 1529 21f 1285 bcf serial_out__byte,serial_out__bit 1530 220 1845 btfsc send_byte__char__520select0__byte,send_byte__char__520select0__bit 1531 221 1685 bsf serial_out__byte,serial_out__bit 1532 ; 2 cycles : 1533 ; char := char >> 1 1534 222 1003 bcf c___byte,c___bit 1535 223 0cc5 rrf send_byte__char,f 1536 ; call delay {{ }} 1537 224 216e call delay 1538 ; call delay {{ }} 1539 225 216e call delay 1540 ; call delay {{ }} 1541 226 216e call delay 1542 ; 3 cycles at end of loop : 1543 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 1544 227 0bc6 decfsz send_byte__count,f 1545 228 2a1e goto send_byte__518_loop 1546 send_byte__518_done: 1547 ; `count_down count 8 ...' end 1548 ; Send the stop bit : 1549 ; 1 cycle to close out previous loop : 1550 ; nop 1 1551 ; Delay 1 cycles 1552 229 0000 nop 1553 ; 1 cycle : 1554 ; serial_out := 1 1555 22a 1685 bsf serial_out__byte,serial_out__bit 1556 ; call delay {{ }} 1557 22b 216e call delay 1558 ; call delay {{ }} 1559 22c 216e call delay 1560 ; call delay {{ }} 1561 22d 216e call delay 1562 ; 2 cycles for call / return : 1563 ; 2 cycles for argument : 1564 ; 1 + 2 + 2 = 5 1565 ; nop extra_instructions_per_bit - 5 1566 ; Delay 4 cycles 1567 22e 0000 nop 1568 22f 0000 nop 1569 230 0000 nop 1570 231 0000 nop 1571 ; procedure send_byte end 1572 232 3400 retlw 0 1573 1574 ; procedure reset start 1575 reset: 1576 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1577 0047 reset__variables__base equ global__variables__bank0+39 1578 0047 reset__bytes__base equ reset__variables__base+0 1579 0049 reset__bits__base equ reset__variables__base+2 1580 0002 reset__total__bytes equ 2 1581 0048 reset__562byte0 equ reset__bytes__base+1 1582 0048 reset__563byte0 equ reset__bytes__base+1 1583 ; arguments_none 1584 ; This procedure will initialize all of the registers : 1585 0047 reset__index equ reset__bytes__base+0 1586 ; inputs := 0 1587 233 01ac clrf inputs 1588 ; high := 0 1589 234 01b1 clrf high 1590 ; low := 0 1591 235 01b2 clrf low 1592 ; raising := 0 1593 236 01b3 clrf raising 1594 ; falling := 0 1595 237 01b0 clrf falling 1596 ; complement := 0 1597 238 01ad clrf complement 1598 ; interrupt_enable := 0 1599 239 1049 bcf interrupt_enable__byte,interrupt_enable__bit 1600 ; interrupt_pending := 0 1601 23a 10c9 bcf interrupt_pending__byte,interrupt_pending__bit 1602 ; index := 0 1603 23b 01c7 clrf reset__index 1604 ; `while index < 4 ...' start 1605 reset__561while__continue: 1606 23c 3004 movlw 4 1607 23d 0247 subwf reset__index,w 1608 ; expression=` index < 4 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 1609 23e 1803 btfsc c___byte,c___bit 1610 23f 2a50 goto reset__561while__break 1611 ; thresholds_high ~~ {{ index }} := 0xc0 1612 240 30c0 movlw 192 1613 241 00c8 movwf reset__562byte0 1614 242 3028 movlw LOW thresholds_high 1615 243 0747 addwf reset__index,w 1616 244 0084 movwf fsr___register 1617 245 0848 movf reset__562byte0,w 1618 246 0080 movwf indf___register 1619 ; thresholds_low ~~ {{ index }} := 0x40 1620 247 3040 movlw 64 1621 248 00c8 movwf reset__563byte0 1622 249 3024 movlw LOW thresholds_low 1623 24a 0747 addwf reset__index,w 1624 24b 0084 movwf fsr___register 1625 24c 0848 movf reset__563byte0,w 1626 24d 0080 movwf indf___register 1627 ; index := index + 1 1628 24e 0ac7 incf reset__index,f 1629 24f 2a3c goto reset__561while__continue 1630 ; if exp=` index < 4 ' false goto 1631 ; Other expression=` index < 4 ' delay=-1 1632 reset__561while__break: 1633 ; `while index < 4 ...' end 1634 ; glitch := 0 1635 250 01ae clrf glitch 1636 ; id_index := 0 1637 251 01af clrf id_index 1638 ; serial_out := 1 1639 252 1685 bsf serial_out__byte,serial_out__bit 1640 ; procedure reset end 1641 253 3400 retlw 0 1642 1643 ; Register bank 0 used 41 bytes of 96 available bytes 1644 ; Register bank 1 used 0 bytes of 32 available bytes 1645 1646 end