1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0043 global__bit__variables__bank0 equ 67 5 00a0 global__bit__variables__bank1 equ 160 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 0003 rp0___byte equ 3 13 0005 rp0___bit equ 5 14 0003 rp1___byte equ 3 15 0006 rp1___bit equ 6 16 0003 irp___byte equ 3 17 0007 irp___bit equ 7 18 0085 trisa___register equ 0x85 19 0086 trisb___register equ 0x86 20 0004 fsr___register equ 4 21 000a pclath___register equ 10 22 org 0 23 start: 24 000 0000 nop 25 001 0000 nop 26 002 0000 nop 27 003 2805 goto skip___interrupt 28 interrupt___vector: 29 004 0009 retfie 30 skip___interrupt: 31 ; Use oscillator calibration stored in high memory 32 005 27ff call 2047 33 ; Switch from register bank 0 to register bank 1 (which contains 143) 34 006 1683 bsf rp0___byte,rp0___bit 35 ; Register bank is now 1 36 007 008f movwf 143 37 ; Initialize A/D system to allow digital I/O 38 008 3007 movlw 7 39 009 009f movwf 159 40 ; Switch from register bank 1 to register bank 0 (which contains 31) 41 00a 1283 bcf rp0___byte,rp0___bit 42 ; Register bank is now 0 43 00b 019f clrf 31 44 ; Initialize TRIS registers 45 00c 30cf movlw 207 46 00d 0065 tris 5 47 00e 018a clrf pclath___register 48 00f 2843 goto main 49 ; comment ############################################################################# 50 ; comment {} 51 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 52 ; comment {All rights reserved .} 53 ; comment {} 54 ; comment {Permission to use , copy , modify , distribute , and sell this software} 55 ; comment {for any purpose is hereby granted without fee provided that the above} 56 ; comment {copyright notice and this permission are retained . The author makes} 57 ; comment {no representations about the suitability of this software for any purpose .} 58 ; comment {It is provided { as is } without express or implied warranty .} 59 ; comment {} 60 ; comment {This is the code that implements the AIROD2 RoboBrick . Basically} 61 ; comment {it just waits for commands that come in at 2400 baud and responds} 62 ; comment {to them . See} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / robobricks / airod2 / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment ############################################################################# 69 ; processor pic12ce674 cp = off pwrte = off wdte = off mclre = off fosc = intrc_no_clock 70 ; 16244=0x3f74 8199=0x2007 71 __config 16244 72 2007 configuration___address equ 8199 73 ; comment {define processor constants} 74 ; constant clock_rate 4000000 75 3d0900 clock_rate equ 4000000 76 ; constant clocks_per_instruction 4 77 0004 clocks_per_instruction equ 4 78 ; constant instruction_rate clock_rate / clocks_per_instruction 79 f4240 instruction_rate equ 1000000 80 ; comment {define serial communication control constants} 81 ; constant baud_rate 2400 82 0960 baud_rate equ 2400 83 ; constant instructions_per_bit instruction_rate / baud_rate 84 01a0 instructions_per_bit equ 416 85 ; constant delays_per_bit 3 86 0003 delays_per_bit equ 3 87 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 88 008a instructions_per_delay equ 138 89 ; constant extra_instructions_per_bit 9 90 0009 extra_instructions_per_bit equ 9 91 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 92 0003 extra_instructions_per_delay equ 3 93 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 94 0087 delay_instructions equ 135 95 ; comment {Oscillator Mask :} 96 008f osccal equ 143 97 ; constant osccal_unit 0x10 98 0010 osccal_unit equ 16 99 ; comment {Analog to digital conversion result register :} 100 001e addres equ 30 101 ; comment {Analog to digital conversion register 0 :} 102 001f addcon0 equ 31 103 ; bind adon addcon0 @ 0 104 001f adon equ addcon0+0 105 001f adon__byte equ addcon0+0 106 0000 adon__bit equ 0 107 ; bind go_done addcon0 @ 2 108 001f go_done equ addcon0+0 109 001f go_done__byte equ addcon0+0 110 0002 go_done__bit equ 2 111 ; bind chs0 addcon0 @ 3 112 001f chs0 equ addcon0+0 113 001f chs0__byte equ addcon0+0 114 0003 chs0__bit equ 3 115 ; bind chs1 addcon0 @ 4 116 001f chs1 equ addcon0+0 117 001f chs1__byte equ addcon0+0 118 0004 chs1__bit equ 4 119 ; bind adcs0 addcon0 @ 6 120 001f adcs0 equ addcon0+0 121 001f adcs0__byte equ addcon0+0 122 0006 adcs0__bit equ 6 123 ; bind adcs1 addcon0 @ 7 124 001f adcs1 equ addcon0+0 125 001f adcs1__byte equ addcon0+0 126 0007 adcs1__bit equ 7 127 ; comment {Interrupt Control Register :} 128 000b intcon equ 11 129 ; bind gpif intcon @ 0 130 000b gpif equ intcon+0 131 000b gpif__byte equ intcon+0 132 0000 gpif__bit equ 0 133 ; bind intf intcon @ 1 134 000b intf equ intcon+0 135 000b intf__byte equ intcon+0 136 0001 intf__bit equ 1 137 ; bind toif intcon @ 2 138 000b toif equ intcon+0 139 000b toif__byte equ intcon+0 140 0002 toif__bit equ 2 141 ; bind gpie intcon @ 3 142 000b gpie equ intcon+0 143 000b gpie__byte equ intcon+0 144 0003 gpie__bit equ 3 145 ; bind inte intcon @ 4 146 000b inte equ intcon+0 147 000b inte__byte equ intcon+0 148 0004 inte__bit equ 4 149 ; bind toie intcon @ 5 150 000b toie equ intcon+0 151 000b toie__byte equ intcon+0 152 0005 toie__bit equ 5 153 ; bind peie intcon @ 6 154 000b peie equ intcon+0 155 000b peie__byte equ intcon+0 156 0006 peie__bit equ 6 157 ; bind gie intcon @ 7 158 000b gie equ intcon+0 159 000b gie__byte equ intcon+0 160 0007 gie__bit equ 7 161 000c pir1 equ 12 162 ; bind adif pir1 @ 6 163 000c adif equ pir1+0 164 000c adif__byte equ pir1+0 165 0006 adif__bit equ 6 166 008c pie1 equ 140 167 ; bind adie pie1 @ 6 168 008c adie equ pie1+0 169 008c adie__byte equ pie1+0 170 0006 adie__bit equ 6 171 ; comment {Analog to digital conversion register 1 :} 172 009f addcon1 equ 159 173 ; bind pcfg0 addcon1 @ 0 174 009f pcfg0 equ addcon1+0 175 009f pcfg0__byte equ addcon1+0 176 0000 pcfg0__bit equ 0 177 ; bind pcfg1 addcon1 @ 1 178 009f pcfg1 equ addcon1+0 179 009f pcfg1__byte equ addcon1+0 180 0001 pcfg1__bit equ 1 181 ; bind pcfg2 addcon1 @ 2 182 009f pcfg2 equ addcon1+0 183 009f pcfg2__byte equ addcon1+0 184 0002 pcfg2__bit equ 2 185 ; constant airod0_bit 0 186 0000 airod0_bit equ 0 187 ; constant vref_bit 1 188 0001 vref_bit equ 1 189 ; constant airod1_bit 2 190 0002 airod1_bit equ 2 191 ; constant serial_in_bit 3 192 0003 serial_in_bit equ 3 193 ; constant enable_bit 4 194 0004 enable_bit equ 4 195 ; constant serial_out_bit 5 196 0005 serial_out_bit equ 5 197 ; constant io_mask 3 198 0003 io_mask equ 3 199 ; comment {define port bit assignments} 200 0005 porta equ 5 201 0005 airod0__byte equ 5 202 0000 airod0__bit equ 0 203 0005 vref__byte equ 5 204 0001 vref__bit equ 1 205 0005 airod1__byte equ 5 206 0002 airod1__bit equ 2 207 0005 enable__byte equ 5 208 0004 enable__bit equ 4 209 0005 serial_in__byte equ 5 210 0003 serial_in__bit equ 3 211 0005 serial_out__byte equ 5 212 0005 serial_out__bit equ 5 213 ; constant analogs_size 2 214 0002 analogs_size equ 2 215 ; string_constants Start 216 string___fetch: 217 010 0082 movwf pcl___register 218 ; id = 1 , 0 , 20 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'AIROD2A' , 15 , 0s'Gramlich&Benson' 219 0000 id___string equ 0 220 id: 221 011 0782 addwf pcl___register,f 222 ; Length = 48 223 012 3430 retlw 48 224 ; 1 225 013 3401 retlw 1 226 ; 0 227 014 3400 retlw 0 228 ; 20 229 015 3414 retlw 20 230 ; 0 231 016 3400 retlw 0 232 ; 0 233 017 3400 retlw 0 234 ; 0 235 018 3400 retlw 0 236 ; 0 237 019 3400 retlw 0 238 ; 0 239 01a 3400 retlw 0 240 ; 0r'16' 241 01b 34bb retlw 187 ; random number 242 01c 34a3 retlw 163 ; random number 243 01d 34f0 retlw 240 ; random number 244 01e 343b retlw 59 ; random number 245 01f 344f retlw 79 ; random number 246 020 3405 retlw 5 ; random number 247 021 3471 retlw 113 ; random number 248 022 34ca retlw 202 ; random number 249 023 346a retlw 106 ; random number 250 024 346c retlw 108 ; random number 251 025 3444 retlw 68 ; random number 252 026 34db retlw 219 ; random number 253 027 34e8 retlw 232 ; random number 254 028 3427 retlw 39 ; random number 255 029 349b retlw 155 ; random number 256 02a 34fa retlw 250 ; random number 257 ; 7 258 02b 3407 retlw 7 259 ; `AIROD2A' 260 02c 3441 retlw 65 261 02d 3449 retlw 73 262 02e 3452 retlw 82 263 02f 344f retlw 79 264 030 3444 retlw 68 265 031 3432 retlw 50 266 032 3441 retlw 65 267 ; 15 268 033 340f retlw 15 269 ; `Gramlich&Benson' 270 034 3447 retlw 71 271 035 3472 retlw 114 272 036 3461 retlw 97 273 037 346d retlw 109 274 038 346c retlw 108 275 039 3469 retlw 105 276 03a 3463 retlw 99 277 03b 3468 retlw 104 278 03c 3426 retlw 38 279 03d 3442 retlw 66 280 03e 3465 retlw 101 281 03f 346e retlw 110 282 040 3473 retlw 115 283 041 346f retlw 111 284 042 346e retlw 110 285 ; string__constants End 286 0020 analogs equ global__variables__bank0+0 287 0022 thresholds_low equ global__variables__bank0+2 288 0024 thresholds_high equ global__variables__bank0+4 289 0026 inputs equ global__variables__bank0+6 290 0027 complement equ global__variables__bank0+7 291 0028 glitch equ global__variables__bank0+8 292 0029 id_index equ global__variables__bank0+9 293 ; comment {Interrupt masks :} 294 0043 interrupt_enable equ global__bit__variables__bank0+0 295 0043 interrupt_enable__byte equ global__bit__variables__bank0+0 296 0000 interrupt_enable__bit equ 0 297 0043 interrupt_pending equ global__bit__variables__bank0+0 298 0043 interrupt_pending__byte equ global__bit__variables__bank0+0 299 0001 interrupt_pending__bit equ 1 300 0043 receiving equ global__bit__variables__bank0+0 301 0043 receiving__byte equ global__bit__variables__bank0+0 302 0002 receiving__bit equ 2 303 002a falling equ global__variables__bank0+10 304 002b high equ global__variables__bank0+11 305 002c low equ global__variables__bank0+12 306 002d raising equ global__variables__bank0+13 307 308 ; procedure main start 309 main: 310 002e main__variables__base equ global__variables__bank0+14 311 002e main__bytes__base equ main__variables__base+0 312 0032 main__bits__base equ main__variables__base+4 313 0005 main__total__bytes equ 5 314 0031 main__269byte0 equ main__bytes__base+3 315 0031 main__144byte0 equ main__bytes__base+3 316 0031 main__276byte0 equ main__bytes__base+3 317 0031 main__227byte0 equ main__bytes__base+3 318 0031 main__223byte0 equ main__bytes__base+3 319 0031 main__233byte0 equ main__bytes__base+3 320 0031 main__147byte0 equ main__bytes__base+3 321 ; arguments_none 322 002e main__bit equ main__bytes__base+0 323 002f main__command equ main__bytes__base+1 324 0030 main__temporary equ main__bytes__base+2 325 ; Initialize the A / D module : 326 ; GP4 = Digital , GP2 = Analog , GP1 = Vref , GP0 = Analog 327 ; addcon1 := 3 328 043 3003 movlw 3 329 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 330 044 1683 bsf rp0___byte,rp0___bit 331 ; Register bank is now 1 332 045 009f movwf addcon1 333 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : 334 ; addcon0 := 0x41 335 046 3041 movlw 65 336 ; Switch from register bank 1 to register bank 0 (which contains addcon0) 337 047 1283 bcf rp0___byte,rp0___bit 338 ; Register bank is now 0 339 048 009f movwf addcon0 340 ; adif := 0 341 049 130c bcf adif__byte,adif__bit 342 ; adie := 0 343 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) 344 04a 1683 bsf rp0___byte,rp0___bit 345 ; Register bank is now 1 346 04b 130c bcf adie__byte,adie__bit 347 ; gie := 0 348 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) 349 04c 1283 bcf rp0___byte,rp0___bit 350 ; Register bank is now 0 351 04d 138b bcf gie__byte,gie__bit 352 ; call reset {{ }} 353 04e 2236 call reset 354 ; Set the direction : 355 ; loop_forever ... start 356 main__139loop__forever: 357 ; Wait for a command : 358 ; command := get_byte {{ }} 359 04f 21ef call get_byte 360 050 083c movf get_byte__0return__byte,w 361 051 00af movwf main__command 362 ; Dispatch on command : 363 ; switch { command >> 6 } 364 052 3000 movlw HIGH switch__144block_start 365 053 008a movwf pclath___register 366 054 0e2f swapf main__command,w 367 055 00b1 movwf main__144byte0 368 056 0cb1 rrf main__144byte0,f 369 057 0c31 rrf main__144byte0,w 370 058 3903 andlw 3 371 ; case 0 372 ; case 1 2 373 ; case 3 374 switch__144block_start: 375 059 0782 addwf pcl___register,f 376 05a 285e goto switch__144block145 377 05b 290b goto switch__144block264 378 05c 290b goto switch__144block264 379 05d 290c goto switch__144block267 380 switch__144block_end: 381 ; switch_check 144 switch__144block_start switch__144block_end 382 switch__144block145: 383 ; Command = 00 xx xxxx : 384 ; switch { command >> 3 } 385 05e 3000 movlw HIGH switch__147block_start 386 05f 008a movwf pclath___register 387 060 0c2f rrf main__command,w 388 061 00b1 movwf main__147byte0 389 062 0cb1 rrf main__147byte0,f 390 063 0c31 rrf main__147byte0,w 391 064 391f andlw 31 392 ; case 0 393 ; case 1 394 ; case 2 395 ; case 4 5 6 396 switch__147block_start: 397 065 0782 addwf pcl___register,f 398 066 286e goto switch__147block148 399 067 2899 goto switch__147block181 400 068 28bb goto switch__147block209 401 069 290a goto switch__147default259 402 06a 28e8 goto switch__147block231 403 06b 28e8 goto switch__147block231 404 06c 28e8 goto switch__147block231 405 06d 290a goto switch__147default259 406 switch__147block_end: 407 ; switch_check 147 switch__147block_start switch__147block_end 408 switch__147block148: 409 ; Command = 0000 0 xxx : 410 ; switch { command & 7 } 411 06e 3000 movlw HIGH switch__150block_start 412 06f 008a movwf pclath___register 413 070 3007 movlw 7 414 071 052f andwf main__command,w 415 ; case 0 1 416 ; case 2 417 ; case 3 418 ; case 4 419 ; case 5 420 ; case 6 7 421 switch__150block_start: 422 072 0782 addwf pcl___register,f 423 073 287b goto switch__150block151 424 074 287b goto switch__150block151 425 075 2882 goto switch__150block155 426 076 2887 goto switch__150block159 427 077 288b goto switch__150block163 428 078 288d goto switch__150block167 429 079 2894 goto switch__150block175 430 07a 2894 goto switch__150block175 431 switch__150block_end: 432 ; switch_check 150 switch__150block_start switch__150block_end 433 switch__150block151: 434 ; Read Pin < Command = 0000 000 b > : 435 ; call send_byte {{ analogs ~~ {{ command }} }} 436 07b 3020 movlw LOW analogs 437 07c 072f addwf main__command,w 438 07d 0084 movwf fsr___register 439 07e 0800 movf indf___register,w 440 07f 00bf movwf send_byte__char 441 080 2210 call send_byte 442 081 2898 goto switch__150end 443 switch__150block155: 444 ; Read Binary Values < Command = 0000 0010 > : 445 ; call send_byte {{ inputs ^ complement }} 446 082 0826 movf inputs,w 447 083 0627 xorwf complement,w 448 084 00bf movwf send_byte__char 449 085 2210 call send_byte 450 086 2898 goto switch__150end 451 switch__150block159: 452 ; Read Raw Binary < Command = 0000 0011 > : 453 ; call send_byte {{ inputs }} 454 087 0826 movf inputs,w 455 088 00bf movwf send_byte__char 456 089 2210 call send_byte 457 08a 2898 goto switch__150end 458 switch__150block163: 459 ; Reset < Command = 0000 0100 > : 460 ; call reset {{ }} 461 08b 2236 call reset 462 08c 2898 goto switch__150end 463 switch__150block167: 464 ; Read Enable Bit < Command = 0000 0110 > : 465 ; temporary := 0 466 08d 01b0 clrf main__temporary 467 ; if { enable } start 468 ; expression=`{ enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 469 08e 1a05 btfsc enable__byte,enable__bit 470 ; if { enable } body start 471 ; temporary @ 0 := 1 472 ; Select temporary @ 0 473 0030 main__temporary__171select0 equ main__temporary+0 474 0030 main__temporary__171select0__byte equ main__temporary+0 475 0000 main__temporary__171select0__bit equ 0 476 08f 1430 bsf main__temporary__171select0__byte,main__temporary__171select0__bit 477 ; if { enable } body end 478 ; if exp=`enable' false skip delay=2 479 ; Other expression=`{ enable }' delay=2 480 ; if { enable } end 481 ; call send_byte {{ temporary }} 482 090 0830 movf main__temporary,w 483 091 00bf movwf send_byte__char 484 092 2210 call send_byte 485 093 2898 goto switch__150end 486 switch__150block175: 487 ; Set Enable Bit < Command = 0000 011 e > : 488 ; enable := command @ 0 489 ; Alias variable for select command @ 0 490 002f main__command__177select0 equ main__command+0 491 002f main__command__177select0__byte equ main__command+0 492 0000 main__command__177select0__bit equ 0 493 094 1c2f btfss main__command__177select0__byte,main__command__177select0__bit 494 095 1205 bcf enable__byte,enable__bit 495 096 182f btfsc main__command__177select0__byte,main__command__177select0__bit 496 097 1605 bsf enable__byte,enable__bit 497 switch__150end: 498 098 290a goto switch__147end 499 switch__147block181: 500 ; Command = 0000 1 xxx : 501 ; switch { command & 7 } 502 099 3000 movlw HIGH switch__183block_start 503 09a 008a movwf pclath___register 504 09b 3007 movlw 7 505 09c 052f andwf main__command,w 506 ; case 0 507 ; case 1 508 ; case 2 509 ; case 3 510 ; case 4 511 switch__183block_start: 512 09d 0782 addwf pcl___register,f 513 09e 28a6 goto switch__183block184 514 09f 28aa goto switch__183block188 515 0a0 28ae goto switch__183block192 516 0a1 28b2 goto switch__183block196 517 0a2 28b6 goto switch__183block200 518 0a3 28ba goto switch__183default204 519 0a4 28ba goto switch__183default204 520 0a5 28ba goto switch__183default204 521 switch__183block_end: 522 ; switch_check 183 switch__183block_start switch__183block_end 523 switch__183block184: 524 ; Read Complement Mask < Command = 0000 1000 > : 525 ; call send_byte {{ complement }} 526 0a6 0827 movf complement,w 527 0a7 00bf movwf send_byte__char 528 0a8 2210 call send_byte 529 0a9 28ba goto switch__183end 530 switch__183block188: 531 ; Read High Mask < Command = 0000 1001 > : 532 ; call send_byte {{ high }} 533 0aa 082b movf high,w 534 0ab 00bf movwf send_byte__char 535 0ac 2210 call send_byte 536 0ad 28ba goto switch__183end 537 switch__183block192: 538 ; Read Low Mask < Command = 0000 1010 > : 539 ; call send_byte {{ low }} 540 0ae 082c movf low,w 541 0af 00bf movwf send_byte__char 542 0b0 2210 call send_byte 543 0b1 28ba goto switch__183end 544 switch__183block196: 545 ; Read Raising Mask < Command = 0000 1011 > : 546 ; call send_byte {{ raising }} 547 0b2 082d movf raising,w 548 0b3 00bf movwf send_byte__char 549 0b4 2210 call send_byte 550 0b5 28ba goto switch__183end 551 switch__183block200: 552 ; Read Falling Mask < Command = 0000 1100 > : 553 ; call send_byte {{ falling }} 554 0b6 082a movf falling,w 555 0b7 00bf movwf send_byte__char 556 0b8 2210 call send_byte 557 0b9 28ba goto switch__183end 558 switch__183default204: 559 ; Undefined command : 560 switch__183end: 561 0ba 290a goto switch__147end 562 switch__147block209: 563 ; Command = 0001 0 xxx : 564 ; bit := command & 1 565 0bb 3001 movlw 1 566 0bc 052f andwf main__command,w 567 0bd 00ae movwf main__bit 568 ; switch { {{ command >> 1 }} & 3 } 569 0be 3000 movlw HIGH switch__212block_start 570 0bf 008a movwf pclath___register 571 0c0 1003 bcf c___byte,c___bit 572 0c1 0c2f rrf main__command,w 573 0c2 3903 andlw 3 574 ; case 0 575 ; case 1 576 ; case 2 577 ; case 3 578 switch__212block_start: 579 0c3 0782 addwf pcl___register,f 580 0c4 28c8 goto switch__212block213 581 0c5 28cf goto switch__212block217 582 0c6 28d6 goto switch__212block221 583 0c7 28df goto switch__212block225 584 switch__212block_end: 585 ; switch_check 212 switch__212block_start switch__212block_end 586 switch__212block213: 587 ; Read High Threshold < Command = 0001 000 b > : 588 ; call send_byte {{ thresholds_high ~~ {{ bit }} }} 589 0c8 3024 movlw LOW thresholds_high 590 0c9 072e addwf main__bit,w 591 0ca 0084 movwf fsr___register 592 0cb 0800 movf indf___register,w 593 0cc 00bf movwf send_byte__char 594 0cd 2210 call send_byte 595 0ce 28e7 goto switch__212end 596 switch__212block217: 597 ; Read Low Threshold < Command = 0001 001 b > : 598 ; call send_byte {{ thresholds_low ~~ {{ bit }} }} 599 0cf 3022 movlw LOW thresholds_low 600 0d0 072e addwf main__bit,w 601 0d1 0084 movwf fsr___register 602 0d2 0800 movf indf___register,w 603 0d3 00bf movwf send_byte__char 604 0d4 2210 call send_byte 605 0d5 28e7 goto switch__212end 606 switch__212block221: 607 ; Set High Threshold < Command = 0001 010 b > : 608 ; thresholds_high ~~ {{ bit }} := get_byte {{ }} 609 0d6 21ef call get_byte 610 0d7 083c movf get_byte__0return__byte,w 611 0d8 00b1 movwf main__223byte0 612 0d9 3024 movlw LOW thresholds_high 613 0da 072e addwf main__bit,w 614 0db 0084 movwf fsr___register 615 0dc 0831 movf main__223byte0,w 616 0dd 0080 movwf indf___register 617 0de 28e7 goto switch__212end 618 switch__212block225: 619 ; Set Low Threshold < Command = 0001 011 b > : 620 ; thresholds_low ~~ {{ bit }} := get_byte {{ }} 621 0df 21ef call get_byte 622 0e0 083c movf get_byte__0return__byte,w 623 0e1 00b1 movwf main__227byte0 624 0e2 3022 movlw LOW thresholds_low 625 0e3 072e addwf main__bit,w 626 0e4 0084 movwf fsr___register 627 0e5 0831 movf main__227byte0,w 628 0e6 0080 movwf indf___register 629 switch__212end: 630 0e7 290a goto switch__147end 631 switch__147block231: 632 ; temporary := command & io_mask 633 0e8 3003 movlw 3 634 0e9 052f andwf main__command,w 635 0ea 00b0 movwf main__temporary 636 ; switch { {{ command >> 2 }} & 7 } 637 0eb 3000 movlw HIGH switch__233block_start 638 0ec 008a movwf pclath___register 639 0ed 0c2f rrf main__command,w 640 0ee 00b1 movwf main__233byte0 641 0ef 0c31 rrf main__233byte0,w 642 0f0 3907 andlw 7 643 ; case 0 644 ; case 1 645 ; case 2 646 ; case 3 647 ; case 4 648 switch__233block_start: 649 0f1 0782 addwf pcl___register,f 650 0f2 28fa goto switch__233block234 651 0f3 28fd goto switch__233block238 652 0f4 2900 goto switch__233block242 653 0f5 2903 goto switch__233block246 654 0f6 2906 goto switch__233block250 655 0f7 2909 goto switch__233default254 656 0f8 2909 goto switch__233default254 657 0f9 2909 goto switch__233default254 658 switch__233block_end: 659 ; switch_check 233 switch__233block_start switch__233block_end 660 switch__233block234: 661 ; Set Complement Mask < Command = 0010 00 cc > : 662 ; complement := temporary 663 0fa 0830 movf main__temporary,w 664 0fb 00a7 movwf complement 665 0fc 2909 goto switch__233end 666 switch__233block238: 667 ; Set High Mask < Command = 0010 01 hh > : 668 ; high := temporary 669 0fd 0830 movf main__temporary,w 670 0fe 00ab movwf high 671 0ff 2909 goto switch__233end 672 switch__233block242: 673 ; Set Low Mask < Command = 0010 10 ll > : 674 ; low := temporary 675 100 0830 movf main__temporary,w 676 101 00ac movwf low 677 102 2909 goto switch__233end 678 switch__233block246: 679 ; Set Raising Mask < Command = 0010 11 rr > : 680 ; raising := temporary 681 103 0830 movf main__temporary,w 682 104 00ad movwf raising 683 105 2909 goto switch__233end 684 switch__233block250: 685 ; Set Falling Mask < Command = 0011 00 ff > : 686 ; falling := temporary 687 106 0830 movf main__temporary,w 688 107 00aa movwf falling 689 108 2909 goto switch__233end 690 switch__233default254: 691 ; Do nothing : 692 switch__233end: 693 109 290a goto switch__147end 694 switch__147default259: 695 ; Do nothing : 696 switch__147end: 697 10a 297e goto switch__144end 698 switch__144block264: 699 ; Do nothing < Command = 10 xx xxxx > : 700 10b 297e goto switch__144end 701 switch__144block267: 702 ; Command = 11 xx xxxx : 703 ; switch { {{ command >> 3 }} & 7 } 704 10c 3001 movlw HIGH switch__269block_start 705 10d 008a movwf pclath___register 706 10e 0c2f rrf main__command,w 707 10f 00b1 movwf main__269byte0 708 110 0cb1 rrf main__269byte0,f 709 111 0c31 rrf main__269byte0,w 710 112 3907 andlw 7 711 ; case 0 1 2 3 4 712 ; case 5 713 ; case 6 714 ; case 7 715 switch__269block_start: 716 113 0782 addwf pcl___register,f 717 114 291c goto switch__269block270 718 115 291c goto switch__269block270 719 116 291c goto switch__269block270 720 117 291c goto switch__269block270 721 118 291c goto switch__269block270 722 119 291d goto switch__269block274 723 11a 292d goto switch__269block288 724 11b 2949 goto switch__269block306 725 switch__269block_end: 726 ; switch_check 269 switch__269block_start switch__269block_end 727 switch__269block270: 728 ; Command = 1100 xxxx or 1110 0 xxx : 729 ; Do nothing : 730 11c 297e goto switch__269end 731 switch__269block274: 732 ; Read Interrupt Bits < Command = 1110 1111 > : 733 ; if { {{ command & 7 }} = 7 } start 734 11d 3007 movlw 7 735 11e 052f andwf main__command,w 736 11f 00b1 movwf main__276byte0 737 120 3007 movlw 7 738 121 0231 subwf main__276byte0,w 739 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 740 122 1d03 btfss z___byte,z___bit 741 123 292c goto label276__1end 742 ; if { {{ command & 7 }} = 7 } body start 743 ; Return Interrupt Bits : 744 ; temporary := 0 745 124 01b0 clrf main__temporary 746 ; if { interrupt_enable } start 747 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 748 125 1843 btfsc interrupt_enable__byte,interrupt_enable__bit 749 ; if { interrupt_enable } body start 750 ; temporary @ 1 := 1 751 ; Select temporary @ 1 752 0030 main__temporary__280select0 equ main__temporary+0 753 0030 main__temporary__280select0__byte equ main__temporary+0 754 0001 main__temporary__280select0__bit equ 1 755 126 14b0 bsf main__temporary__280select0__byte,main__temporary__280select0__bit 756 ; if { interrupt_enable } body end 757 ; if exp=`interrupt_enable' false skip delay=2 758 ; Other expression=`{ interrupt_enable }' delay=2 759 ; if { interrupt_enable } end 760 ; if { interrupt_pending } start 761 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 762 127 18c3 btfsc interrupt_pending__byte,interrupt_pending__bit 763 ; if { interrupt_pending } body start 764 ; temporary @ 0 := 1 765 ; Select temporary @ 0 766 0030 main__temporary__283select0 equ main__temporary+0 767 0030 main__temporary__283select0__byte equ main__temporary+0 768 0000 main__temporary__283select0__bit equ 0 769 128 1430 bsf main__temporary__283select0__byte,main__temporary__283select0__bit 770 ; if { interrupt_pending } body end 771 ; if exp=`interrupt_pending' false skip delay=2 772 ; Other expression=`{ interrupt_pending }' delay=2 773 ; if { interrupt_pending } end 774 ; call send_byte {{ temporary }} 775 129 0830 movf main__temporary,w 776 12a 00bf movwf send_byte__char 777 12b 2210 call send_byte 778 ; if { {{ command & 7 }} = 7 } body end 779 label276__1end: 780 ; if exp=` {{ command & 7 }} = 7 ' empty false 781 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 782 ; if { {{ command & 7 }} = 7 } end 783 12c 297e goto switch__269end 784 switch__269block288: 785 ; Shared Interrupt commands < Command = 1111 0 xxx > : 786 ; switch { command & 7 } 787 12d 3001 movlw HIGH switch__290block_start 788 12e 008a movwf pclath___register 789 12f 3007 movlw 7 790 130 052f andwf main__command,w 791 ; case 0 1 2 3 792 ; case 4 5 793 ; case 6 7 794 switch__290block_start: 795 131 0782 addwf pcl___register,f 796 132 293a goto switch__290block291 797 133 293a goto switch__290block291 798 134 293a goto switch__290block291 799 135 293a goto switch__290block291 800 136 2941 goto switch__290block296 801 137 2941 goto switch__290block296 802 138 2945 goto switch__290block300 803 139 2945 goto switch__290block300 804 switch__290block_end: 805 ; switch_check 290 switch__290block_start switch__290block_end 806 switch__290block291: 807 ; Set interrupt bits < Command = 1111 10 ep > : 808 ; interrupt_enable := command @ 1 809 ; Alias variable for select command @ 1 810 002f main__command__293select0 equ main__command+0 811 002f main__command__293select0__byte equ main__command+0 812 0001 main__command__293select0__bit equ 1 813 13a 1043 bcf interrupt_enable__byte,interrupt_enable__bit 814 13b 18af btfsc main__command__293select0__byte,main__command__293select0__bit 815 13c 1443 bsf interrupt_enable__byte,interrupt_enable__bit 816 ; interrupt_pending := command @ 0 817 ; Alias variable for select command @ 0 818 002f main__command__294select0 equ main__command+0 819 002f main__command__294select0__byte equ main__command+0 820 0000 main__command__294select0__bit equ 0 821 13d 10c3 bcf interrupt_pending__byte,interrupt_pending__bit 822 13e 182f btfsc main__command__294select0__byte,main__command__294select0__bit 823 13f 14c3 bsf interrupt_pending__byte,interrupt_pending__bit 824 140 2948 goto switch__290end 825 switch__290block296: 826 ; Set Interrupt Pending < Command = 1111 110 p > : 827 ; interrupt_pending := command @ 0 828 ; Alias variable for select command @ 0 829 002f main__command__298select0 equ main__command+0 830 002f main__command__298select0__byte equ main__command+0 831 0000 main__command__298select0__bit equ 0 832 141 10c3 bcf interrupt_pending__byte,interrupt_pending__bit 833 142 182f btfsc main__command__298select0__byte,main__command__298select0__bit 834 143 14c3 bsf interrupt_pending__byte,interrupt_pending__bit 835 144 2948 goto switch__290end 836 switch__290block300: 837 ; Set Interrupt Enable < Command = 1110 111 e > : 838 ; interrupt_enable := command @ 0 839 ; Alias variable for select command @ 0 840 002f main__command__302select0 equ main__command+0 841 002f main__command__302select0__byte equ main__command+0 842 0000 main__command__302select0__bit equ 0 843 145 1043 bcf interrupt_enable__byte,interrupt_enable__bit 844 146 182f btfsc main__command__302select0__byte,main__command__302select0__bit 845 147 1443 bsf interrupt_enable__byte,interrupt_enable__bit 846 switch__290end: 847 148 297e goto switch__269end 848 switch__269block306: 849 ; Shared commands < Command = 1111 1 xxx > : 850 ; switch { command & 7 } 851 149 3001 movlw HIGH switch__308block_start 852 14a 008a movwf pclath___register 853 14b 3007 movlw 7 854 14c 052f andwf main__command,w 855 ; case 0 856 ; case 1 857 ; case 2 858 ; case 3 859 ; case 4 860 ; case 5 861 ; case 6 862 ; case 7 863 switch__308block_start: 864 14d 0782 addwf pcl___register,f 865 14e 2956 goto switch__308block309 866 14f 295b goto switch__308block313 867 150 2960 goto switch__308block317 868 151 2966 goto switch__308block321 869 152 2969 goto switch__308block325 870 153 2974 goto switch__308block333 871 154 2976 goto switch__308block337 872 155 297b goto switch__308block342 873 switch__308block_end: 874 ; switch_check 308 switch__308block_start switch__308block_end 875 switch__308block309: 876 ; Clock Decrement < Command = 1111 1000 > : 877 ; osccal := osccal - osccal_unit 878 156 30f0 movlw 240 879 ; Switch from register bank 0 to register bank 1 (which contains osccal) 880 157 1683 bsf rp0___byte,rp0___bit 881 ; Register bank is now 1 882 158 078f addwf osccal,f 883 ; Switch from register bank 1 to register bank 0 884 159 1283 bcf rp0___byte,rp0___bit 885 ; Register bank is now 0 886 15a 297e goto switch__308end 887 switch__308block313: 888 ; Clock Increment < Command = 1111 1001 > : 889 ; osccal := osccal + osccal_unit 890 15b 3010 movlw 16 891 ; Switch from register bank 0 to register bank 1 (which contains osccal) 892 15c 1683 bsf rp0___byte,rp0___bit 893 ; Register bank is now 1 894 15d 078f addwf osccal,f 895 ; Switch from register bank 1 to register bank 0 896 15e 1283 bcf rp0___byte,rp0___bit 897 ; Register bank is now 0 898 15f 297e goto switch__308end 899 switch__308block317: 900 ; Clock Read < Command = 1111 1010 > : 901 ; call send_byte {{ osccal }} 902 ; Switch from register bank 0 to register bank 1 (which contains osccal) 903 160 1683 bsf rp0___byte,rp0___bit 904 ; Register bank is now 1 905 161 080f movf osccal,w 906 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 907 162 1283 bcf rp0___byte,rp0___bit 908 ; Register bank is now 0 909 163 00bf movwf send_byte__char 910 164 2210 call send_byte 911 165 297e goto switch__308end 912 switch__308block321: 913 ; Clock Pulse < Command = 1111 1011 > : 914 ; call send_byte {{ 0 }} 915 166 01bf clrf send_byte__char 916 167 2210 call send_byte 917 168 297e goto switch__308end 918 switch__308block325: 919 ; ID Next < Command = 1111 1100 > : 920 ; call send_byte {{ id ~~ {{ id_index }} }} 921 169 0a29 incf id_index,w 922 16a 018a clrf pclath___register 923 16b 2011 call id 924 16c 00bf movwf send_byte__char 925 16d 2210 call send_byte 926 ; id_index := id_index + 1 927 16e 0aa9 incf id_index,f 928 ; if { id_index >= id . size } start 929 16f 3030 movlw 48 930 170 0229 subwf id_index,w 931 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 932 171 1803 btfsc c___byte,c___bit 933 ; if { id_index >= id . size } body start 934 ; id_index := 0 935 172 01a9 clrf id_index 936 ; if { id_index >= id . size } body end 937 ; if exp=` id_index >= id . size ' false skip delay=4 938 ; Other expression=`{ id_index >= id . size }' delay=4 939 ; if { id_index >= id . size } end 940 173 297e goto switch__308end 941 switch__308block333: 942 ; ID Reset < Command = 1111 1101 > : 943 ; id_index := 0 944 174 01a9 clrf id_index 945 175 297e goto switch__308end 946 switch__308block337: 947 ; Glitch Read < Command = 1111 1110 > : 948 ; call send_byte {{ glitch }} 949 176 0828 movf glitch,w 950 177 00bf movwf send_byte__char 951 178 2210 call send_byte 952 ; glitch := 0 953 179 01a8 clrf glitch 954 17a 297e goto switch__308end 955 switch__308block342: 956 ; Glitch < Command = 1111 1111 > : 957 ; if { glitch != 0xff } start 958 17b 0a28 incf glitch,w 959 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 960 17c 1d03 btfss z___byte,z___bit 961 ; if { glitch != 0xff } body start 962 ; glitch := glitch + 1 963 17d 0aa8 incf glitch,f 964 ; if { glitch != 0xff } body end 965 ; if exp=` glitch != 0xff ' false skip delay=3 966 ; Other expression=`{ glitch != 0xff }' delay=3 967 ; if { glitch != 0xff } end 968 switch__308end: 969 switch__269end: 970 switch__144end: 971 17e 284f goto main__139loop__forever 972 ; loop_forever ... end 973 ; procedure main end 974 975 ; procedure delay start 976 ; optimize 0 977 delay: 978 0033 delay__variables__base equ global__variables__bank0+19 979 0033 delay__bytes__base equ delay__variables__base+0 980 003c delay__bits__base equ delay__variables__base+9 981 0009 delay__total__bytes equ 9 982 003b delay__356byte1 equ delay__bytes__base+8 983 003b delay__412byte0 equ delay__bytes__base+8 984 003b delay__389byte0 equ delay__bytes__base+8 985 003b delay__378byte3 equ delay__bytes__base+8 986 003b delay__410byte1 equ delay__bytes__base+8 987 ; arguments_none 988 ; uniform_delay delay_instructions 989 ; Uniform delay remaining = 131 Accumulated Delay = 0 990 ; Uniform delay remaining = 131 Accumulated Delay = 0 991 ; This procedure will delay for one third of a bit time . 992 ; Uniform delay remaining = 131 Accumulated Delay = 0 993 ; Uniform delay remaining = 131 Accumulated Delay = 0 994 ; Uniform delay remaining = 131 Accumulated Delay = 0 995 0033 delay__channel equ delay__bytes__base+0 996 ; Uniform delay remaining = 131 Accumulated Delay = 0 997 0034 delay__current equ delay__bytes__base+1 998 ; Uniform delay remaining = 131 Accumulated Delay = 0 999 0035 delay__changed equ delay__bytes__base+2 1000 ; Uniform delay remaining = 131 Accumulated Delay = 0 1001 0036 delay__previous equ delay__bytes__base+3 1002 ; Uniform delay remaining = 131 Accumulated Delay = 0 1003 0037 delay__not_current equ delay__bytes__base+4 1004 ; Uniform delay remaining = 131 Accumulated Delay = 0 1005 0038 delay__counter equ delay__bytes__base+5 1006 ; Uniform delay remaining = 131 Accumulated Delay = 0 1007 0039 delay__mask equ delay__bytes__base+6 1008 ; Uniform delay remaining = 131 Accumulated Delay = 0 1009 003a delay__result equ delay__bytes__base+7 1010 ; Uniform delay remaining = 131 Accumulated Delay = 0 1011 ; Uniform delay remaining = 131 Accumulated Delay = 0 1012 ; Kick the dog : 1013 ; Uniform delay remaining = 131 Accumulated Delay = 0 1014 ; watch_dog_reset 1015 17f 0064 clrwdt 1016 ; Uniform delay remaining = 130 Accumulated Delay = 1 1017 ; Uniform delay remaining = 130 Accumulated Delay = 1 1018 ; channel := {{ counter >> 1 }} & 1 1019 180 1003 bcf c___byte,c___bit 1020 181 0c38 rrf delay__counter,w 1021 182 3901 andlw 1 1022 183 00b3 movwf delay__channel 1023 ; Uniform delay remaining = 126 Accumulated Delay = 5 1024 ; counter := counter + 1 1025 184 0ab8 incf delay__counter,f 1026 ; Uniform delay remaining = 125 Accumulated Delay = 6 1027 ; if { counter @ 0 } start 1028 ; Alias variable for select counter @ 0 1029 0038 delay__counter__378select0 equ delay__counter+0 1030 0038 delay__counter__378select0__byte equ delay__counter+0 1031 0000 delay__counter__378select0__bit equ 0 1032 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=40 false_delay=100 true_size=44 false_size=49 1033 185 1c38 btfss delay__counter__378select0__byte,delay__counter__378select0__bit 1034 186 29b9 goto label378__1false 1035 label378__1true: 1036 ; if { counter @ 0 } body start 1037 ; Uniform delay remaining = 125 Accumulated Delay = 0 1038 ; Set up and wait for acquistion : 1039 ; Uniform delay remaining = 125 Accumulated Delay = 0 1040 ; addcon0 := {{ channel << 4 }} | 0x41 1041 187 0e33 swapf delay__channel,w 1042 188 39f0 andlw 240 1043 189 3841 iorlw 65 1044 18a 009f movwf addcon0 1045 ; Uniform delay remaining = 121 Accumulated Delay = 4 1046 ; Setup for interrupts : 1047 ; Uniform delay remaining = 121 Accumulated Delay = 4 1048 ; previous := current 1049 18b 0834 movf delay__current,w 1050 18c 00b6 movwf delay__previous 1051 ; Uniform delay remaining = 119 Accumulated Delay = 6 1052 ; Read the I / O port once : 1053 ; Uniform delay remaining = 119 Accumulated Delay = 6 1054 ; current := inputs ^ complement 1055 18d 0826 movf inputs,w 1056 18e 0627 xorwf complement,w 1057 18f 00b4 movwf delay__current 1058 ; Uniform delay remaining = 116 Accumulated Delay = 9 1059 ; not_current := current ^ io_mask 1060 190 3003 movlw 3 1061 191 0634 xorwf delay__current,w 1062 192 00b7 movwf delay__not_current 1063 ; Uniform delay remaining = 113 Accumulated Delay = 12 1064 ; changed := current ^ previous 1065 193 0834 movf delay__current,w 1066 194 0636 xorwf delay__previous,w 1067 195 00b5 movwf delay__changed 1068 ; Uniform delay remaining = 110 Accumulated Delay = 15 1069 ; Uniform delay remaining = 110 Accumulated Delay = 15 1070 ; See about triggering the interrupt_pending flag : 1071 ; Uniform delay remaining = 110 Accumulated Delay = 15 1072 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start 1073 196 082c movf low,w 1074 197 0537 andwf delay__not_current,w 1075 198 00bb movwf delay__389byte0 1076 199 082b movf high,w 1077 19a 0534 andwf delay__current,w 1078 19b 04bb iorwf delay__389byte0,f 1079 19c 0835 movf delay__changed,w 1080 19d 0534 andwf delay__current,w 1081 19e 052d andwf raising,w 1082 19f 04bb iorwf delay__389byte0,f 1083 1a0 0835 movf delay__changed,w 1084 1a1 0537 andwf delay__not_current,w 1085 1a2 052a andwf falling,w 1086 1a3 043b iorwf delay__389byte0,w 1087 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 1088 1a4 1d03 btfss z___byte,z___bit 1089 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start 1090 ; Uniform delay remaining = 110 Accumulated Delay = 0 1091 ; interrupt_pending := 1 1092 1a5 14c3 bsf interrupt_pending__byte,interrupt_pending__bit 1093 ; Uniform delay remaining = 109 Accumulated Delay = 1 1094 ; Uniform delay remaining = 109 Accumulated Delay = 1 1095 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end 1096 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 1097 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 1098 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end 1099 ; Uniform delay remaining = 94 Accumulated Delay = 31 1100 ; Uniform delay remaining = 94 Accumulated Delay = 31 1101 ; Send an interrupt if interrupts are enabled : 1102 ; Uniform delay remaining = 94 Accumulated Delay = 31 1103 ; if { interrupt_pending && interrupt_enable } start 1104 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1105 1a6 18c3 btfsc interrupt_pending__byte,interrupt_pending__bit 1106 1a7 29ab goto label394__2true 1107 label394__2false: 1108 ; Delay 2 cycles 1109 1a8 0000 nop 1110 1a9 0000 nop 1111 1aa 29b3 goto and394__0false 1112 label394__2true: 1113 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1114 1ab 1c43 btfss interrupt_enable__byte,interrupt_enable__bit 1115 1ac 29b0 goto label394__1false 1116 label394__1true: 1117 and394__0true: 1118 ; if { interrupt_pending && interrupt_enable } body start 1119 ; Uniform delay remaining = 94 Accumulated Delay = 0 1120 ; Shove serial out to low : 1121 ; Uniform delay remaining = 94 Accumulated Delay = 0 1122 ; interrupt_enable := 0 1123 1ad 1043 bcf interrupt_enable__byte,interrupt_enable__bit 1124 ; Uniform delay remaining = 93 Accumulated Delay = 1 1125 ; serial_out := 0 1126 1ae 1285 bcf serial_out__byte,serial_out__bit 1127 ; Uniform delay remaining = 92 Accumulated Delay = 2 1128 ; Uniform delay remaining = 92 Accumulated Delay = 2 1129 ; if { interrupt_pending && interrupt_enable } body end 1130 1af 29b3 goto label394__1end 1131 label394__1false: 1132 ; Delay 3 cycles 1133 1b0 0000 nop 1134 1b1 0000 nop 1135 1b2 0000 nop 1136 ; if exp=`interrupt_enable' total delay=6 1137 ; if exp=`interrupt_enable' generic 1138 label394__1end: 1139 ; Other expression=`interrupt_enable' delay=6 1140 ; if exp=`interrupt_pending' total delay=9 1141 ; if exp=`interrupt_pending' generic 1142 label394__2end: 1143 ; Other expression=`interrupt_pending' delay=9 1144 and394__0false: 1145 and394__0end: 1146 ; if { interrupt_pending && interrupt_enable } end 1147 ; Uniform delay remaining = 85 Accumulated Delay = 40 1148 ; Uniform delay remaining = 85 Accumulated Delay = 40 1149 ; if { counter @ 0 } body end 1150 ; Delay 59 cycles 1151 1b3 3013 movlw 19 1152 1b4 00bb movwf delay__378byte3 1153 delay__378delay2: 1154 1b5 0bbb decfsz delay__378byte3,f 1155 1b6 29b5 goto delay__378delay2 1156 1b7 0000 nop 1157 1b8 29ea goto label378__1end 1158 label378__1false: 1159 ; else body start 1160 ; Uniform delay remaining = 125 Accumulated Delay = 0 1161 ; Start the conversion : 1162 ; Uniform delay remaining = 125 Accumulated Delay = 0 1163 ; go_done := 1 1164 1b9 151f bsf go_done__byte,go_done__bit 1165 ; Uniform delay remaining = 124 Accumulated Delay = 1 1166 ; mask := 0 1167 1ba 01b9 clrf delay__mask 1168 ; Uniform delay remaining = 123 Accumulated Delay = 2 1169 ; if { channel @ 0 } start 1170 ; Alias variable for select channel @ 0 1171 0033 delay__channel__403select0 equ delay__channel+0 1172 0033 delay__channel__403select0__byte equ delay__channel+0 1173 0000 delay__channel__403select0__bit equ 0 1174 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1175 1bb 1833 btfsc delay__channel__403select0__byte,delay__channel__403select0__bit 1176 ; if { channel @ 0 } body start 1177 ; Uniform delay remaining = 123 Accumulated Delay = 0 1178 ; mask @ 1 := 1 1179 ; Select mask @ 1 1180 0039 delay__mask__404select0 equ delay__mask+0 1181 0039 delay__mask__404select0__byte equ delay__mask+0 1182 0001 delay__mask__404select0__bit equ 1 1183 1bc 14b9 bsf delay__mask__404select0__byte,delay__mask__404select0__bit 1184 ; Uniform delay remaining = 122 Accumulated Delay = 1 1185 ; Uniform delay remaining = 122 Accumulated Delay = 1 1186 ; if { channel @ 0 } body end 1187 1bd 1c33 btfss delay__channel__403select0__byte,delay__channel__403select0__bit 1188 ; else body start 1189 ; Uniform delay remaining = 123 Accumulated Delay = 0 1190 ; mask @ 0 := 1 1191 ; Select mask @ 0 1192 0039 delay__mask__406select0 equ delay__mask+0 1193 0039 delay__mask__406select0__byte equ delay__mask+0 1194 0000 delay__mask__406select0__bit equ 0 1195 1be 1439 bsf delay__mask__406select0__byte,delay__mask__406select0__bit 1196 ; Uniform delay remaining = 122 Accumulated Delay = 1 1197 ; Uniform delay remaining = 122 Accumulated Delay = 1 1198 ; else body end 1199 ; if exp=` channel @ 0 ' single true and false skip delay=4 1200 ; Other expression=`{ channel @ 0 }' delay=4 1201 ; if { channel @ 0 } end 1202 ; Uniform delay remaining = 119 Accumulated Delay = 6 1203 ; Delaying 60 uS is way longer than necessary for the conversion 1204 ; Uniform delay remaining = 119 Accumulated Delay = 6 1205 ; to complete . 1206 ; Uniform delay remaining = 119 Accumulated Delay = 6 1207 ; nop 60 1208 ; Delay 60 cycles 1209 1bf 3013 movlw 19 1210 1c0 00bb movwf delay__410byte1 1211 delay__410delay0: 1212 1c1 0bbb decfsz delay__410byte1,f 1213 1c2 29c1 goto delay__410delay0 1214 1c3 0000 nop 1215 1c4 0000 nop 1216 ; Uniform delay remaining = 59 Accumulated Delay = 66 1217 ; result := addres 1218 1c5 081e movf addres,w 1219 1c6 00ba movwf delay__result 1220 ; Uniform delay remaining = 57 Accumulated Delay = 68 1221 ; analogs ~~ {{ channel }} := result 1222 1c7 083a movf delay__result,w 1223 1c8 00bb movwf delay__412byte0 1224 1c9 3020 movlw LOW analogs 1225 1ca 0733 addwf delay__channel,w 1226 1cb 0084 movwf fsr___register 1227 1cc 083b movf delay__412byte0,w 1228 1cd 0080 movwf indf___register 1229 ; Uniform delay remaining = 50 Accumulated Delay = 75 1230 ; if { result <= thresholds_low ~~ {{ channel }} } start 1231 1ce 3022 movlw LOW thresholds_low 1232 1cf 0733 addwf delay__channel,w 1233 1d0 0084 movwf fsr___register 1234 1d1 0800 movf indf___register,w 1235 1d2 023a subwf delay__result,w 1236 1d3 1903 btfsc z___byte,z___bit 1237 1d4 1003 bcf c___byte,c___bit 1238 ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 1239 1d5 1c03 btfss c___byte,c___bit 1240 1d6 29da goto label413__0true 1241 label413__0false: 1242 ; Delay 2 cycles 1243 1d7 0000 nop 1244 1d8 0000 nop 1245 1d9 29dd goto label413__0end 1246 label413__0true: 1247 ; if { result <= thresholds_low ~~ {{ channel }} } body start 1248 ; Uniform delay remaining = 50 Accumulated Delay = 0 1249 ; inputs := inputs & {{ mask ^ io_mask }} 1250 1da 3003 movlw 3 1251 1db 0639 xorwf delay__mask,w 1252 1dc 05a6 andwf inputs,f 1253 ; Uniform delay remaining = 47 Accumulated Delay = 3 1254 ; Uniform delay remaining = 47 Accumulated Delay = 3 1255 ; if { result <= thresholds_low ~~ {{ channel }} } body end 1256 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 1257 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic 1258 label413__0end: 1259 ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 1260 ; if { result <= thresholds_low ~~ {{ channel }} } end 1261 ; Uniform delay remaining = 37 Accumulated Delay = 88 1262 ; if { result >= thresholds_high ~~ {{ channel }} } start 1263 1dd 3024 movlw LOW thresholds_high 1264 1de 0733 addwf delay__channel,w 1265 1df 0084 movwf fsr___register 1266 1e0 0800 movf indf___register,w 1267 1e1 023a subwf delay__result,w 1268 ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 1269 1e2 1803 btfsc c___byte,c___bit 1270 1e3 29e6 goto label416__0true 1271 label416__0false: 1272 ; Delay 1 cycles 1273 1e4 0000 nop 1274 1e5 29e8 goto label416__0end 1275 label416__0true: 1276 ; if { result >= thresholds_high ~~ {{ channel }} } body start 1277 ; Uniform delay remaining = 37 Accumulated Delay = 0 1278 ; inputs := inputs | mask 1279 1e6 0839 movf delay__mask,w 1280 1e7 04a6 iorwf inputs,f 1281 ; Uniform delay remaining = 35 Accumulated Delay = 2 1282 ; Uniform delay remaining = 35 Accumulated Delay = 2 1283 ; if { result >= thresholds_high ~~ {{ channel }} } body end 1284 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 1285 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic 1286 label416__0end: 1287 ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 1288 ; if { result >= thresholds_high ~~ {{ channel }} } end 1289 ; Uniform delay remaining = 27 Accumulated Delay = 98 1290 ; inputs := inputs & io_mask 1291 1e8 3003 movlw 3 1292 1e9 05a6 andwf inputs,f 1293 ; Uniform delay remaining = 25 Accumulated Delay = 100 1294 ; Uniform delay remaining = 25 Accumulated Delay = 100 1295 ; else body end 1296 ; if exp=` counter @ 0 ' total delay=103 1297 ; if exp=` counter @ 0 ' generic 1298 label378__1end: 1299 ; Other expression=`{ counter @ 0 }' delay=103 1300 ; if { counter @ 0 } end 1301 ; Uniform delay remaining = 22 Accumulated Delay = 109 1302 ; Uniform delay remaining = 22 Accumulated Delay = 109 1303 ; Soak up remaining 22 cycles 1304 ; Delay 22 cycles 1305 1ea 3007 movlw 7 1306 1eb 00bb movwf delay__356byte1 1307 delay__356delay0: 1308 1ec 0bbb decfsz delay__356byte1,f 1309 1ed 29ec goto delay__356delay0 1310 ; procedure delay end 1311 1ee 3400 retlw 0 1312 ; optimize 1 1313 1314 ; procedure get_byte start 1315 get_byte: 1316 003c get_byte__variables__base equ global__variables__bank0+28 1317 003c get_byte__bytes__base equ get_byte__variables__base+0 1318 003f get_byte__bits__base equ get_byte__variables__base+3 1319 0003 get_byte__total__bytes equ 3 1320 ; arguments_none 1321 003c get_byte__0return__byte equ get_byte__bytes__base+0 1322 ; Wait for a character and return it . 1323 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 1324 ; way the next call to get_byte < > will sychronize on the start 1325 ; bit instead of possibly starting a little later . 1326 003d get_byte__count equ get_byte__bytes__base+1 1327 003e get_byte__char equ get_byte__bytes__base+2 1328 ; Wait for start bit : 1329 ; receiving := 1 1330 1ef 1543 bsf receiving__byte,receiving__bit 1331 ; `while serial_in ...' start 1332 get_byte__439while__continue: 1333 ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 1334 1f0 1d85 btfss serial_in__byte,serial_in__bit 1335 1f1 29f4 goto get_byte__439while__break 1336 ; call delay {{ }} 1337 1f2 217f call delay 1338 1f3 29f0 goto get_byte__439while__continue 1339 ; if exp=`serial_in' false goto 1340 ; Other expression=`serial_in' delay=-1 1341 get_byte__439while__break: 1342 ; `while serial_in ...' end 1343 ; Clear interrupts and interrupt pending : 1344 ; 1 cycle : 1345 ; serial_out := 1 1346 1f4 1685 bsf serial_out__byte,serial_out__bit 1347 ; Skip over start bit : 1348 ; call delay {{ }} 1349 1f5 217f call delay 1350 ; call delay {{ }} 1351 1f6 217f call delay 1352 ; call delay {{ }} 1353 1f7 217f call delay 1354 ; Sample in the middle third of each data bit : 1355 ; 1 cycle : 1356 ; char := 0 1357 1f8 01be clrf get_byte__char 1358 ; 2 cycles to set up loop : 1359 ; 1 + 1 + 2 = 4 1360 ; nop extra_instructions_per_bit - 4 1361 ; Delay 5 cycles 1362 1f9 0000 nop 1363 1fa 0000 nop 1364 1fb 0000 nop 1365 1fc 0000 nop 1366 1fd 0000 nop 1367 ; `count_down count 8 ...' start 1368 1fe 3008 movlw 8 1369 1ff 00bd movwf get_byte__count 1370 get_byte__458_loop: 1371 ; call delay {{ }} 1372 200 217f call delay 1373 ; 2 cycles : 1374 ; char := char >> 1 1375 201 1003 bcf c___byte,c___bit 1376 202 0cbe rrf get_byte__char,f 1377 ; 2 cycles : 1378 ; if { serial_in } start 1379 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1380 203 1985 btfsc serial_in__byte,serial_in__bit 1381 ; if { serial_in } body start 1382 ; char @ 7 := 1 1383 ; Select char @ 7 1384 003e get_byte__char__464select0 equ get_byte__char+0 1385 003e get_byte__char__464select0__byte equ get_byte__char+0 1386 0007 get_byte__char__464select0__bit equ 7 1387 204 17be bsf get_byte__char__464select0__byte,get_byte__char__464select0__bit 1388 ; if { serial_in } body end 1389 ; if exp=`serial_in' false skip delay=2 1390 ; Other expression=`{ serial_in }' delay=2 1391 ; if { serial_in } end 1392 ; call delay {{ }} 1393 205 217f call delay 1394 ; call delay {{ }} 1395 206 217f call delay 1396 ; 3 cycles at end of loop : 1397 ; 2 + 2 + 3 = 7 1398 ; nop extra_instructions_per_bit - 7 1399 ; Delay 2 cycles 1400 207 0000 nop 1401 208 0000 nop 1402 209 0bbd decfsz get_byte__count,f 1403 20a 2a00 goto get_byte__458_loop 1404 get_byte__458_done: 1405 ; `count_down count 8 ...' end 1406 ; Skip over 2 / 3 ' s of stop bit : 1407 ; call delay {{ }} 1408 20b 217f call delay 1409 ; call delay {{ }} 1410 20c 217f call delay 1411 ; return char 1412 20d 083e movf get_byte__char,w 1413 20e 00bc movwf get_byte__0return__byte 1414 20f 3400 retlw 0 1415 ; procedure get_byte end 1416 1417 ; procedure send_byte start 1418 send_byte: 1419 003f send_byte__variables__base equ global__variables__bank0+31 1420 003f send_byte__bytes__base equ send_byte__variables__base+0 1421 0041 send_byte__bits__base equ send_byte__variables__base+2 1422 0002 send_byte__total__bytes equ 2 1423 003f send_byte__char equ send_byte__bytes__base+0 1424 ; Send < char > to < tx > : 1425 0040 send_byte__count equ send_byte__bytes__base+1 1426 ; < receiving > will be 1 if the last get / put routine was a get . 1427 ; Before we start transmitting a response back , we want to ensure 1428 ; that there has been enough time to turn the line line around . 1429 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 1430 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 1431 ; for good measure . Technically , the second call to delay < > 1432 ; is not really needed . 1433 ; if { receiving } start 1434 ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 1435 210 1d43 btfss receiving__byte,receiving__bit 1436 211 2a15 goto label495__0end 1437 ; if { receiving } body start 1438 ; receiving := 0 1439 212 1143 bcf receiving__byte,receiving__bit 1440 ; call delay {{ }} 1441 213 217f call delay 1442 ; call delay {{ }} 1443 214 217f call delay 1444 ; if { receiving } body end 1445 label495__0end: 1446 ; if exp=`receiving' empty false 1447 ; Other expression=`{ receiving }' delay=-1 1448 ; if { receiving } end 1449 ; Send the start bit : 1450 ; 1 cycle : 1451 ; serial_out := 0 1452 215 1285 bcf serial_out__byte,serial_out__bit 1453 ; call delay {{ }} 1454 216 217f call delay 1455 ; call delay {{ }} 1456 217 217f call delay 1457 ; call delay {{ }} 1458 218 217f call delay 1459 ; 2 cycles for loop setup : 1460 ; 1 + 2 = 3 1461 ; nop extra_instructions_per_bit - 3 1462 ; Delay 6 cycles 1463 219 0000 nop 1464 21a 0000 nop 1465 21b 0000 nop 1466 21c 0000 nop 1467 21d 0000 nop 1468 21e 0000 nop 1469 ; Send the data : 1470 ; `count_down count 8 ...' start 1471 21f 3008 movlw 8 1472 220 00c0 movwf send_byte__count 1473 send_byte__512_loop: 1474 ; 4 cycles : 1475 ; serial_out := char @ 0 1476 ; Alias variable for select char @ 0 1477 003f send_byte__char__514select0 equ send_byte__char+0 1478 003f send_byte__char__514select0__byte equ send_byte__char+0 1479 0000 send_byte__char__514select0__bit equ 0 1480 221 1c3f btfss send_byte__char__514select0__byte,send_byte__char__514select0__bit 1481 222 1285 bcf serial_out__byte,serial_out__bit 1482 223 183f btfsc send_byte__char__514select0__byte,send_byte__char__514select0__bit 1483 224 1685 bsf serial_out__byte,serial_out__bit 1484 ; 2 cycles : 1485 ; char := char >> 1 1486 225 1003 bcf c___byte,c___bit 1487 226 0cbf rrf send_byte__char,f 1488 ; call delay {{ }} 1489 227 217f call delay 1490 ; call delay {{ }} 1491 228 217f call delay 1492 ; call delay {{ }} 1493 229 217f call delay 1494 ; 3 cycles at end of loop : 1495 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 1496 22a 0bc0 decfsz send_byte__count,f 1497 22b 2a21 goto send_byte__512_loop 1498 send_byte__512_done: 1499 ; `count_down count 8 ...' end 1500 ; Send the stop bit : 1501 ; 1 cycle to close out previous loop : 1502 ; nop 1 1503 ; Delay 1 cycles 1504 22c 0000 nop 1505 ; 1 cycle : 1506 ; serial_out := 1 1507 22d 1685 bsf serial_out__byte,serial_out__bit 1508 ; call delay {{ }} 1509 22e 217f call delay 1510 ; call delay {{ }} 1511 22f 217f call delay 1512 ; call delay {{ }} 1513 230 217f call delay 1514 ; 2 cycles for call / return : 1515 ; 2 cycles for argument : 1516 ; 1 + 2 + 2 = 5 1517 ; nop extra_instructions_per_bit - 5 1518 ; Delay 4 cycles 1519 231 0000 nop 1520 232 0000 nop 1521 233 0000 nop 1522 234 0000 nop 1523 ; procedure send_byte end 1524 235 3400 retlw 0 1525 1526 ; procedure reset start 1527 reset: 1528 0041 reset__variables__base equ global__variables__bank0+33 1529 0041 reset__bytes__base equ reset__variables__base+0 1530 0043 reset__bits__base equ reset__variables__base+2 1531 0002 reset__total__bytes equ 2 1532 0042 reset__557byte0 equ reset__bytes__base+1 1533 0042 reset__558byte0 equ reset__bytes__base+1 1534 ; arguments_none 1535 ; This procedure will initialize all of the registers : 1536 0041 reset__index equ reset__bytes__base+0 1537 ; inputs := 0 1538 236 01a6 clrf inputs 1539 ; high := 0 1540 237 01ab clrf high 1541 ; low := 0 1542 238 01ac clrf low 1543 ; raising := 0 1544 239 01ad clrf raising 1545 ; falling := 0 1546 23a 01aa clrf falling 1547 ; complement := 0 1548 23b 01a7 clrf complement 1549 ; interrupt_enable := 0 1550 23c 1043 bcf interrupt_enable__byte,interrupt_enable__bit 1551 ; interrupt_pending := 0 1552 23d 10c3 bcf interrupt_pending__byte,interrupt_pending__bit 1553 ; index := 0 1554 23e 01c1 clrf reset__index 1555 ; enable := 1 1556 23f 1605 bsf enable__byte,enable__bit 1557 ; `while index < 2 ...' start 1558 reset__556while__continue: 1559 240 3002 movlw 2 1560 241 0241 subwf reset__index,w 1561 ; expression=` index < 2 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 1562 242 1803 btfsc c___byte,c___bit 1563 243 2a54 goto reset__556while__break 1564 ; thresholds_high ~~ {{ index }} := 0xc0 1565 244 30c0 movlw 192 1566 245 00c2 movwf reset__557byte0 1567 246 3024 movlw LOW thresholds_high 1568 247 0741 addwf reset__index,w 1569 248 0084 movwf fsr___register 1570 249 0842 movf reset__557byte0,w 1571 24a 0080 movwf indf___register 1572 ; thresholds_low ~~ {{ index }} := 0x40 1573 24b 3040 movlw 64 1574 24c 00c2 movwf reset__558byte0 1575 24d 3022 movlw LOW thresholds_low 1576 24e 0741 addwf reset__index,w 1577 24f 0084 movwf fsr___register 1578 250 0842 movf reset__558byte0,w 1579 251 0080 movwf indf___register 1580 ; index := index + 1 1581 252 0ac1 incf reset__index,f 1582 253 2a40 goto reset__556while__continue 1583 ; if exp=` index < 2 ' false goto 1584 ; Other expression=` index < 2 ' delay=-1 1585 reset__556while__break: 1586 ; `while index < 2 ...' end 1587 ; glitch := 0 1588 254 01a8 clrf glitch 1589 ; id_index := 0 1590 255 01a9 clrf id_index 1591 ; serial_out := 1 1592 256 1685 bsf serial_out__byte,serial_out__bit 1593 ; procedure reset end 1594 257 3400 retlw 0 1595 1596 ; Register bank 0 used 35 bytes of 96 available bytes 1597 ; Register bank 1 used 0 bytes of 32 available bytes 1598 1599 end