radix dec global__variables__bank0 equ 7 global__variables__bank1 equ 48 global__bit__variables__bank0 equ 30 global__bit__variables__bank1 equ 56 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers a___tris equ global__variables__bank1+8 movlw 223 tris 6 ; Switch from register bank 0 to register bank 1 (which contains a___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf a___tris ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the InOut4 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / inout4 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12c509 cp = off wdte = off mclre = off fosc = intrc ; 10=0xa 4095=0xfff __config 10 configuration___address equ 4095 ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {define serial communication control constants} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 osccal equ 5 ; constant osccal_unit 0x10 osccal_unit equ 16 ; constant inout_bit0 0 inout_bit0 equ 0 ; constant inout_bit1 1 inout_bit1 equ 1 ; constant inout_bit2 2 inout_bit2 equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; constant inout_bit3 4 inout_bit3 equ 4 ; constant serial_out_bit 5 serial_out_bit equ 5 ; constant inout_mask0 {{ 1 << inout_bit0 }} inout_mask0 equ 1 ; constant inout_mask1 {{ 1 << inout_bit1 }} inout_mask1 equ 2 ; constant inout_mask2 {{ 1 << inout_bit2 }} inout_mask2 equ 4 ; constant inout_mask3 {{ 1 << inout_bit3 }} inout_mask3 equ 16 ; constant serial_in_mask {{ 1 << serial_in_bit }} serial_in_mask equ 8 ; constant serial_out_mask {{ 1 << serial_out_bit }} serial_out_mask equ 32 ; constant io_mask 0xf io_mask equ 15 ; constant inout_mask {{ inout_mask0 | inout_mask1 | inout_mask2 | inout_mask3 }} inout_mask equ 23 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} serial_mask equ 40 ; comment {define port bit assignments} porta equ 6 inout0__byte equ 6 inout0__bit equ 0 inout1__byte equ 6 inout1__bit equ 1 inout2__byte equ 6 inout2__bit equ 2 inout3__byte equ 6 inout3__bit equ 4 serial_in__byte equ 6 serial_in__bit equ 3 serial_out__byte equ 6 serial_out__bit equ 5 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 19 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'InOut4A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 48 retlw 48 ; 1 retlw 1 ; 0 retlw 0 ; 19 retlw 19 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 228 ; random number retlw 160 ; random number retlw 153 ; random number retlw 180 ; random number retlw 12 ; random number retlw 96 ; random number retlw 34 ; random number retlw 145 ; random number retlw 12 ; random number retlw 122 ; random number retlw 203 ; random number retlw 91 ; random number retlw 10 ; random number retlw 27 ; random number retlw 249 ; random number retlw 212 ; random number ; 7 retlw 7 ; `InOut4A' retlw 73 retlw 110 retlw 79 retlw 117 retlw 116 retlw 52 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; constant id_size 8 + 16 + 1 + 7 + 1 + 15 id_size equ 48 ; bank 0 ; Default register bank is now 0 inputs equ global__variables__bank0+1 complement equ global__variables__bank0+2 direction equ global__variables__bank0+3 outputs equ global__variables__bank0+4 ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 falling equ global__variables__bank0+5 high equ global__variables__bank0+6 low equ global__variables__bank0+7 raising equ global__variables__bank0+8 ; comment {For now put all the smaller routines first so that they can live} ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} ; comment {can only call routines that are within the first 256 bytes < i . e .} ; comment {the first half > of the code page .} ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+9 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+5 delay__total__bytes equ 6 delay__93byte1 equ delay__bytes__base+4 delay__118byte0 equ delay__bytes__base+4 ; arguments_none ; uniform_delay instructions_per_delay ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; This procedure will delay for one third of a bit time . ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__current equ delay__bytes__base+0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__changed equ delay__bytes__base+1 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__previous equ delay__bytes__base+2 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__not_current equ delay__bytes__base+3 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 134 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Setup for interrupts : ; Uniform delay remaining = 133 Accumulated Delay = 1 ; previous := current movf delay__current,w movwf delay__previous ; Uniform delay remaining = 131 Accumulated Delay = 3 ; Read the I / O port once : ; Uniform delay remaining = 131 Accumulated Delay = 3 ; inputs := porta movf porta,w movwf inputs ; Uniform delay remaining = 129 Accumulated Delay = 5 ; inputs := inputs | {{ inputs >> 1 }} & 8 bcf c___byte,c___bit rrf inputs,w andlw 8 iorwf inputs,f ; Uniform delay remaining = 125 Accumulated Delay = 9 ; current := inputs ^ complement movf inputs,w xorwf complement,w movwf delay__current ; Uniform delay remaining = 122 Accumulated Delay = 12 ; not_current := current ^ 0xf movlw 15 xorwf delay__current,w movwf delay__not_current ; Uniform delay remaining = 119 Accumulated Delay = 15 ; changed := inputs ^ previous movf inputs,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 116 Accumulated Delay = 18 ; Uniform delay remaining = 116 Accumulated Delay = 18 ; See about triggering the interrupt_pending flag : ; Uniform delay remaining = 116 Accumulated Delay = 18 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start movf low,w andwf delay__not_current,w movwf delay__118byte0 movf high,w andwf delay__current,w iorwf delay__118byte0,f movf delay__changed,w andwf delay__current,w andwf raising,w iorwf delay__118byte0,f movf delay__changed,w andwf delay__not_current,w andwf falling,w iorwf delay__118byte0,w ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start ; Uniform delay remaining = 116 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 115 Accumulated Delay = 1 ; Uniform delay remaining = 115 Accumulated Delay = 1 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end ; Uniform delay remaining = 100 Accumulated Delay = 34 ; Uniform delay remaining = 100 Accumulated Delay = 34 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 100 Accumulated Delay = 34 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label123__2true label123__2false: ; Delay 1 cycles nop goto and123__0false label123__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_enable__byte,interrupt_enable__bit and123__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 100 Accumulated Delay = 0 ; Shove serial out to low : ; Uniform delay remaining = 100 Accumulated Delay = 0 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 99 Accumulated Delay = 1 ; Uniform delay remaining = 99 Accumulated Delay = 1 ; if { interrupt_pending && interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`interrupt_enable' delay=2 ; if exp=`interrupt_pending' total delay=5 ; if exp=`interrupt_pending' generic label123__2end: ; Other expression=`interrupt_pending' delay=5 and123__0false: and123__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 95 Accumulated Delay = 39 ; Uniform delay remaining = 95 Accumulated Delay = 39 ; Soak up remaining 95 cycles ; Delay 95 cycles movlw 31 movwf delay__93byte1 delay__93delay0: decfsz delay__93byte1,f goto delay__93delay0 nop ; procedure delay end retlw 0 ; optimize 1 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank0+15 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__145while__continue: ; expression=`serial_in' exp_delay=0 true_delay=139 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__145while__break ; call delay {{ }} call delay goto get_byte__145while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__145while__break: ; `while serial_in ...' end ; Clear interrupts and interrupt pending : ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; char := 0 clrf get_byte__char ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__159_loop: ; call delay {{ }} call delay ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss serial_in__byte,serial_in__bit goto label162__0end ; if { serial_in } body start ; char := char | 0x80 movlw 128 iorwf get_byte__char,f ; if { serial_in } body end label162__0end: ; if exp=`serial_in' empty false ; Other expression=`{ serial_in }' delay=-1 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz get_byte__count,f goto get_byte__159_loop get_byte__159_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank0+18 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=275 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label191__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label191__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf send_byte__count send_byte__204_loop: ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__205select0 equ send_byte__char+0 send_byte__char__205select0__byte equ send_byte__char+0 send_byte__char__205select0__bit equ 0 btfss send_byte__char__205select0__byte,send_byte__char__205select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__205select0__byte,send_byte__char__205select0__bit bsf serial_out__byte,serial_out__bit ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz send_byte__count,f goto send_byte__204_loop send_byte__204_done: ; `count_down count 8 ...' end ; Send the stop bit : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; procedure send_byte end retlw 0 ; procedure update_outputs start update_outputs: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 update_outputs__variables__base equ global__variables__bank0+20 update_outputs__bytes__base equ update_outputs__variables__base+0 update_outputs__bits__base equ update_outputs__variables__base+3 update_outputs__total__bytes equ 3 update_outputs__228byte1 equ update_outputs__bytes__base+2 ; arguments_none ; This procedure will update the output bits : update_outputs__mask equ update_outputs__bytes__base+0 update_outputs__temp equ update_outputs__bytes__base+1 ; mask := {{ direction << 1 }} & 0x10 | direction & 7 | serial_in_mask bcf c___byte,c___bit rlf direction,w andlw 16 movwf update_outputs__228byte1 movlw 7 andwf direction,w iorwf update_outputs__228byte1,w iorlw 8 movwf update_outputs__mask ; inline assembly statements begin tris 6 ; inline assembly statements end ; temp := porta & {{ mask | serial_mask }} movlw 40 iorwf update_outputs__mask,w andwf porta,w movwf update_outputs__temp ; mask := mask ^ 0x17 movlw 23 xorwf update_outputs__mask,f ; porta := temp | {{ {{ outputs << 1 }} | outputs }} & mask bcf c___byte,c___bit rlf outputs,w iorwf outputs,w andwf update_outputs__mask,w iorwf update_outputs__temp,w movwf porta ; procedure update_outputs end retlw 0 ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; procedure bit_to_mask start bit_to_mask: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 bit_to_mask__variables__base equ global__variables__bank1+0 bit_to_mask__bytes__base equ bit_to_mask__variables__base+0 bit_to_mask__bits__base equ bit_to_mask__variables__base+3 bit_to_mask__total__bytes equ 3 bit_to_mask__bit equ bit_to_mask__bytes__base+0 bit_to_mask__0return__byte equ bit_to_mask__bytes__base+1 ; Convert low order 2 - bits of < bit > to a mask . bit_to_mask__mask equ bit_to_mask__bytes__base+2 ; bit := bit & 3 movlw 3 andwf bit_to_mask__bit,f ; mask := 1 movlw 1 movwf bit_to_mask__mask ; `while bit != 0 ...' start bit_to_mask__250while__continue: movf bit_to_mask__bit,w ; expression=` bit != 0 ' exp_delay=1 true_delay=5 false_delay=2 true_size=4 false_size=1 btfsc z___byte,z___bit goto bit_to_mask__250while__break ; mask := mask << 1 bcf c___byte,c___bit rlf bit_to_mask__mask,f ; bit := bit - 1 decf bit_to_mask__bit,f goto bit_to_mask__250while__continue ; if exp=` bit != 0 ' false goto ; Other expression=` bit != 0 ' delay=-1 bit_to_mask__250while__break: ; `while bit != 0 ...' end ; return mask movf bit_to_mask__mask,w movwf bit_to_mask__0return__byte retlw 0 ; procedure bit_to_mask end ; comment {The main routine can span the 256 byte boundary :} ; procedure main start switch__302block_start: addwf pcl___register,f goto switch__302block303 goto switch__302block307 goto switch__302block311 goto switch__302block315 goto switch__302block319 goto switch__302block323 goto switch__302block327 goto switch__302block331 switch__302block_end: ; switch_check 302 switch__302block_start switch__302block_end switch__339block_start: addwf pcl___register,f goto switch__339block340 goto switch__339block344 goto switch__339block348 goto switch__339block352 goto switch__339block356 goto switch__339block360 goto switch__339block364 goto switch__339block369 switch__339block_end: ; switch_check 339 switch__339block_start switch__339block_end switch__299block_start: addwf pcl___register,f goto switch__299block300 goto switch__299block337 goto switch__299block376 goto switch__299block386 goto switch__299default400 goto switch__299default400 goto switch__299default400 goto switch__299default400 switch__299block_end: ; switch_check 299 switch__299block_start switch__299block_end switch__434block_start: addwf pcl___register,f goto switch__434block435 goto switch__434block435 goto switch__434block435 goto switch__434block435 goto switch__434block440 goto switch__434block440 goto switch__434block444 goto switch__434block444 switch__434block_end: ; switch_check 434 switch__434block_start switch__434block_end switch__452block_start: addwf pcl___register,f goto switch__452block453 goto switch__452block457 goto switch__452block461 goto switch__452block465 goto switch__452block469 goto switch__452block480 goto switch__452block484 goto switch__452block489 switch__452block_end: ; switch_check 452 switch__452block_start switch__452block_end switch__413block_start: addwf pcl___register,f goto switch__413block414 goto switch__413block414 goto switch__413block414 goto switch__413block414 goto switch__413block414 goto switch__413block418 goto switch__413block432 goto switch__413block450 switch__413block_end: ; switch_check 413 switch__413block_start switch__413block_end switch__296block_start: addwf pcl___register,f goto switch__296block297 goto switch__296block405 goto switch__296block408 goto switch__296block411 switch__296block_end: ; switch_check 296 switch__296block_start switch__296block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+3 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+5 main__total__bytes equ 5 main__391byte0 equ main__bytes__base+4 main__296byte0 equ main__bytes__base+4 main__420byte0 equ main__bytes__base+4 main__383byte0 equ main__bytes__base+4 main__397byte0 equ main__bytes__base+4 main__380byte0 equ main__bytes__base+4 main__413byte0 equ main__bytes__base+4 main__299byte0 equ main__bytes__base+4 ; arguments_none main__command equ main__bytes__base+0 main__glitch equ main__bytes__base+1 main__id_index equ main__bytes__base+2 main__result equ main__bytes__base+3 ; Let ROOT = http : / / web . gramlich . com / projects / robobricks . ; For InOut4A specific commands see : ; ROOT / InOut4 / rev_a / index . html ; For shared commands see : ; ROOT / specifications . html # Software_Protocol ; For shared interruptcommands see : ; ROOT / specifications . html # Interrupts ; Set the direction : ; direction inout0 read bsf a___tris,inout0__bit movf a___tris,w tris 6 ; direction inout1 read bsf a___tris,inout1__bit movf a___tris,w tris 6 ; direction inout2 read bsf a___tris,inout2__bit movf a___tris,w tris 6 ; direction inout3 read bsf a___tris,inout3__bit movf a___tris,w tris 6 ; outputs := 0 clrf outputs ; direction := 0xff movlw 255 movwf direction ; interrupt_enable := 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; falling := 0 clrf falling ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; id_index := 0 clrf main__id_index ; loop_forever ... start main__291loop__forever: ; Wait for a command : ; command := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__command ; Dispatch on command : ; switch { command >> 6 } swapf main__command,w movwf main__296byte0 rrf main__296byte0,f rrf main__296byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__296block_start switch__296block297: ; Command = 00 xx xxxx : ; switch { command >> 3 } rrf main__command,w movwf main__299byte0 rrf main__299byte0,f rrf main__299byte0,w andlw 31 ; case 0 ; case 1 ; case 2 ; case 3 goto switch__299block_start switch__299block300: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__302block_start switch__302block303: ; Read Inputs < Command = 0000 0000 > : ; call send_byte {{ inputs ^ complement }} movf inputs,w xorwf complement,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block307: ; Read Complement Mask < Command = 0000 0001 > : ; call send_byte {{ complement }} movf complement,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block311: ; Read Low Mask < Command = 0000 0010 > : ; call send_byte {{ low }} movf low,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block315: ; Read High Mask < Command = 0000 0011 > : ; call send_byte {{ high }} movf high,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block319: ; Read Raising Mask < Command = 0000 0100 > : ; call send_byte {{ raising }} movf raising,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block323: ; Read Falling Mask < Command = 0000 0101 > : ; call send_byte {{ falling }} movf falling,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block327: ; Read Direction Mask < Command = 0000 0110 > : ; call send_byte {{ direction }} movf direction,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__302end switch__302block331: ; Read Outputs < Command = 0000 0111 > : ; call send_byte {{ outputs }} movf outputs,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit switch__302end: goto switch__299end switch__299block337: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__339block_start switch__339block340: ; Read Raw < Command = 0000 1000 > : ; call send_byte {{ inputs }} movf inputs,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block344: ; Set Complement Mask < Command = 0000 1001 > : ; complement := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf complement ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block348: ; Set High Mask < Command = 0000 1010 > : ; high := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block352: ; Set Low Mask < Command = 0000 1011 > : ; low := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block356: ; Set Raising Mask < Command = 0000 1100 > : ; raising := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf raising ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block360: ; Set Falling Mask < Command = 0000 1101 > : ; falling := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf falling ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block364: ; Set Direction Mask < Command = 0000 1110 > : ; direction := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf direction ; call update_outputs {{ }} call update_outputs ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__339end switch__339block369: ; Set Outputs < Command = 0000 1111 > : ; outputs := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 15 movwf outputs ; call update_outputs {{ }} call update_outputs ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit switch__339end: goto switch__299end switch__299block376: ; Command = 0001 0 xxx : ; if { command @ 2 } start ; Alias variable for select command @ 2 main__command__378select0 equ main__command+0 main__command__378select0__byte equ main__command+0 main__command__378select0__bit equ 2 ; expression=`{ command @ 2 }' exp_delay=0 true_delay=5 false_delay=6 true_size=7 false_size=8 btfss main__command__378select0__byte,main__command__378select0__bit goto label378__1false label378__1true: ; if { command @ 2 } body start ; Bit Set < Command = 0001 01 bb > : ; outputs := outputs | bit_to_mask {{ command }} movf outputs,w movwf main__380byte0 movf main__command,w movwf bit_to_mask__bit call bit_to_mask movf bit_to_mask__0return__byte,w iorwf main__380byte0,w ; 1 instructions found for sharing goto label378__1end label378__1false: ; else body start ; Bit Clear < Command = 0001 00 bb > : ; outputs := outputs & {{ bit_to_mask {{ command }} ^ io_mask }} movf outputs,w movwf main__383byte0 movf main__command,w movwf bit_to_mask__bit call bit_to_mask movf bit_to_mask__0return__byte,w xorlw 15 andwf main__383byte0,w ; 1 instructions found for sharing ; if exp=` command @ 2 ' generic label378__1end: ; Other expression=`{ command @ 2 }' delay=-1 ; 1 shared instructions follow movwf outputs ; if { command @ 2 } end goto switch__299end switch__299block386: ; Command = 0001 1 xxx : ; if { command @ 2 } start ; Alias variable for select command @ 2 main__command__388select0 equ main__command+0 main__command__388select0__byte equ main__command+0 main__command__388select0__bit equ 2 ; expression=`{ command @ 2 }' exp_delay=0 true_delay=-1 false_delay=6 true_size=15 false_size=8 btfss main__command__388select0__byte,main__command__388select0__bit goto label388__1false label388__1true: ; if { command @ 2 } body start ; Bit Read < Command = 0001 11 bb > : ; result := 0 clrf main__result ; if { outputs & bit_to_mask {{ command }} != 0 } start movf outputs,w movwf main__391byte0 movf main__command,w movwf bit_to_mask__bit call bit_to_mask movf bit_to_mask__0return__byte,w andwf main__391byte0,w ; expression=`{ outputs & bit_to_mask {{ command }} != 0 }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc z___byte,z___bit goto label391__1end ; if { outputs & bit_to_mask {{ command }} != 0 } body start ; result := 1 movlw 1 movwf main__result ; if { outputs & bit_to_mask {{ command }} != 0 } body end label391__1end: ; if exp=` outputs & bit_to_mask ## {{ command }} != 0 ' empty false ; Other expression=`{ outputs & bit_to_mask {{ command }} != 0 }' delay=-1 ; if { outputs & bit_to_mask {{ command }} != 0 } end ; call send_byte {{ result }} movf main__result,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { command @ 2 } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto label388__1end label388__1false: ; else body start ; Bit Toggle < Command = 0001 10 bb > : ; outputs := outputs ^ bit_to_mask {{ command }} movf outputs,w movwf main__397byte0 movf main__command,w movwf bit_to_mask__bit call bit_to_mask movf bit_to_mask__0return__byte,w xorwf main__397byte0,w movwf outputs ; else body end ; if exp=` command @ 2 ' generic label388__1end: ; Other expression=`{ command @ 2 }' delay=-1 ; if { command @ 2 } end goto switch__299end switch__299default400: ; Undefined commands ; do nothing : switch__299end: goto switch__296end switch__296block405: ; do nothing < Command = 01 xx xxxx > : goto switch__296end switch__296block408: ; Do nothing < Command = 10 xx xxxx > : goto switch__296end switch__296block411: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__413byte0 rrf main__413byte0,f rrf main__413byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 goto switch__413block_start switch__413block414: ; Command = 1100 xxxx or 1110 0 xxx : ; Do nothing : goto switch__413end switch__413block418: ; Read Interrupt Bits < Command = 1110 1111 > : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__420byte0 movlw 7 subwf main__420byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 btfss z___byte,z___bit goto label420__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits : ; result := 0 clrf main__result ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_enable__byte,interrupt_enable__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label423__0end ; if { interrupt_enable } body start ; result := result | 2 movlw 2 iorwf main__result,f ; if { interrupt_enable } body end label423__0end: ; if exp=`interrupt_enable' empty false ; Other expression=`{ interrupt_enable }' delay=-1 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_pending__byte,interrupt_pending__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label426__0end ; if { interrupt_pending } body start ; result := result | 1 movlw 1 iorwf main__result,f ; if { interrupt_pending } body end label426__0end: ; if exp=`interrupt_pending' empty false ; Other expression=`{ interrupt_pending }' delay=-1 ; if { interrupt_pending } end ; call send_byte {{ result }} movf main__result,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { {{ command & 7 }} = 7 } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label420__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__413end switch__413block432: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 goto switch__434block_start switch__434block435: ; Set interrupt bits < Command = 1111 10 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__437select0 equ main__command+0 main__command__437select0__byte equ main__command+0 main__command__437select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__437select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__437select0__byte,main__command__437select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__438select0 equ main__command+0 main__command__438select0__byte equ main__command+0 main__command__438select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__438select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__438select0__byte,main__command__438select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__434end switch__434block440: ; Set Interrupt Pending < Command = 1111 110 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__442select0 equ main__command+0 main__command__442select0__byte equ main__command+0 main__command__442select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__442select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__442select0__byte,main__command__442select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__434end switch__434block444: ; Set Interrupt Enable < Command = 1110 111 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__446select0 equ main__command+0 main__command__446select0__byte equ main__command+0 main__command__446select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__446select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__446select0__byte,main__command__446select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__434end: goto switch__413end switch__413block450: ; Shared commands < Command = 1111 1 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__452block_start switch__452block453: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 240 addwf osccal,f goto switch__452end switch__452block457: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 16 addwf osccal,f goto switch__452end switch__452block461: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__452end switch__452block465: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__452end switch__452block469: ; ID Next < Command = 1111 1100 > : ; if { id_index >= id . size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end ; call send_byte {{ id ~~ {{ id_index }} }} incf main__id_index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id movwf send_byte__char call send_byte ; id_index := id_index + 1 ; Switch from register bank 0 to register bank 1 (which contains main__id_index) bsf rp0___byte,rp0___bit ; Register bank is now 1 incf main__id_index,f ; if { id_index >= id_size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { id_index >= id_size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id_size } body end ; if exp=` id_index >= id_size ' false skip delay=4 ; Other expression=`{ id_index >= id_size }' delay=4 ; if { id_index >= id_size } end goto switch__452end switch__452block480: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf main__id_index goto switch__452end switch__452block484: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf main__glitch,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__452end switch__452block489: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf main__glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf main__glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__452end: switch__413end: switch__296end: goto main__291loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 23 bytes of 25 available bytes ; Register bank 1 used 8 bytes of 16 available bytes end