1 radix dec 2 0008 global__variables__bank0 equ 8 3 0030 global__variables__bank1 equ 48 4 0050 global__variables__bank2 equ 80 5 0070 global__variables__bank3 equ 112 6 001e global__bit__variables__bank0 equ 30 7 003e global__bit__variables__bank1 equ 62 8 0050 global__bit__variables__bank2 equ 80 9 0070 global__bit__variables__bank3 equ 112 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 17 0004 rp0___byte equ 4 18 0005 rp0___bit equ 5 19 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 20 0004 rp1___byte equ 4 21 0006 rp1___bit equ 6 22 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 23 0003 pa0___byte equ 3 24 0005 pa0___bit equ 5 25 0004 fsr___register equ 4 26 org 0 27 start: 28 ; Use oscillator calibration value already in register W 29 000 025 movwf 5 30 ; Initialize TRIS registers 31 001 cfe movlw 254 32 002 006 tris 6 33 003 cff movlw 255 34 004 007 tris 7 35 ; Switch from register bank 0 to register bank 1 36 005 5a4 bsf rp0___byte,rp0___bit 37 ; Register bank is now 1 38 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 39 006 5a3 bsf pa0___byte,pa0___bit 40 007 a58 goto main 41 ; comment ############################################################################# 42 ; comment {} 43 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich and Bill Benson} 44 ; comment {All rights reserved .} 45 ; comment {} 46 ; comment {Permission to use , copy , modify , distribute , and sell this software} 47 ; comment {for any purpose is hereby granted without fee provided that the above} 48 ; comment {copyright notice and this permission are retained . The author makes} 49 ; comment {no representations about the suitability of this software for any purpose .} 50 ; comment {It is provided { as is } without express or implied warranty .} 51 ; comment {} 52 ; comment {This is the code that implements the Out10 RoboBrick . Basically} 53 ; comment {it just waits for commands that come in at 2400 baud and responds} 54 ; comment {to them . See} 55 ; comment {} 56 ; comment {http : / / web . gramlich . net / projects / robobricks / inout10 / index . html} 57 ; comment {} 58 ; comment {for more details .} 59 ; comment {} 60 ; comment ############################################################################# 61 ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock 62 ; 4052=0xfd4 4095=0xfff 63 __config 4052 64 0fff configuration___address equ 4095 65 ; comment {Define processor constants :} 66 ; constant clock_rate 4000000 67 3d0900 clock_rate equ 4000000 68 ; constant clocks_per_instruction 4 69 0004 clocks_per_instruction equ 4 70 ; constant instruction_rate clock_rate / clocks_per_instruction 71 f4240 instruction_rate equ 1000000 72 ; comment {Define serial communication control constants :} 73 ; constant baud_rate 2400 74 0960 baud_rate equ 2400 75 ; constant instructions_per_bit instruction_rate / baud_rate 76 01a0 instructions_per_bit equ 416 77 ; constant delays_per_bit 3 78 0003 delays_per_bit equ 3 79 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 80 008a instructions_per_delay equ 138 81 ; constant extra_instructions_per_bit 9 82 0009 extra_instructions_per_bit equ 9 83 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 84 0003 extra_instructions_per_delay equ 3 85 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 86 0087 delay_instructions equ 135 87 ; comment {Register definitions :} 88 ; comment {Status register :} 89 0003 status equ 3 90 ; bind c status @ 0 91 0003 c equ status+0 92 0003 c__byte equ status+0 93 0000 c__bit equ 0 94 ; bind z status @ 2 95 0003 z equ status+0 96 0003 z__byte equ status+0 97 0002 z__bit equ 2 98 ; comment {OSCCAL register :} 99 0005 osccal equ 5 100 ; constant osccal_lsb 4 101 0004 osccal_lsb equ 4 102 ; comment {Define bit offsets :} 103 ; constant io0_bit 5 104 0005 io0_bit equ 5 105 ; constant io1_bit 4 106 0004 io1_bit equ 4 107 ; constant io2_bit 1 108 0001 io2_bit equ 1 109 ; constant io3_bit 2 110 0002 io3_bit equ 2 111 ; constant io4_bit 0 112 0000 io4_bit equ 0 113 ; constant io5_bit 1 114 0001 io5_bit equ 1 115 ; constant io6_bit 2 116 0002 io6_bit equ 2 117 ; constant io7_bit 3 118 0003 io7_bit equ 3 119 ; constant io8_bit 4 120 0004 io8_bit equ 4 121 ; constant io9_bit 5 122 0005 io9_bit equ 5 123 ; constant serial_out_bit 0 124 0000 serial_out_bit equ 0 125 ; constant serial_in_bit 3 126 0003 serial_in_bit equ 3 127 ; comment {Define pin assignments and directions :} 128 ; comment {Techically , the pins are all read_write_manual , but it} 129 ; comment {is easier to do all of the tris register manipulation} 130 ; comment {by hand rather than using uCL { direction } commands . We} 131 ; comment {start with all the I / O pins set to read - only until such} 132 ; comment {time as the user explicitly sets them to outputs :} 133 0006 portb equ 6 134 0007 portc equ 7 135 0007 io9__byte equ 7 136 0005 io9__bit equ 5 137 0007 io8__byte equ 7 138 0004 io8__bit equ 4 139 0007 io7__byte equ 7 140 0003 io7__bit equ 3 141 0007 io6__byte equ 7 142 0002 io6__bit equ 2 143 0007 io5__byte equ 7 144 0001 io5__bit equ 1 145 0007 io4__byte equ 7 146 0000 io4__bit equ 0 147 0006 io3__byte equ 6 148 0002 io3__bit equ 2 149 0006 io2__byte equ 6 150 0001 io2__bit equ 1 151 0006 io1__byte equ 6 152 0004 io1__bit equ 4 153 0006 io0__byte equ 6 154 0005 io0__bit equ 5 155 0006 serial_out__byte equ 6 156 0000 serial_out__bit equ 0 157 0006 serial_in__byte equ 6 158 0003 serial_in__bit equ 3 159 ; constant mask 0x1f 160 001f mask equ 31 161 ; string_constants Start 162 ; Switch from register bank 1 to register bank 0 163 008 4a4 bcf rp0___byte,rp0___bit 164 ; Register bank is now 0 165 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 166 009 4a3 bcf pa0___byte,pa0___bit 167 string___fetch: 168 00a 022 movwf pcl___register 169 ; id = 1 , 0 , 13 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 8 , 0s'InOut10C' , 15 , 0s'Gramlich&Benson' 170 0000 id___string equ 0 171 id: 172 00b 1e2 addwf pcl___register,f 173 ; Length = 49 174 00c 831 retlw 49 175 ; 1 176 00d 801 retlw 1 177 ; 0 178 00e 800 retlw 0 179 ; 13 180 00f 80d retlw 13 181 ; 1 182 010 801 retlw 1 183 ; 0 184 011 800 retlw 0 185 ; 0 186 012 800 retlw 0 187 ; 0 188 013 800 retlw 0 189 ; 0 190 014 800 retlw 0 191 ; 0r'16' 192 015 80c retlw 12 ; random number 193 016 877 retlw 119 ; random number 194 017 8f7 retlw 247 ; random number 195 018 869 retlw 105 ; random number 196 019 8f7 retlw 247 ; random number 197 01a 808 retlw 8 ; random number 198 01b 8c2 retlw 194 ; random number 199 01c 818 retlw 24 ; random number 200 01d 889 retlw 137 ; random number 201 01e 8cb retlw 203 ; random number 202 01f 890 retlw 144 ; random number 203 020 8c9 retlw 201 ; random number 204 021 8ad retlw 173 ; random number 205 022 87f retlw 127 ; random number 206 023 8f7 retlw 247 ; random number 207 024 831 retlw 49 ; random number 208 ; 8 209 025 808 retlw 8 210 ; `InOut10C' 211 026 849 retlw 73 212 027 86e retlw 110 213 028 84f retlw 79 214 029 875 retlw 117 215 02a 874 retlw 116 216 02b 831 retlw 49 217 02c 830 retlw 48 218 02d 843 retlw 67 219 ; 15 220 02e 80f retlw 15 221 ; `Gramlich&Benson' 222 02f 847 retlw 71 223 030 872 retlw 114 224 031 861 retlw 97 225 032 86d retlw 109 226 033 86c retlw 108 227 034 869 retlw 105 228 035 863 retlw 99 229 036 868 retlw 104 230 037 826 retlw 38 231 038 842 retlw 66 232 039 865 retlw 101 233 03a 86e retlw 110 234 03b 873 retlw 115 235 03c 86f retlw 111 236 03d 86e retlw 110 237 ; string__constants End 238 ; comment {Some globals : byte} 239 0008 raw_low equ global__variables__bank0+0 240 0009 raw_high equ global__variables__bank0+1 241 000a inputs_low equ global__variables__bank0+2 242 000b inputs_high equ global__variables__bank0+3 243 000c outputs_low equ global__variables__bank0+4 244 000d outputs_high equ global__variables__bank0+5 245 000e complement_low equ global__variables__bank0+6 246 000f complement_high equ global__variables__bank0+7 247 0010 low_low equ global__variables__bank0+8 248 0011 low_high equ global__variables__bank0+9 249 0012 high_low equ global__variables__bank0+10 250 0013 high_high equ global__variables__bank0+11 251 0014 raising_low equ global__variables__bank0+12 252 0015 raising_high equ global__variables__bank0+13 253 0016 falling_low equ global__variables__bank0+14 254 0017 falling_high equ global__variables__bank0+15 255 0018 temporary equ global__variables__bank0+16 256 001e interrupt_enable equ global__bit__variables__bank0+0 257 001e interrupt_enable__byte equ global__bit__variables__bank0+0 258 0000 interrupt_enable__bit equ 0 259 001e interrupt_pending equ global__bit__variables__bank0+0 260 001e interrupt_pending__byte equ global__bit__variables__bank0+0 261 0001 interrupt_pending__bit equ 1 262 001e receiving equ global__bit__variables__bank0+0 263 001e receiving__byte equ global__bit__variables__bank0+0 264 0002 receiving__bit equ 2 265 ; bank 1 266 ; Default register bank is now 1 267 0030 direction_low equ global__variables__bank1+0 268 0031 direction_high equ global__variables__bank1+1 269 0032 glitch equ global__variables__bank1+2 270 0033 index equ global__variables__bank1+3 271 ; comment {Note that the 12 - bit PIC ' s only have a 2 - level deep stack .} 272 ; comment {The code starts in the main procedure < located at the end of this code >} 273 ; comment {The next level of procedure call is either get_byte or send_byte .} 274 ; comment {Lastly , the lowest level of procedure call is delay . It all fits ,} 275 ; comment {but just barely .} 276 277 ; procedure get_byte start 278 get_byte: 279 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 280 ; Procedure must be called with PCLATH set to code bank 0 281 0034 get_byte__variables__base equ global__variables__bank1+4 282 0034 get_byte__bytes__base equ get_byte__variables__base+0 283 0037 get_byte__bits__base equ get_byte__variables__base+3 284 0003 get_byte__total__bytes equ 3 285 ; arguments_none 286 0034 get_byte__0return__byte equ get_byte__bytes__base+0 287 ; This procedure will wait for a byte to be received from 288 ; serial_in_bit . It calls the delay procedure for all delays . 289 0035 get_byte__count equ get_byte__bytes__base+1 290 0036 get_byte__char equ get_byte__bytes__base+2 291 ; Why does the delay procedure wait for a third of bit ? Well , it 292 ; has to do with the loop immediately below . If we catch the 293 ; start bit at the beginning of a 1 / 3 bit time , we will be 294 ; sampling data at approximately 1 / 3 of the way into each bit . 295 ; Conversely , if we catch the start near the end of a 1 / 3 bit 296 ; bit time , we will be sampling data at approximately 2 / 3 of the 297 ; way into each bit . So , what this means is that our bit sample 298 ; times will be somewhere between 1 / 3 and 2 / 3 of bit < i . e . in 299 ; the middle of the bit . 300 ; It would be nice to tweak the code to shorter delay times 301 ; < 1 / 4 bit , 1 / 5 bit , etc . > but then it gets too hard to get 302 ; the bookeeping done in the delay routine . A 12 - bit PIC 303 ; running at 4 MHz <= 1 MIPS > , only has 138 instructions available 304 ; for the delay routine when at 1 / 3 of bit . 305 ; Wait for a start bit : 306 ; receiving := 1 307 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 308 03e 4a4 bcf rp0___byte,rp0___bit 309 ; Register bank is now 0 310 03f 55e bsf receiving__byte,receiving__bit 311 ; `while serial_in ...' start 312 ; Switch from register bank 0 to register bank 1 313 040 5a4 bsf rp0___byte,rp0___bit 314 ; Register bank is now 1 315 get_byte__155while__continue: 316 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 317 041 766 btfss serial_in__byte,serial_in__bit 318 042 a47 goto get_byte__155while__break 319 ; call delay {{ }} 320 ; Switch from register bank 1 to register bank 0 321 043 4a4 bcf rp0___byte,rp0___bit 322 ; Register bank is now 0 323 044 9d5 call delay 324 ; Switch from register bank 0 to register bank 1 325 045 5a4 bsf rp0___byte,rp0___bit 326 ; Register bank is now 1 327 046 a41 goto get_byte__155while__continue 328 ; if exp=`serial_in' false goto 329 ; Other expression=`serial_in' delay=-1 330 get_byte__155while__break: 331 ; `while serial_in ...' end 332 ; Clear interrupt : 333 ; 1 cycle : 334 ; serial_out := 1 335 047 506 bsf serial_out__byte,serial_out__bit 336 ; Skip over start bit : 337 ; call delay {{ }} 338 ; Switch from register bank 1 to register bank 0 339 048 4a4 bcf rp0___byte,rp0___bit 340 ; Register bank is now 0 341 049 9d5 call delay 342 ; call delay {{ }} 343 04a 9d5 call delay 344 ; call delay {{ }} 345 04b 9d5 call delay 346 ; Sample in the middle third of each data bit ; 347 ; 1 cycle : 348 ; char := 0 349 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 350 04c 5a4 bsf rp0___byte,rp0___bit 351 ; Register bank is now 1 352 04d 076 clrf get_byte__char 353 ; 2 cycles to set up loop : 354 ; 1 + 1 + 2 = 4 355 ; nop extra_instructions_per_bit - 4 356 ; Delay 5 cycles 357 04e 000 nop 358 04f 000 nop 359 050 000 nop 360 051 000 nop 361 052 000 nop 362 ; `count_down count 8 ...' start 363 053 c08 movlw 8 364 054 035 movwf get_byte__count 365 get_byte__174_loop: 366 ; call delay {{ }} 367 ; Switch from register bank 1 to register bank 0 368 055 4a4 bcf rp0___byte,rp0___bit 369 ; Register bank is now 0 370 056 9d5 call delay 371 ; 2 cycles : 372 ; char := char >> 1 373 057 403 bcf c___byte,c___bit 374 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 375 058 5a4 bsf rp0___byte,rp0___bit 376 ; Register bank is now 1 377 059 336 rrf get_byte__char,f 378 ; 2 cycles : 379 ; if { serial_in } start 380 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 381 05a 666 btfsc serial_in__byte,serial_in__bit 382 ; if { serial_in } body start 383 ; char @ 7 := 1 384 ; Select char @ 7 385 0036 get_byte__char__180select0 equ get_byte__char+0 386 0036 get_byte__char__180select0__byte equ get_byte__char+0 387 0007 get_byte__char__180select0__bit equ 7 388 05b 5f6 bsf get_byte__char__180select0__byte,get_byte__char__180select0__bit 389 ; if { serial_in } body end 390 ; if exp=`serial_in' false skip delay=2 391 ; Other expression=`{ serial_in }' delay=2 392 ; if { serial_in } end 393 ; call delay {{ }} 394 ; Switch from register bank 1 to register bank 0 395 05c 4a4 bcf rp0___byte,rp0___bit 396 ; Register bank is now 0 397 05d 9d5 call delay 398 ; call delay {{ }} 399 05e 9d5 call delay 400 ; 3 cycles at end of loop : 401 ; 2 + 2 + 3 = 7 402 ; nop extra_instructions_per_bit - 7 403 ; Delay 2 cycles 404 05f 000 nop 405 060 000 nop 406 ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) 407 061 5a4 bsf rp0___byte,rp0___bit 408 ; Register bank is now 1 409 062 2f5 decfsz get_byte__count,f 410 063 a55 goto get_byte__174_loop 411 get_byte__174_done: 412 ; `count_down count 8 ...' end 413 ; Skip over 2 / 3 ' s of stop bit : 414 ; call delay {{ }} 415 ; Switch from register bank 1 to register bank 0 416 064 4a4 bcf rp0___byte,rp0___bit 417 ; Register bank is now 0 418 065 9d5 call delay 419 ; call delay {{ }} 420 066 9d5 call delay 421 ; return char 422 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 423 067 5a4 bsf rp0___byte,rp0___bit 424 ; Register bank is now 1 425 068 216 movf get_byte__char,w 426 069 034 movwf get_byte__0return__byte 427 06a 800 retlw 0 428 ; procedure get_byte end 429 430 ; procedure send_byte start 431 send_byte: 432 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 433 ; Procedure must be called with PCLATH set to code bank 0 434 0037 send_byte__variables__base equ global__variables__bank1+7 435 0037 send_byte__bytes__base equ send_byte__variables__base+0 436 0039 send_byte__bits__base equ send_byte__variables__base+2 437 0002 send_byte__total__bytes equ 2 438 0037 send_byte__char equ send_byte__bytes__base+0 439 ; Send < char > to < tx > : 440 0038 send_byte__count equ send_byte__bytes__base+1 441 ; < receiving > will be 1 if the last get / put routine was a get . 442 ; Before we start transmitting a response back , we want to ensure 443 ; that there has been enough time to turn the line around . 444 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 445 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 446 ; for good measure . Technically , the second call to delay < > 447 ; is not really needed . 448 ; if { receiving } start 449 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 450 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 451 06b 4a4 bcf rp0___byte,rp0___bit 452 ; Register bank is now 0 453 06c 443 bcf z___byte,z___bit 454 06d 65e btfsc receiving__byte,receiving__bit 455 06e 543 bsf z___byte,z___bit 456 ; Switch from register bank 0 to register bank 1 457 06f 5a4 bsf rp0___byte,rp0___bit 458 ; Register bank is now 1 459 070 743 btfss z___byte,z___bit 460 071 a77 goto label210__0end 461 ; if { receiving } body start 462 ; receiving := 0 463 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 464 072 4a4 bcf rp0___byte,rp0___bit 465 ; Register bank is now 0 466 073 45e bcf receiving__byte,receiving__bit 467 ; call delay {{ }} 468 074 9d5 call delay 469 ; call delay {{ }} 470 075 9d5 call delay 471 ; if { receiving } body end 472 ; Switch from register bank 0 to register bank 1 473 076 5a4 bsf rp0___byte,rp0___bit 474 ; Register bank is now 1 475 label210__0end: 476 ; if exp=`receiving' empty false 477 ; Other expression=`{ receiving }' delay=-1 478 ; if { receiving } end 479 ; Send the start bit : 480 ; 1 cycle : 481 ; serial_out := 0 482 077 406 bcf serial_out__byte,serial_out__bit 483 ; call delay {{ }} 484 ; Switch from register bank 1 to register bank 0 485 078 4a4 bcf rp0___byte,rp0___bit 486 ; Register bank is now 0 487 079 9d5 call delay 488 ; call delay {{ }} 489 07a 9d5 call delay 490 ; call delay {{ }} 491 07b 9d5 call delay 492 ; 2 cycles to set up loop : 493 ; 1 + 2 = 3 494 ; nop extra_instructions_per_bit - 3 495 ; Delay 6 cycles 496 07c 000 nop 497 07d 000 nop 498 07e 000 nop 499 07f 000 nop 500 080 000 nop 501 081 000 nop 502 ; Send the data : 503 ; `count_down count 8 ...' start 504 082 c08 movlw 8 505 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 506 083 5a4 bsf rp0___byte,rp0___bit 507 ; Register bank is now 1 508 084 038 movwf send_byte__count 509 send_byte__228_loop: 510 ; 4 cycles : 511 ; serial_out := char @ 0 512 ; Alias variable for select char @ 0 513 0037 send_byte__char__230select0 equ send_byte__char+0 514 0037 send_byte__char__230select0__byte equ send_byte__char+0 515 0000 send_byte__char__230select0__bit equ 0 516 085 717 btfss send_byte__char__230select0__byte,send_byte__char__230select0__bit 517 086 406 bcf serial_out__byte,serial_out__bit 518 087 617 btfsc send_byte__char__230select0__byte,send_byte__char__230select0__bit 519 088 506 bsf serial_out__byte,serial_out__bit 520 ; 2 cycles : 521 ; char := char >> 1 522 089 403 bcf c___byte,c___bit 523 08a 337 rrf send_byte__char,f 524 ; call delay {{ }} 525 ; Switch from register bank 1 to register bank 0 526 08b 4a4 bcf rp0___byte,rp0___bit 527 ; Register bank is now 0 528 08c 9d5 call delay 529 ; call delay {{ }} 530 08d 9d5 call delay 531 ; call delay {{ }} 532 08e 9d5 call delay 533 ; 3 cycles at end of loop : 534 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 535 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 536 08f 5a4 bsf rp0___byte,rp0___bit 537 ; Register bank is now 1 538 090 2f8 decfsz send_byte__count,f 539 091 a85 goto send_byte__228_loop 540 send_byte__228_done: 541 ; `count_down count 8 ...' end 542 ; Send the stop bit : 543 ; nop 1 544 ; Delay 1 cycles 545 092 000 nop 546 ; 1 cycle 547 ; serial_out := 1 548 093 506 bsf serial_out__byte,serial_out__bit 549 ; call delay {{ }} 550 ; Switch from register bank 1 to register bank 0 551 094 4a4 bcf rp0___byte,rp0___bit 552 ; Register bank is now 0 553 095 9d5 call delay 554 ; call delay {{ }} 555 096 9d5 call delay 556 ; call delay {{ }} 557 097 9d5 call delay 558 ; 2 cycles for call / return 559 ; 2 cycles for argument 560 ; 1 + 2 + 2 = 5 561 ; nop extra_instructions_per_bit - 5 562 ; Delay 4 cycles 563 098 000 nop 564 099 000 nop 565 09a 000 nop 566 09b 000 nop 567 ; procedure send_byte end 568 ; Switch from register bank 0 to register bank 1 569 09c 5a4 bsf rp0___byte,rp0___bit 570 ; Register bank is now 1 571 09d 800 retlw 0 572 ; bank 1 573 ; Default register bank is now 1 574 575 ; procedure direction_set start 576 direction_set: 577 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 578 ; Procedure must be called with PCLATH set to code bank 0 579 0039 direction_set__variables__base equ global__variables__bank1+9 580 0039 direction_set__bytes__base equ direction_set__variables__base+0 581 003a direction_set__bits__base equ direction_set__variables__base+1 582 0001 direction_set__total__bytes equ 1 583 ; arguments_none 584 ; This procedure will set the direction appropriately . 585 0039 direction_set__temp equ direction_set__bytes__base+0 586 ; Deal with port C : 587 ; temp := 0 588 09e 079 clrf direction_set__temp 589 ; RC0 = IO4 : 590 ; if { direction_low @ 4 } start 591 ; Alias variable for select direction_low @ 4 592 0030 direction_low__266select0 equ direction_low+0 593 0030 direction_low__266select0__byte equ direction_low+0 594 0004 direction_low__266select0__bit equ 4 595 ; expression=`{ direction_low @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 596 09f 690 btfsc direction_low__266select0__byte,direction_low__266select0__bit 597 ; if { direction_low @ 4 } body start 598 ; temp @ 0 := 1 599 ; Select temp @ 0 600 0039 direction_set__temp__267select0 equ direction_set__temp+0 601 0039 direction_set__temp__267select0__byte equ direction_set__temp+0 602 0000 direction_set__temp__267select0__bit equ 0 603 0a0 519 bsf direction_set__temp__267select0__byte,direction_set__temp__267select0__bit 604 ; if { direction_low @ 4 } body end 605 ; if exp=` direction_low @ 4 ' false skip delay=2 606 ; Other expression=`{ direction_low @ 4 }' delay=2 607 ; if { direction_low @ 4 } end 608 ; RC1 = IO5 : 609 ; if { direction_high @ 0 } start 610 ; Alias variable for select direction_high @ 0 611 0031 direction_high__270select0 equ direction_high+0 612 0031 direction_high__270select0__byte equ direction_high+0 613 0000 direction_high__270select0__bit equ 0 614 ; expression=`{ direction_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 615 0a1 611 btfsc direction_high__270select0__byte,direction_high__270select0__bit 616 ; if { direction_high @ 0 } body start 617 ; temp @ 1 := 1 618 ; Select temp @ 1 619 0039 direction_set__temp__271select0 equ direction_set__temp+0 620 0039 direction_set__temp__271select0__byte equ direction_set__temp+0 621 0001 direction_set__temp__271select0__bit equ 1 622 0a2 539 bsf direction_set__temp__271select0__byte,direction_set__temp__271select0__bit 623 ; if { direction_high @ 0 } body end 624 ; if exp=` direction_high @ 0 ' false skip delay=2 625 ; Other expression=`{ direction_high @ 0 }' delay=2 626 ; if { direction_high @ 0 } end 627 ; RC2 = IO6 : 628 ; if { direction_high @ 1 } start 629 ; Alias variable for select direction_high @ 1 630 0031 direction_high__274select0 equ direction_high+0 631 0031 direction_high__274select0__byte equ direction_high+0 632 0001 direction_high__274select0__bit equ 1 633 ; expression=`{ direction_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 634 0a3 631 btfsc direction_high__274select0__byte,direction_high__274select0__bit 635 ; if { direction_high @ 1 } body start 636 ; temp @ 2 := 1 637 ; Select temp @ 2 638 0039 direction_set__temp__275select0 equ direction_set__temp+0 639 0039 direction_set__temp__275select0__byte equ direction_set__temp+0 640 0002 direction_set__temp__275select0__bit equ 2 641 0a4 559 bsf direction_set__temp__275select0__byte,direction_set__temp__275select0__bit 642 ; if { direction_high @ 1 } body end 643 ; if exp=` direction_high @ 1 ' false skip delay=2 644 ; Other expression=`{ direction_high @ 1 }' delay=2 645 ; if { direction_high @ 1 } end 646 ; RC3 = IO7 : 647 ; if { direction_high @ 2 } start 648 ; Alias variable for select direction_high @ 2 649 0031 direction_high__278select0 equ direction_high+0 650 0031 direction_high__278select0__byte equ direction_high+0 651 0002 direction_high__278select0__bit equ 2 652 ; expression=`{ direction_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 653 0a5 651 btfsc direction_high__278select0__byte,direction_high__278select0__bit 654 ; if { direction_high @ 2 } body start 655 ; temp @ 3 := 1 656 ; Select temp @ 3 657 0039 direction_set__temp__279select0 equ direction_set__temp+0 658 0039 direction_set__temp__279select0__byte equ direction_set__temp+0 659 0003 direction_set__temp__279select0__bit equ 3 660 0a6 579 bsf direction_set__temp__279select0__byte,direction_set__temp__279select0__bit 661 ; if { direction_high @ 2 } body end 662 ; if exp=` direction_high @ 2 ' false skip delay=2 663 ; Other expression=`{ direction_high @ 2 }' delay=2 664 ; if { direction_high @ 2 } end 665 ; RC4 = IO8 : 666 ; if { direction_high @ 3 } start 667 ; Alias variable for select direction_high @ 3 668 0031 direction_high__282select0 equ direction_high+0 669 0031 direction_high__282select0__byte equ direction_high+0 670 0003 direction_high__282select0__bit equ 3 671 ; expression=`{ direction_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 672 0a7 671 btfsc direction_high__282select0__byte,direction_high__282select0__bit 673 ; if { direction_high @ 3 } body start 674 ; temp @ 4 := 1 675 ; Select temp @ 4 676 0039 direction_set__temp__283select0 equ direction_set__temp+0 677 0039 direction_set__temp__283select0__byte equ direction_set__temp+0 678 0004 direction_set__temp__283select0__bit equ 4 679 0a8 599 bsf direction_set__temp__283select0__byte,direction_set__temp__283select0__bit 680 ; if { direction_high @ 3 } body end 681 ; if exp=` direction_high @ 3 ' false skip delay=2 682 ; Other expression=`{ direction_high @ 3 }' delay=2 683 ; if { direction_high @ 3 } end 684 ; RC5 = IO9 : 685 ; if { direction_high @ 4 } start 686 ; Alias variable for select direction_high @ 4 687 0031 direction_high__286select0 equ direction_high+0 688 0031 direction_high__286select0__byte equ direction_high+0 689 0004 direction_high__286select0__bit equ 4 690 ; expression=`{ direction_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 691 0a9 691 btfsc direction_high__286select0__byte,direction_high__286select0__bit 692 ; if { direction_high @ 4 } body start 693 ; temp @ 5 := 1 694 ; Select temp @ 5 695 0039 direction_set__temp__287select0 equ direction_set__temp+0 696 0039 direction_set__temp__287select0__byte equ direction_set__temp+0 697 0005 direction_set__temp__287select0__bit equ 5 698 0aa 5b9 bsf direction_set__temp__287select0__byte,direction_set__temp__287select0__bit 699 ; if { direction_high @ 4 } body end 700 ; if exp=` direction_high @ 4 ' false skip delay=2 701 ; Other expression=`{ direction_high @ 4 }' delay=2 702 ; if { direction_high @ 4 } end 703 ; inline assembly statements begin 704 0ab 219 movf direction_set__temp,w 705 0ac 007 tris 7 706 ; inline assembly statements end 707 ; Deal with port B : 708 ; temp := 0 709 0ad 079 clrf direction_set__temp 710 ; RB0 = SOUT : 711 ; RB1 = IO2 : 712 ; if { direction_low @ 2 } start 713 ; Alias variable for select direction_low @ 2 714 0030 direction_low__298select0 equ direction_low+0 715 0030 direction_low__298select0__byte equ direction_low+0 716 0002 direction_low__298select0__bit equ 2 717 ; expression=`{ direction_low @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 718 0ae 650 btfsc direction_low__298select0__byte,direction_low__298select0__bit 719 ; if { direction_low @ 2 } body start 720 ; temp @ 1 := 1 721 ; Select temp @ 1 722 0039 direction_set__temp__299select0 equ direction_set__temp+0 723 0039 direction_set__temp__299select0__byte equ direction_set__temp+0 724 0001 direction_set__temp__299select0__bit equ 1 725 0af 539 bsf direction_set__temp__299select0__byte,direction_set__temp__299select0__bit 726 ; if { direction_low @ 2 } body end 727 ; if exp=` direction_low @ 2 ' false skip delay=2 728 ; Other expression=`{ direction_low @ 2 }' delay=2 729 ; if { direction_low @ 2 } end 730 ; RB2 = IO3 : 731 ; if { direction_low @ 3 } start 732 ; Alias variable for select direction_low @ 3 733 0030 direction_low__302select0 equ direction_low+0 734 0030 direction_low__302select0__byte equ direction_low+0 735 0003 direction_low__302select0__bit equ 3 736 ; expression=`{ direction_low @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 737 0b0 670 btfsc direction_low__302select0__byte,direction_low__302select0__bit 738 ; if { direction_low @ 3 } body start 739 ; temp @ 2 := 1 740 ; Select temp @ 2 741 0039 direction_set__temp__303select0 equ direction_set__temp+0 742 0039 direction_set__temp__303select0__byte equ direction_set__temp+0 743 0002 direction_set__temp__303select0__bit equ 2 744 0b1 559 bsf direction_set__temp__303select0__byte,direction_set__temp__303select0__bit 745 ; if { direction_low @ 3 } body end 746 ; if exp=` direction_low @ 3 ' false skip delay=2 747 ; Other expression=`{ direction_low @ 3 }' delay=2 748 ; if { direction_low @ 3 } end 749 ; RB3 = SIN : 750 ; temp @ 3 := 1 751 ; Select temp @ 3 752 0039 direction_set__temp__306select0 equ direction_set__temp+0 753 0039 direction_set__temp__306select0__byte equ direction_set__temp+0 754 0003 direction_set__temp__306select0__bit equ 3 755 0b2 579 bsf direction_set__temp__306select0__byte,direction_set__temp__306select0__bit 756 ; RB4 = IO1 : 757 ; if { direction_low @ 1 } start 758 ; Alias variable for select direction_low @ 1 759 0030 direction_low__308select0 equ direction_low+0 760 0030 direction_low__308select0__byte equ direction_low+0 761 0001 direction_low__308select0__bit equ 1 762 ; expression=`{ direction_low @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 763 0b3 630 btfsc direction_low__308select0__byte,direction_low__308select0__bit 764 ; if { direction_low @ 1 } body start 765 ; temp @ 4 := 1 766 ; Select temp @ 4 767 0039 direction_set__temp__309select0 equ direction_set__temp+0 768 0039 direction_set__temp__309select0__byte equ direction_set__temp+0 769 0004 direction_set__temp__309select0__bit equ 4 770 0b4 599 bsf direction_set__temp__309select0__byte,direction_set__temp__309select0__bit 771 ; if { direction_low @ 1 } body end 772 ; if exp=` direction_low @ 1 ' false skip delay=2 773 ; Other expression=`{ direction_low @ 1 }' delay=2 774 ; if { direction_low @ 1 } end 775 ; RB5 = IO0 : 776 ; if { direction_low @ 0 } start 777 ; Alias variable for select direction_low @ 0 778 0030 direction_low__312select0 equ direction_low+0 779 0030 direction_low__312select0__byte equ direction_low+0 780 0000 direction_low__312select0__bit equ 0 781 ; expression=`{ direction_low @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 782 0b5 610 btfsc direction_low__312select0__byte,direction_low__312select0__bit 783 ; if { direction_low @ 0 } body start 784 ; temp @ 5 := 1 785 ; Select temp @ 5 786 0039 direction_set__temp__313select0 equ direction_set__temp+0 787 0039 direction_set__temp__313select0__byte equ direction_set__temp+0 788 0005 direction_set__temp__313select0__bit equ 5 789 0b6 5b9 bsf direction_set__temp__313select0__byte,direction_set__temp__313select0__bit 790 ; if { direction_low @ 0 } body end 791 ; if exp=` direction_low @ 0 ' false skip delay=2 792 ; Other expression=`{ direction_low @ 0 }' delay=2 793 ; if { direction_low @ 0 } end 794 ; inline assembly statements begin 795 0b7 219 movf direction_set__temp,w 796 0b8 006 tris 6 797 ; inline assembly statements end 798 ; procedure direction_set end 799 0b9 800 retlw 0 800 801 ; procedure reset start 802 reset: 803 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 804 ; Procedure must be called with PCLATH set to code bank 0 805 003a reset__variables__base equ global__variables__bank1+10 806 003a reset__bytes__base equ reset__variables__base+0 807 003a reset__bits__base equ reset__variables__base+0 808 0000 reset__total__bytes equ 0 809 ; arguments_none 810 ; This procedure will initialize all global registers : 811 ; Initialize global registers : 812 ; inputs_low := 0 813 0ba 06a clrf inputs_low 814 ; inputs_high := 0 815 0bb 06b clrf inputs_high 816 ; raw_low := 0 817 0bc 068 clrf raw_low 818 ; raw_high := 0 819 0bd 069 clrf raw_high 820 ; outputs_low := 0 821 0be 06c clrf outputs_low 822 ; outputs_high := 0 823 0bf 06d clrf outputs_high 824 ; complement_low := 0 825 0c0 06e clrf complement_low 826 ; complement_high := 0 827 0c1 06f clrf complement_high 828 ; direction_low := mask 829 0c2 c1f movlw 31 830 0c3 030 movwf direction_low 831 ; direction_high := mask 832 0c4 c1f movlw 31 833 0c5 031 movwf direction_high 834 ; low_low := 0 835 ; Switch from register bank 1 to register bank 0 (which contains low_low) 836 0c6 4a4 bcf rp0___byte,rp0___bit 837 ; Register bank is now 0 838 0c7 070 clrf low_low 839 ; low_high := 0 840 0c8 071 clrf low_high 841 ; high_low := 0 842 0c9 072 clrf high_low 843 ; high_high := 0 844 0ca 073 clrf high_high 845 ; raising_low := 0 846 0cb 074 clrf raising_low 847 ; raising_high := 0 848 0cc 075 clrf raising_high 849 ; falling_low := 0 850 0cd 076 clrf falling_low 851 ; falling_high := 0 852 0ce 077 clrf falling_high 853 ; interrupt_enable := 0 854 0cf 41e bcf interrupt_enable__byte,interrupt_enable__bit 855 ; interrupt_pending := 0 856 0d0 43e bcf interrupt_pending__byte,interrupt_pending__bit 857 ; Initialize remaining registers : 858 ; glitch := 0 859 ; Switch from register bank 0 to register bank 1 (which contains glitch) 860 0d1 5a4 bsf rp0___byte,rp0___bit 861 ; Register bank is now 1 862 0d2 072 clrf glitch 863 ; index := 0 864 0d3 073 clrf index 865 ; procedure reset end 866 0d4 800 retlw 0 867 ; bank 0 868 ; Default register bank is now 0 869 870 ; procedure delay start 871 ; optimize 0 872 delay: 873 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 874 ; Procedure must be called with PCLATH set to code bank 0 875 0019 delay__variables__base equ global__variables__bank0+17 876 0019 delay__bytes__base equ delay__variables__base+0 877 001d delay__bits__base equ delay__variables__base+4 878 0005 delay__total__bytes equ 5 879 001c delay__356byte1 equ delay__bytes__base+3 880 001c delay__480byte0 equ delay__bytes__base+3 881 001c delay__479byte0 equ delay__bytes__base+3 882 ; arguments_none 883 ; uniform_delay delay_instructions 884 ; Uniform delay remaining = 131 Accumulated Delay = 0 885 ; Uniform delay remaining = 131 Accumulated Delay = 0 886 ; This procedure delays 1 / 3 of a bit . 887 ; Uniform delay remaining = 131 Accumulated Delay = 0 888 ; Uniform delay remaining = 131 Accumulated Delay = 0 889 0019 delay__previous_low equ delay__bytes__base+0 890 ; Uniform delay remaining = 131 Accumulated Delay = 0 891 001a delay__previous_high equ delay__bytes__base+1 892 ; Uniform delay remaining = 131 Accumulated Delay = 0 893 001b delay__temp equ delay__bytes__base+2 894 ; Uniform delay remaining = 131 Accumulated Delay = 0 895 ; Uniform delay remaining = 131 Accumulated Delay = 0 896 ; Kick the dog : 897 ; Uniform delay remaining = 131 Accumulated Delay = 0 898 ; watch_dog_reset 899 0d5 004 clrwdt 900 ; Uniform delay remaining = 130 Accumulated Delay = 1 901 ; Uniform delay remaining = 130 Accumulated Delay = 1 902 ; Set the port C outputs first : 903 ; Uniform delay remaining = 130 Accumulated Delay = 1 904 ; temp := 0 905 0d6 07b clrf delay__temp 906 ; Uniform delay remaining = 129 Accumulated Delay = 2 907 ; Uniform delay remaining = 129 Accumulated Delay = 2 908 ; RC0 = IO4 : 909 ; Uniform delay remaining = 129 Accumulated Delay = 2 910 ; if { outputs_low @ 4 } start 911 ; Alias variable for select outputs_low @ 4 912 000c outputs_low__374select0 equ outputs_low+0 913 000c outputs_low__374select0__byte equ outputs_low+0 914 0004 outputs_low__374select0__bit equ 4 915 ; expression=`{ outputs_low @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 916 0d7 68c btfsc outputs_low__374select0__byte,outputs_low__374select0__bit 917 ; if { outputs_low @ 4 } body start 918 ; Uniform delay remaining = 129 Accumulated Delay = 0 919 ; temp @ 0 := 1 920 ; Select temp @ 0 921 001b delay__temp__375select0 equ delay__temp+0 922 001b delay__temp__375select0__byte equ delay__temp+0 923 0000 delay__temp__375select0__bit equ 0 924 0d8 51b bsf delay__temp__375select0__byte,delay__temp__375select0__bit 925 ; Uniform delay remaining = 128 Accumulated Delay = 1 926 ; Uniform delay remaining = 128 Accumulated Delay = 1 927 ; if { outputs_low @ 4 } body end 928 ; if exp=` outputs_low @ 4 ' false skip delay=2 929 ; Other expression=`{ outputs_low @ 4 }' delay=2 930 ; if { outputs_low @ 4 } end 931 ; Uniform delay remaining = 127 Accumulated Delay = 4 932 ; RC1 = IO5 : 933 ; Uniform delay remaining = 127 Accumulated Delay = 4 934 ; if { outputs_high @ 0 } start 935 ; Alias variable for select outputs_high @ 0 936 000d outputs_high__378select0 equ outputs_high+0 937 000d outputs_high__378select0__byte equ outputs_high+0 938 0000 outputs_high__378select0__bit equ 0 939 ; expression=`{ outputs_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 940 0d9 60d btfsc outputs_high__378select0__byte,outputs_high__378select0__bit 941 ; if { outputs_high @ 0 } body start 942 ; Uniform delay remaining = 127 Accumulated Delay = 0 943 ; temp @ 1 := 1 944 ; Select temp @ 1 945 001b delay__temp__379select0 equ delay__temp+0 946 001b delay__temp__379select0__byte equ delay__temp+0 947 0001 delay__temp__379select0__bit equ 1 948 0da 53b bsf delay__temp__379select0__byte,delay__temp__379select0__bit 949 ; Uniform delay remaining = 126 Accumulated Delay = 1 950 ; Uniform delay remaining = 126 Accumulated Delay = 1 951 ; if { outputs_high @ 0 } body end 952 ; if exp=` outputs_high @ 0 ' false skip delay=2 953 ; Other expression=`{ outputs_high @ 0 }' delay=2 954 ; if { outputs_high @ 0 } end 955 ; Uniform delay remaining = 125 Accumulated Delay = 6 956 ; RC2 = IO6 : 957 ; Uniform delay remaining = 125 Accumulated Delay = 6 958 ; if { outputs_high @ 1 } start 959 ; Alias variable for select outputs_high @ 1 960 000d outputs_high__382select0 equ outputs_high+0 961 000d outputs_high__382select0__byte equ outputs_high+0 962 0001 outputs_high__382select0__bit equ 1 963 ; expression=`{ outputs_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 964 0db 62d btfsc outputs_high__382select0__byte,outputs_high__382select0__bit 965 ; if { outputs_high @ 1 } body start 966 ; Uniform delay remaining = 125 Accumulated Delay = 0 967 ; temp @ 2 := 1 968 ; Select temp @ 2 969 001b delay__temp__383select0 equ delay__temp+0 970 001b delay__temp__383select0__byte equ delay__temp+0 971 0002 delay__temp__383select0__bit equ 2 972 0dc 55b bsf delay__temp__383select0__byte,delay__temp__383select0__bit 973 ; Uniform delay remaining = 124 Accumulated Delay = 1 974 ; Uniform delay remaining = 124 Accumulated Delay = 1 975 ; if { outputs_high @ 1 } body end 976 ; if exp=` outputs_high @ 1 ' false skip delay=2 977 ; Other expression=`{ outputs_high @ 1 }' delay=2 978 ; if { outputs_high @ 1 } end 979 ; Uniform delay remaining = 123 Accumulated Delay = 8 980 ; RC3 = IO7 : 981 ; Uniform delay remaining = 123 Accumulated Delay = 8 982 ; if { outputs_high @ 2 } start 983 ; Alias variable for select outputs_high @ 2 984 000d outputs_high__386select0 equ outputs_high+0 985 000d outputs_high__386select0__byte equ outputs_high+0 986 0002 outputs_high__386select0__bit equ 2 987 ; expression=`{ outputs_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 988 0dd 64d btfsc outputs_high__386select0__byte,outputs_high__386select0__bit 989 ; if { outputs_high @ 2 } body start 990 ; Uniform delay remaining = 123 Accumulated Delay = 0 991 ; temp @ 3 := 1 992 ; Select temp @ 3 993 001b delay__temp__387select0 equ delay__temp+0 994 001b delay__temp__387select0__byte equ delay__temp+0 995 0003 delay__temp__387select0__bit equ 3 996 0de 57b bsf delay__temp__387select0__byte,delay__temp__387select0__bit 997 ; Uniform delay remaining = 122 Accumulated Delay = 1 998 ; Uniform delay remaining = 122 Accumulated Delay = 1 999 ; if { outputs_high @ 2 } body end 1000 ; if exp=` outputs_high @ 2 ' false skip delay=2 1001 ; Other expression=`{ outputs_high @ 2 }' delay=2 1002 ; if { outputs_high @ 2 } end 1003 ; Uniform delay remaining = 121 Accumulated Delay = 10 1004 ; RC4 = IO8 : 1005 ; Uniform delay remaining = 121 Accumulated Delay = 10 1006 ; if { outputs_high @ 3 } start 1007 ; Alias variable for select outputs_high @ 3 1008 000d outputs_high__390select0 equ outputs_high+0 1009 000d outputs_high__390select0__byte equ outputs_high+0 1010 0003 outputs_high__390select0__bit equ 3 1011 ; expression=`{ outputs_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1012 0df 66d btfsc outputs_high__390select0__byte,outputs_high__390select0__bit 1013 ; if { outputs_high @ 3 } body start 1014 ; Uniform delay remaining = 121 Accumulated Delay = 0 1015 ; temp @ 4 := 1 1016 ; Select temp @ 4 1017 001b delay__temp__391select0 equ delay__temp+0 1018 001b delay__temp__391select0__byte equ delay__temp+0 1019 0004 delay__temp__391select0__bit equ 4 1020 0e0 59b bsf delay__temp__391select0__byte,delay__temp__391select0__bit 1021 ; Uniform delay remaining = 120 Accumulated Delay = 1 1022 ; Uniform delay remaining = 120 Accumulated Delay = 1 1023 ; if { outputs_high @ 3 } body end 1024 ; if exp=` outputs_high @ 3 ' false skip delay=2 1025 ; Other expression=`{ outputs_high @ 3 }' delay=2 1026 ; if { outputs_high @ 3 } end 1027 ; Uniform delay remaining = 119 Accumulated Delay = 12 1028 ; RC5 = IO9 : 1029 ; Uniform delay remaining = 119 Accumulated Delay = 12 1030 ; if { outputs_high @ 4 } start 1031 ; Alias variable for select outputs_high @ 4 1032 000d outputs_high__394select0 equ outputs_high+0 1033 000d outputs_high__394select0__byte equ outputs_high+0 1034 0004 outputs_high__394select0__bit equ 4 1035 ; expression=`{ outputs_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1036 0e1 68d btfsc outputs_high__394select0__byte,outputs_high__394select0__bit 1037 ; if { outputs_high @ 4 } body start 1038 ; Uniform delay remaining = 119 Accumulated Delay = 0 1039 ; temp @ 5 := 1 1040 ; Select temp @ 5 1041 001b delay__temp__395select0 equ delay__temp+0 1042 001b delay__temp__395select0__byte equ delay__temp+0 1043 0005 delay__temp__395select0__bit equ 5 1044 0e2 5bb bsf delay__temp__395select0__byte,delay__temp__395select0__bit 1045 ; Uniform delay remaining = 118 Accumulated Delay = 1 1046 ; Uniform delay remaining = 118 Accumulated Delay = 1 1047 ; if { outputs_high @ 4 } body end 1048 ; if exp=` outputs_high @ 4 ' false skip delay=2 1049 ; Other expression=`{ outputs_high @ 4 }' delay=2 1050 ; if { outputs_high @ 4 } end 1051 ; Uniform delay remaining = 117 Accumulated Delay = 14 1052 ; portc := temp 1053 0e3 21b movf delay__temp,w 1054 0e4 027 movwf portc 1055 ; Uniform delay remaining = 115 Accumulated Delay = 16 1056 ; Uniform delay remaining = 115 Accumulated Delay = 16 1057 ; Set the port B outputs next : 1058 ; Uniform delay remaining = 115 Accumulated Delay = 16 1059 ; temp := 0 1060 0e5 07b clrf delay__temp 1061 ; Uniform delay remaining = 114 Accumulated Delay = 17 1062 ; RB0 = SOUT : 1063 ; Uniform delay remaining = 114 Accumulated Delay = 17 1064 ; if { portb @ 0 } start 1065 ; Alias variable for select portb @ 0 1066 0006 portb__402select0 equ portb+0 1067 0006 portb__402select0__byte equ portb+0 1068 0000 portb__402select0__bit equ 0 1069 ; expression=`{ portb @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1070 0e6 606 btfsc portb__402select0__byte,portb__402select0__bit 1071 ; if { portb @ 0 } body start 1072 ; Uniform delay remaining = 114 Accumulated Delay = 0 1073 ; temp @ 0 := 1 1074 ; Select temp @ 0 1075 001b delay__temp__403select0 equ delay__temp+0 1076 001b delay__temp__403select0__byte equ delay__temp+0 1077 0000 delay__temp__403select0__bit equ 0 1078 0e7 51b bsf delay__temp__403select0__byte,delay__temp__403select0__bit 1079 ; Uniform delay remaining = 113 Accumulated Delay = 1 1080 ; Uniform delay remaining = 113 Accumulated Delay = 1 1081 ; if { portb @ 0 } body end 1082 ; if exp=` portb @ 0 ' false skip delay=2 1083 ; Other expression=`{ portb @ 0 }' delay=2 1084 ; if { portb @ 0 } end 1085 ; Uniform delay remaining = 112 Accumulated Delay = 19 1086 ; RB1 = IO2 : 1087 ; Uniform delay remaining = 112 Accumulated Delay = 19 1088 ; if { outputs_low @ 2 } start 1089 ; Alias variable for select outputs_low @ 2 1090 000c outputs_low__406select0 equ outputs_low+0 1091 000c outputs_low__406select0__byte equ outputs_low+0 1092 0002 outputs_low__406select0__bit equ 2 1093 ; expression=`{ outputs_low @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1094 0e8 64c btfsc outputs_low__406select0__byte,outputs_low__406select0__bit 1095 ; if { outputs_low @ 2 } body start 1096 ; Uniform delay remaining = 112 Accumulated Delay = 0 1097 ; temp @ 1 := 1 1098 ; Select temp @ 1 1099 001b delay__temp__407select0 equ delay__temp+0 1100 001b delay__temp__407select0__byte equ delay__temp+0 1101 0001 delay__temp__407select0__bit equ 1 1102 0e9 53b bsf delay__temp__407select0__byte,delay__temp__407select0__bit 1103 ; Uniform delay remaining = 111 Accumulated Delay = 1 1104 ; Uniform delay remaining = 111 Accumulated Delay = 1 1105 ; if { outputs_low @ 2 } body end 1106 ; if exp=` outputs_low @ 2 ' false skip delay=2 1107 ; Other expression=`{ outputs_low @ 2 }' delay=2 1108 ; if { outputs_low @ 2 } end 1109 ; Uniform delay remaining = 110 Accumulated Delay = 21 1110 ; RB2 = IO3 : 1111 ; Uniform delay remaining = 110 Accumulated Delay = 21 1112 ; if { outputs_low @ 3 } start 1113 ; Alias variable for select outputs_low @ 3 1114 000c outputs_low__410select0 equ outputs_low+0 1115 000c outputs_low__410select0__byte equ outputs_low+0 1116 0003 outputs_low__410select0__bit equ 3 1117 ; expression=`{ outputs_low @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1118 0ea 66c btfsc outputs_low__410select0__byte,outputs_low__410select0__bit 1119 ; if { outputs_low @ 3 } body start 1120 ; Uniform delay remaining = 110 Accumulated Delay = 0 1121 ; temp @ 2 := 1 1122 ; Select temp @ 2 1123 001b delay__temp__411select0 equ delay__temp+0 1124 001b delay__temp__411select0__byte equ delay__temp+0 1125 0002 delay__temp__411select0__bit equ 2 1126 0eb 55b bsf delay__temp__411select0__byte,delay__temp__411select0__bit 1127 ; Uniform delay remaining = 109 Accumulated Delay = 1 1128 ; Uniform delay remaining = 109 Accumulated Delay = 1 1129 ; if { outputs_low @ 3 } body end 1130 ; if exp=` outputs_low @ 3 ' false skip delay=2 1131 ; Other expression=`{ outputs_low @ 3 }' delay=2 1132 ; if { outputs_low @ 3 } end 1133 ; Uniform delay remaining = 108 Accumulated Delay = 23 1134 ; RB3 = SIN : 1135 ; Uniform delay remaining = 108 Accumulated Delay = 23 1136 ; RB4 = IO1 : 1137 ; Uniform delay remaining = 108 Accumulated Delay = 23 1138 ; if { outputs_low @ 1 } start 1139 ; Alias variable for select outputs_low @ 1 1140 000c outputs_low__415select0 equ outputs_low+0 1141 000c outputs_low__415select0__byte equ outputs_low+0 1142 0001 outputs_low__415select0__bit equ 1 1143 ; expression=`{ outputs_low @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1144 0ec 62c btfsc outputs_low__415select0__byte,outputs_low__415select0__bit 1145 ; if { outputs_low @ 1 } body start 1146 ; Uniform delay remaining = 108 Accumulated Delay = 0 1147 ; temp @ 4 := 1 1148 ; Select temp @ 4 1149 001b delay__temp__416select0 equ delay__temp+0 1150 001b delay__temp__416select0__byte equ delay__temp+0 1151 0004 delay__temp__416select0__bit equ 4 1152 0ed 59b bsf delay__temp__416select0__byte,delay__temp__416select0__bit 1153 ; Uniform delay remaining = 107 Accumulated Delay = 1 1154 ; Uniform delay remaining = 107 Accumulated Delay = 1 1155 ; if { outputs_low @ 1 } body end 1156 ; if exp=` outputs_low @ 1 ' false skip delay=2 1157 ; Other expression=`{ outputs_low @ 1 }' delay=2 1158 ; if { outputs_low @ 1 } end 1159 ; Uniform delay remaining = 106 Accumulated Delay = 25 1160 ; RB5 = IO0 : 1161 ; Uniform delay remaining = 106 Accumulated Delay = 25 1162 ; if { outputs_low @ 0 } start 1163 ; Alias variable for select outputs_low @ 0 1164 000c outputs_low__419select0 equ outputs_low+0 1165 000c outputs_low__419select0__byte equ outputs_low+0 1166 0000 outputs_low__419select0__bit equ 0 1167 ; expression=`{ outputs_low @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1168 0ee 60c btfsc outputs_low__419select0__byte,outputs_low__419select0__bit 1169 ; if { outputs_low @ 0 } body start 1170 ; Uniform delay remaining = 106 Accumulated Delay = 0 1171 ; temp @ 5 := 1 1172 ; Select temp @ 5 1173 001b delay__temp__420select0 equ delay__temp+0 1174 001b delay__temp__420select0__byte equ delay__temp+0 1175 0005 delay__temp__420select0__bit equ 5 1176 0ef 5bb bsf delay__temp__420select0__byte,delay__temp__420select0__bit 1177 ; Uniform delay remaining = 105 Accumulated Delay = 1 1178 ; Uniform delay remaining = 105 Accumulated Delay = 1 1179 ; if { outputs_low @ 0 } body end 1180 ; if exp=` outputs_low @ 0 ' false skip delay=2 1181 ; Other expression=`{ outputs_low @ 0 }' delay=2 1182 ; if { outputs_low @ 0 } end 1183 ; Uniform delay remaining = 104 Accumulated Delay = 27 1184 ; portb := temp 1185 0f0 21b movf delay__temp,w 1186 0f1 026 movwf portb 1187 ; Uniform delay remaining = 102 Accumulated Delay = 29 1188 ; Uniform delay remaining = 102 Accumulated Delay = 29 1189 ; Now read inputs : 1190 ; Uniform delay remaining = 102 Accumulated Delay = 29 1191 ; raw_low := 0 1192 0f2 068 clrf raw_low 1193 ; Uniform delay remaining = 101 Accumulated Delay = 30 1194 ; raw_high := 0 1195 0f3 069 clrf raw_high 1196 ; Uniform delay remaining = 100 Accumulated Delay = 31 1197 ; temp := portb 1198 0f4 206 movf portb,w 1199 0f5 03b movwf delay__temp 1200 ; Uniform delay remaining = 98 Accumulated Delay = 33 1201 ; RB0 = SOUT : 1202 ; Uniform delay remaining = 98 Accumulated Delay = 33 1203 ; RB1 = IO2 : 1204 ; Uniform delay remaining = 98 Accumulated Delay = 33 1205 ; if { temp @ 1 } start 1206 ; Alias variable for select temp @ 1 1207 001b delay__temp__430select0 equ delay__temp+0 1208 001b delay__temp__430select0__byte equ delay__temp+0 1209 0001 delay__temp__430select0__bit equ 1 1210 ; expression=`{ temp @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1211 0f6 63b btfsc delay__temp__430select0__byte,delay__temp__430select0__bit 1212 ; if { temp @ 1 } body start 1213 ; Uniform delay remaining = 98 Accumulated Delay = 0 1214 ; raw_low @ 2 := 1 1215 ; Select raw_low @ 2 1216 0008 raw_low__431select0 equ raw_low+0 1217 0008 raw_low__431select0__byte equ raw_low+0 1218 0002 raw_low__431select0__bit equ 2 1219 0f7 548 bsf raw_low__431select0__byte,raw_low__431select0__bit 1220 ; Uniform delay remaining = 97 Accumulated Delay = 1 1221 ; Uniform delay remaining = 97 Accumulated Delay = 1 1222 ; if { temp @ 1 } body end 1223 ; if exp=` temp @ 1 ' false skip delay=2 1224 ; Other expression=`{ temp @ 1 }' delay=2 1225 ; if { temp @ 1 } end 1226 ; Uniform delay remaining = 96 Accumulated Delay = 35 1227 ; RB2 = IO3 : 1228 ; Uniform delay remaining = 96 Accumulated Delay = 35 1229 ; if { temp @ 2 } start 1230 ; Alias variable for select temp @ 2 1231 001b delay__temp__434select0 equ delay__temp+0 1232 001b delay__temp__434select0__byte equ delay__temp+0 1233 0002 delay__temp__434select0__bit equ 2 1234 ; expression=`{ temp @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1235 0f8 65b btfsc delay__temp__434select0__byte,delay__temp__434select0__bit 1236 ; if { temp @ 2 } body start 1237 ; Uniform delay remaining = 96 Accumulated Delay = 0 1238 ; raw_low @ 3 := 1 1239 ; Select raw_low @ 3 1240 0008 raw_low__435select0 equ raw_low+0 1241 0008 raw_low__435select0__byte equ raw_low+0 1242 0003 raw_low__435select0__bit equ 3 1243 0f9 568 bsf raw_low__435select0__byte,raw_low__435select0__bit 1244 ; Uniform delay remaining = 95 Accumulated Delay = 1 1245 ; Uniform delay remaining = 95 Accumulated Delay = 1 1246 ; if { temp @ 2 } body end 1247 ; if exp=` temp @ 2 ' false skip delay=2 1248 ; Other expression=`{ temp @ 2 }' delay=2 1249 ; if { temp @ 2 } end 1250 ; Uniform delay remaining = 94 Accumulated Delay = 37 1251 ; RB3 = SIN : 1252 ; Uniform delay remaining = 94 Accumulated Delay = 37 1253 ; RB4 = IO1 : 1254 ; Uniform delay remaining = 94 Accumulated Delay = 37 1255 ; if { temp @ 4 } start 1256 ; Alias variable for select temp @ 4 1257 001b delay__temp__439select0 equ delay__temp+0 1258 001b delay__temp__439select0__byte equ delay__temp+0 1259 0004 delay__temp__439select0__bit equ 4 1260 ; expression=`{ temp @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1261 0fa 69b btfsc delay__temp__439select0__byte,delay__temp__439select0__bit 1262 ; if { temp @ 4 } body start 1263 ; Uniform delay remaining = 94 Accumulated Delay = 0 1264 ; raw_low @ 1 := 1 1265 ; Select raw_low @ 1 1266 0008 raw_low__440select0 equ raw_low+0 1267 0008 raw_low__440select0__byte equ raw_low+0 1268 0001 raw_low__440select0__bit equ 1 1269 0fb 528 bsf raw_low__440select0__byte,raw_low__440select0__bit 1270 ; Uniform delay remaining = 93 Accumulated Delay = 1 1271 ; Uniform delay remaining = 93 Accumulated Delay = 1 1272 ; if { temp @ 4 } body end 1273 ; if exp=` temp @ 4 ' false skip delay=2 1274 ; Other expression=`{ temp @ 4 }' delay=2 1275 ; if { temp @ 4 } end 1276 ; Uniform delay remaining = 92 Accumulated Delay = 39 1277 ; RB5 = IO0 : 1278 ; Uniform delay remaining = 92 Accumulated Delay = 39 1279 ; if { temp @ 5 } start 1280 ; Alias variable for select temp @ 5 1281 001b delay__temp__443select0 equ delay__temp+0 1282 001b delay__temp__443select0__byte equ delay__temp+0 1283 0005 delay__temp__443select0__bit equ 5 1284 ; expression=`{ temp @ 5 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1285 0fc 6bb btfsc delay__temp__443select0__byte,delay__temp__443select0__bit 1286 ; if { temp @ 5 } body start 1287 ; Uniform delay remaining = 92 Accumulated Delay = 0 1288 ; raw_low @ 0 := 1 1289 ; Select raw_low @ 0 1290 0008 raw_low__444select0 equ raw_low+0 1291 0008 raw_low__444select0__byte equ raw_low+0 1292 0000 raw_low__444select0__bit equ 0 1293 0fd 508 bsf raw_low__444select0__byte,raw_low__444select0__bit 1294 ; Uniform delay remaining = 91 Accumulated Delay = 1 1295 ; Uniform delay remaining = 91 Accumulated Delay = 1 1296 ; if { temp @ 5 } body end 1297 ; if exp=` temp @ 5 ' false skip delay=2 1298 ; Other expression=`{ temp @ 5 }' delay=2 1299 ; if { temp @ 5 } end 1300 ; Uniform delay remaining = 90 Accumulated Delay = 41 1301 ; temp := portc 1302 0fe 207 movf portc,w 1303 0ff 03b movwf delay__temp 1304 ; Uniform delay remaining = 88 Accumulated Delay = 43 1305 ; RC0 = IO4 : 1306 ; Uniform delay remaining = 88 Accumulated Delay = 43 1307 ; if { temp @ 0 } start 1308 ; Alias variable for select temp @ 0 1309 001b delay__temp__448select0 equ delay__temp+0 1310 001b delay__temp__448select0__byte equ delay__temp+0 1311 0000 delay__temp__448select0__bit equ 0 1312 ; expression=`{ temp @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1313 100 61b btfsc delay__temp__448select0__byte,delay__temp__448select0__bit 1314 ; if { temp @ 0 } body start 1315 ; Uniform delay remaining = 88 Accumulated Delay = 0 1316 ; raw_low @ 4 := 1 1317 ; Select raw_low @ 4 1318 0008 raw_low__449select0 equ raw_low+0 1319 0008 raw_low__449select0__byte equ raw_low+0 1320 0004 raw_low__449select0__bit equ 4 1321 101 588 bsf raw_low__449select0__byte,raw_low__449select0__bit 1322 ; Uniform delay remaining = 87 Accumulated Delay = 1 1323 ; Uniform delay remaining = 87 Accumulated Delay = 1 1324 ; if { temp @ 0 } body end 1325 ; if exp=` temp @ 0 ' false skip delay=2 1326 ; Other expression=`{ temp @ 0 }' delay=2 1327 ; if { temp @ 0 } end 1328 ; Uniform delay remaining = 86 Accumulated Delay = 45 1329 ; RC1 = IO5 : 1330 ; Uniform delay remaining = 86 Accumulated Delay = 45 1331 ; if { temp @ 1 } start 1332 ; Alias variable for select temp @ 1 1333 001b delay__temp__452select0 equ delay__temp+0 1334 001b delay__temp__452select0__byte equ delay__temp+0 1335 0001 delay__temp__452select0__bit equ 1 1336 ; expression=`{ temp @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1337 102 63b btfsc delay__temp__452select0__byte,delay__temp__452select0__bit 1338 ; if { temp @ 1 } body start 1339 ; Uniform delay remaining = 86 Accumulated Delay = 0 1340 ; raw_high @ 0 := 1 1341 ; Select raw_high @ 0 1342 0009 raw_high__453select0 equ raw_high+0 1343 0009 raw_high__453select0__byte equ raw_high+0 1344 0000 raw_high__453select0__bit equ 0 1345 103 509 bsf raw_high__453select0__byte,raw_high__453select0__bit 1346 ; Uniform delay remaining = 85 Accumulated Delay = 1 1347 ; Uniform delay remaining = 85 Accumulated Delay = 1 1348 ; if { temp @ 1 } body end 1349 ; if exp=` temp @ 1 ' false skip delay=2 1350 ; Other expression=`{ temp @ 1 }' delay=2 1351 ; if { temp @ 1 } end 1352 ; Uniform delay remaining = 84 Accumulated Delay = 47 1353 ; RC2 = IO6 : 1354 ; Uniform delay remaining = 84 Accumulated Delay = 47 1355 ; if { temp @ 2 } start 1356 ; Alias variable for select temp @ 2 1357 001b delay__temp__456select0 equ delay__temp+0 1358 001b delay__temp__456select0__byte equ delay__temp+0 1359 0002 delay__temp__456select0__bit equ 2 1360 ; expression=`{ temp @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1361 104 65b btfsc delay__temp__456select0__byte,delay__temp__456select0__bit 1362 ; if { temp @ 2 } body start 1363 ; Uniform delay remaining = 84 Accumulated Delay = 0 1364 ; raw_high @ 1 := 1 1365 ; Select raw_high @ 1 1366 0009 raw_high__457select0 equ raw_high+0 1367 0009 raw_high__457select0__byte equ raw_high+0 1368 0001 raw_high__457select0__bit equ 1 1369 105 529 bsf raw_high__457select0__byte,raw_high__457select0__bit 1370 ; Uniform delay remaining = 83 Accumulated Delay = 1 1371 ; Uniform delay remaining = 83 Accumulated Delay = 1 1372 ; if { temp @ 2 } body end 1373 ; if exp=` temp @ 2 ' false skip delay=2 1374 ; Other expression=`{ temp @ 2 }' delay=2 1375 ; if { temp @ 2 } end 1376 ; Uniform delay remaining = 82 Accumulated Delay = 49 1377 ; RC3 = IO7 : 1378 ; Uniform delay remaining = 82 Accumulated Delay = 49 1379 ; if { temp @ 3 } start 1380 ; Alias variable for select temp @ 3 1381 001b delay__temp__460select0 equ delay__temp+0 1382 001b delay__temp__460select0__byte equ delay__temp+0 1383 0003 delay__temp__460select0__bit equ 3 1384 ; expression=`{ temp @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1385 106 67b btfsc delay__temp__460select0__byte,delay__temp__460select0__bit 1386 ; if { temp @ 3 } body start 1387 ; Uniform delay remaining = 82 Accumulated Delay = 0 1388 ; raw_high @ 2 := 1 1389 ; Select raw_high @ 2 1390 0009 raw_high__461select0 equ raw_high+0 1391 0009 raw_high__461select0__byte equ raw_high+0 1392 0002 raw_high__461select0__bit equ 2 1393 107 549 bsf raw_high__461select0__byte,raw_high__461select0__bit 1394 ; Uniform delay remaining = 81 Accumulated Delay = 1 1395 ; Uniform delay remaining = 81 Accumulated Delay = 1 1396 ; if { temp @ 3 } body end 1397 ; if exp=` temp @ 3 ' false skip delay=2 1398 ; Other expression=`{ temp @ 3 }' delay=2 1399 ; if { temp @ 3 } end 1400 ; Uniform delay remaining = 80 Accumulated Delay = 51 1401 ; RC4 = IO8 : 1402 ; Uniform delay remaining = 80 Accumulated Delay = 51 1403 ; if { temp @ 4 } start 1404 ; Alias variable for select temp @ 4 1405 001b delay__temp__464select0 equ delay__temp+0 1406 001b delay__temp__464select0__byte equ delay__temp+0 1407 0004 delay__temp__464select0__bit equ 4 1408 ; expression=`{ temp @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1409 108 69b btfsc delay__temp__464select0__byte,delay__temp__464select0__bit 1410 ; if { temp @ 4 } body start 1411 ; Uniform delay remaining = 80 Accumulated Delay = 0 1412 ; raw_high @ 3 := 1 1413 ; Select raw_high @ 3 1414 0009 raw_high__465select0 equ raw_high+0 1415 0009 raw_high__465select0__byte equ raw_high+0 1416 0003 raw_high__465select0__bit equ 3 1417 109 569 bsf raw_high__465select0__byte,raw_high__465select0__bit 1418 ; Uniform delay remaining = 79 Accumulated Delay = 1 1419 ; Uniform delay remaining = 79 Accumulated Delay = 1 1420 ; if { temp @ 4 } body end 1421 ; if exp=` temp @ 4 ' false skip delay=2 1422 ; Other expression=`{ temp @ 4 }' delay=2 1423 ; if { temp @ 4 } end 1424 ; Uniform delay remaining = 78 Accumulated Delay = 53 1425 ; RC5 = IO9 : 1426 ; Uniform delay remaining = 78 Accumulated Delay = 53 1427 ; if { temp @ 5 } start 1428 ; Alias variable for select temp @ 5 1429 001b delay__temp__468select0 equ delay__temp+0 1430 001b delay__temp__468select0__byte equ delay__temp+0 1431 0005 delay__temp__468select0__bit equ 5 1432 ; expression=`{ temp @ 5 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1433 10a 6bb btfsc delay__temp__468select0__byte,delay__temp__468select0__bit 1434 ; if { temp @ 5 } body start 1435 ; Uniform delay remaining = 78 Accumulated Delay = 0 1436 ; raw_high @ 4 := 1 1437 ; Select raw_high @ 4 1438 0009 raw_high__469select0 equ raw_high+0 1439 0009 raw_high__469select0__byte equ raw_high+0 1440 0004 raw_high__469select0__bit equ 4 1441 10b 589 bsf raw_high__469select0__byte,raw_high__469select0__bit 1442 ; Uniform delay remaining = 77 Accumulated Delay = 1 1443 ; Uniform delay remaining = 77 Accumulated Delay = 1 1444 ; if { temp @ 5 } body end 1445 ; if exp=` temp @ 5 ' false skip delay=2 1446 ; Other expression=`{ temp @ 5 }' delay=2 1447 ; if { temp @ 5 } end 1448 ; Uniform delay remaining = 76 Accumulated Delay = 55 1449 ; Uniform delay remaining = 76 Accumulated Delay = 55 1450 ; Process the inputs through the complements mask : 1451 ; Uniform delay remaining = 76 Accumulated Delay = 55 1452 ; previous_low := inputs_low 1453 10c 20a movf inputs_low,w 1454 10d 039 movwf delay__previous_low 1455 ; Uniform delay remaining = 74 Accumulated Delay = 57 1456 ; previous_high := inputs_high 1457 10e 20b movf inputs_high,w 1458 10f 03a movwf delay__previous_high 1459 ; Uniform delay remaining = 72 Accumulated Delay = 59 1460 ; inputs_low := {{ raw_low ^ complement_low }} & mask 1461 110 208 movf raw_low,w 1462 111 18e xorwf complement_low,w 1463 112 e1f andlw 31 1464 113 02a movwf inputs_low 1465 ; Uniform delay remaining = 68 Accumulated Delay = 63 1466 ; inputs_high := {{ raw_high ^ complement_high }} & mask 1467 114 209 movf raw_high,w 1468 115 18f xorwf complement_high,w 1469 116 e1f andlw 31 1470 117 02b movwf inputs_high 1471 ; Uniform delay remaining = 64 Accumulated Delay = 67 1472 ; Uniform delay remaining = 64 Accumulated Delay = 67 1473 ; Now generate any interrupts : 1474 ; Uniform delay remaining = 64 Accumulated Delay = 67 1475 ; temp := inputs_low & high_low | inputs_high & high_high 1476 118 20a movf inputs_low,w 1477 119 152 andwf high_low,w 1478 11a 03c movwf delay__479byte0 1479 11b 20b movf inputs_high,w 1480 11c 153 andwf high_high,w 1481 11d 11c iorwf delay__479byte0,w 1482 11e 03b movwf delay__temp 1483 ; Uniform delay remaining = 57 Accumulated Delay = 74 1484 ; temp := temp | {{ inputs_low ^ mask }} & low_low | {{ inputs_high ^ mask }} & low_high 1485 11f 21b movf delay__temp,w 1486 120 03c movwf delay__480byte0 1487 121 c1f movlw 31 1488 122 18a xorwf inputs_low,w 1489 123 150 andwf low_low,w 1490 124 13c iorwf delay__480byte0,f 1491 125 c1f movlw 31 1492 126 18b xorwf inputs_high,w 1493 127 151 andwf low_high,w 1494 128 11c iorwf delay__480byte0,w 1495 129 03b movwf delay__temp 1496 ; Uniform delay remaining = 46 Accumulated Delay = 85 1497 ; temp := temp | {{ inputs_low ^ previous_low }} & raising_low & inputs_low 1498 12a 20a movf inputs_low,w 1499 12b 199 xorwf delay__previous_low,w 1500 12c 154 andwf raising_low,w 1501 12d 14a andwf inputs_low,w 1502 12e 13b iorwf delay__temp,f 1503 ; Uniform delay remaining = 41 Accumulated Delay = 90 1504 ; temp := temp | {{ inputs_high ^ previous_high }} & raising_high & inputs_high 1505 12f 20b movf inputs_high,w 1506 130 19a xorwf delay__previous_high,w 1507 131 155 andwf raising_high,w 1508 132 14b andwf inputs_high,w 1509 133 13b iorwf delay__temp,f 1510 ; Uniform delay remaining = 36 Accumulated Delay = 95 1511 ; temp := temp | {{ inputs_low ^ previous_low }} & falling_low & previous_low 1512 134 20a movf inputs_low,w 1513 135 199 xorwf delay__previous_low,w 1514 136 156 andwf falling_low,w 1515 137 159 andwf delay__previous_low,w 1516 138 13b iorwf delay__temp,f 1517 ; Uniform delay remaining = 31 Accumulated Delay = 100 1518 ; temp := temp | {{ inputs_high ^ previous_high }} & falling_high & previous_high 1519 139 20b movf inputs_high,w 1520 13a 19a xorwf delay__previous_high,w 1521 13b 157 andwf falling_high,w 1522 13c 15a andwf delay__previous_high,w 1523 13d 13b iorwf delay__temp,f 1524 ; Uniform delay remaining = 26 Accumulated Delay = 105 1525 ; if { temp != 0 } start 1526 13e 21b movf delay__temp,w 1527 ; expression=`{ temp != 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1528 13f 743 btfss z___byte,z___bit 1529 ; if { temp != 0 } body start 1530 ; Uniform delay remaining = 26 Accumulated Delay = 0 1531 ; interrupt_pending := 1 1532 140 53e bsf interrupt_pending__byte,interrupt_pending__bit 1533 ; Uniform delay remaining = 25 Accumulated Delay = 1 1534 ; Uniform delay remaining = 25 Accumulated Delay = 1 1535 ; if { temp != 0 } body end 1536 ; if exp=` temp != 0 ' false skip delay=3 1537 ; Other expression=`{ temp != 0 }' delay=3 1538 ; if { temp != 0 } end 1539 ; Uniform delay remaining = 23 Accumulated Delay = 108 1540 ; if { receiving && interrupt_pending && interrupt_enable } start 1541 ; expression=`receiving' exp_delay=0 true_delay=10 false_delay=9 true_size=14 false_size=1 1542 141 65e btfsc receiving__byte,receiving__bit 1543 142 b46 goto label488__4true 1544 label488__4false: 1545 ; Delay 2 cycles 1546 143 000 nop 1547 144 000 nop 1548 145 b51 goto and488__2false 1549 label488__4true: 1550 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1551 146 73e btfss interrupt_pending__byte,interrupt_pending__bit 1552 147 b51 goto label488__3false 1553 label488__3true: 1554 and488__2true: 1555 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1556 148 71e btfss interrupt_enable__byte,interrupt_enable__bit 1557 149 b4d goto label488__1false 1558 label488__1true: 1559 and488__0true: 1560 ; if { receiving && interrupt_pending && interrupt_enable } body start 1561 ; Uniform delay remaining = 23 Accumulated Delay = 0 1562 ; serial_out := 0 1563 14a 406 bcf serial_out__byte,serial_out__bit 1564 ; Uniform delay remaining = 22 Accumulated Delay = 1 1565 ; interrupt_enable := 0 1566 14b 41e bcf interrupt_enable__byte,interrupt_enable__bit 1567 ; Uniform delay remaining = 21 Accumulated Delay = 2 1568 ; Uniform delay remaining = 21 Accumulated Delay = 2 1569 ; if { receiving && interrupt_pending && interrupt_enable } body end 1570 14c b50 goto label488__1end 1571 label488__1false: 1572 ; Delay 3 cycles 1573 14d 000 nop 1574 14e 000 nop 1575 14f 000 nop 1576 ; if exp=`interrupt_enable' total delay=6 1577 ; if exp=`interrupt_enable' generic 1578 label488__1end: 1579 ; Other expression=`interrupt_enable' delay=6 1580 150 b54 goto label488__3end 1581 label488__3false: 1582 and488__2false: 1583 ; Delay 2 cycles 1584 151 000 nop 1585 152 000 nop 1586 153 b54 goto and488__0false 1587 ; if exp=`interrupt_pending' total delay=10 1588 ; if exp=`interrupt_pending' generic 1589 label488__3end: 1590 ; Other expression=`interrupt_pending' delay=10 1591 ; if exp=`receiving' total delay=13 1592 ; if exp=`receiving' generic 1593 label488__4end: 1594 ; Other expression=`receiving' delay=13 1595 and488__2end: 1596 and488__0false: 1597 and488__0end: 1598 ; if { receiving && interrupt_pending && interrupt_enable } end 1599 ; Uniform delay remaining = 10 Accumulated Delay = 121 1600 ; Uniform delay remaining = 10 Accumulated Delay = 121 1601 ; Soak up remaining 10 cycles 1602 ; Delay 10 cycles 1603 154 c03 movlw 3 1604 155 03c movwf delay__356byte1 1605 delay__356delay0: 1606 156 2fc decfsz delay__356byte1,f 1607 157 b56 goto delay__356delay0 1608 ; procedure delay end 1609 158 800 retlw 0 1610 ; optimize 1 1611 ; origin 0x200 1612 org 512 1613 ; bank 1 1614 ; Default register bank is now 1 1615 ; comment {The main procedure is loaded with switch statements . On the 12 - bit} 1616 ; comment {PIC ' s , switch statements have to live in the first 256 bytes of} 1617 ; comment {each code bank . For this reason , we shove main into code bank 1 .} 1618 ; comment {If we , try to put main in code bank 0 , it pushes the first bytes} 1619 ; comment {of several routines out of the first 256 bytes , which is also a} 1620 ; comment {no - no of the 12 - bit PIC ' s .} 1621 1622 ; procedure main start 1623 switch__526block_start: 1624 200 1e2 addwf pcl___register,f 1625 201 a6f goto switch__526block527 1626 202 a72 goto switch__526block531 1627 203 a75 goto switch__526block535 1628 204 a78 goto switch__526block539 1629 205 a7b goto switch__526block543 1630 206 a7e goto switch__526block547 1631 207 a81 goto switch__526block551 1632 208 a84 goto switch__526block555 1633 switch__526block_end: 1634 ; switch_check 526 switch__526block_start switch__526block_end 1635 switch__564block_start: 1636 209 1e2 addwf pcl___register,f 1637 20a a90 goto switch__564block565 1638 20b a95 goto switch__564block569 1639 20c a9a goto switch__564block573 1640 20d a9f goto switch__564block577 1641 20e aa4 goto switch__564block581 1642 20f aa9 goto switch__564block585 1643 210 aae goto switch__564block589 1644 211 ab3 goto switch__564block593 1645 switch__564block_end: 1646 ; switch_check 564 switch__564block_start switch__564block_end 1647 switch__602block_start: 1648 212 1e2 addwf pcl___register,f 1649 213 ac1 goto switch__602block603 1650 214 ac7 goto switch__602block607 1651 215 acd goto switch__602block611 1652 216 ad4 goto switch__602block615 1653 217 adb goto switch__602block619 1654 218 ae3 goto switch__602block624 1655 219 aeb goto switch__602block629 1656 21a aee goto switch__602block634 1657 switch__602block_end: 1658 ; switch_check 602 switch__602block_start switch__602block_end 1659 switch__643block_start: 1660 21b 1e2 addwf pcl___register,f 1661 21c afb goto switch__643block644 1662 21d b00 goto switch__643block648 1663 21e b05 goto switch__643block652 1664 21f b0a goto switch__643block656 1665 220 b0f goto switch__643block660 1666 221 b14 goto switch__643block664 1667 222 b19 goto switch__643block668 1668 223 b1e goto switch__643block672 1669 switch__643block_end: 1670 ; switch_check 643 switch__643block_start switch__643block_end 1671 switch__523block_start: 1672 224 1e2 addwf pcl___register,f 1673 225 a6c goto switch__523block524 1674 226 a8d goto switch__523block562 1675 227 abe goto switch__523block600 1676 228 af2 goto switch__523block640 1677 229 b23 goto switch__523block678 1678 22a b23 goto switch__523block678 1679 22b b23 goto switch__523block678 1680 22c b23 goto switch__523block678 1681 switch__523block_end: 1682 ; switch_check 523 switch__523block_start switch__523block_end 1683 switch__688block_start: 1684 22d 1e2 addwf pcl___register,f 1685 22e b30 goto switch__688block689 1686 22f b38 goto switch__688block692 1687 230 b40 goto switch__688block695 1688 231 b48 goto switch__688block698 1689 232 b50 goto switch__688block701 1690 233 b58 goto switch__688block704 1691 234 b60 goto switch__688block707 1692 235 b68 goto switch__688block710 1693 236 b70 goto switch__688block713 1694 237 b78 goto switch__688block716 1695 switch__688block_end: 1696 ; switch_check 688 switch__688block_start switch__688block_end 1697 switch__756block_start: 1698 238 1e2 addwf pcl___register,f 1699 239 ba0 goto switch__756block757 1700 23a ba0 goto switch__756block757 1701 23b ba0 goto switch__756block757 1702 23c ba0 goto switch__756block757 1703 23d ba9 goto switch__756block762 1704 23e ba9 goto switch__756block762 1705 23f baf goto switch__756block766 1706 240 baf goto switch__756block766 1707 switch__756block_end: 1708 ; switch_check 756 switch__756block_start switch__756block_end 1709 switch__773block_start: 1710 241 1e2 addwf pcl___register,f 1711 242 bb8 goto switch__773block774 1712 243 bbb goto switch__773block778 1713 244 bbe goto switch__773block782 1714 245 bc4 goto switch__773block786 1715 246 bc9 goto switch__773block790 1716 247 bd7 goto switch__773block798 1717 248 bd9 goto switch__773block802 1718 249 be0 goto switch__773block807 1719 switch__773block_end: 1720 ; switch_check 773 switch__773block_start switch__773block_end 1721 switch__731block_start: 1722 24a 1e2 addwf pcl___register,f 1723 24b b87 goto switch__731block732 1724 24c b87 goto switch__731block732 1725 24d b87 goto switch__731block732 1726 24e b87 goto switch__731block732 1727 24f b87 goto switch__731block732 1728 250 b88 goto switch__731block736 1729 251 b99 goto switch__731block750 1730 252 bb5 goto switch__731block772 1731 switch__731block_end: 1732 ; switch_check 731 switch__731block_start switch__731block_end 1733 switch__520block_start: 1734 253 1e2 addwf pcl___register,f 1735 254 a66 goto switch__520block521 1736 255 b27 goto switch__520block684 1737 256 b80 goto switch__520block725 1738 257 b81 goto switch__520block729 1739 switch__520block_end: 1740 ; switch_check 520 switch__520block_start switch__520block_end 1741 main: 1742 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1743 ; Procedure must be called with PCLATH set to code bank 0 1744 003a main__variables__base equ global__variables__bank1+10 1745 003a main__bytes__base equ main__variables__base+0 1746 003d main__bits__base equ main__variables__base+3 1747 0004 main__total__bytes equ 4 1748 003c main__523byte0 equ main__bytes__base+2 1749 003c main__731byte0 equ main__bytes__base+2 1750 003c main__520byte0 equ main__bytes__base+2 1751 003d main__714bit1 equ main__bits__base+0 1752 003d main__714bit1__byte equ main__bits__base+0 1753 0000 main__714bit1__bit equ 0 1754 003d main__717bit1 equ main__bits__base+0 1755 003d main__717bit1__byte equ main__bits__base+0 1756 0000 main__717bit1__bit equ 0 1757 003d main__690bit1 equ main__bits__base+0 1758 003d main__690bit1__byte equ main__bits__base+0 1759 0000 main__690bit1__bit equ 0 1760 003d main__702bit1 equ main__bits__base+0 1761 003d main__702bit1__byte equ main__bits__base+0 1762 0000 main__702bit1__bit equ 0 1763 003d main__693bit1 equ main__bits__base+0 1764 003d main__693bit1__byte equ main__bits__base+0 1765 0000 main__693bit1__bit equ 0 1766 003d main__705bit1 equ main__bits__base+0 1767 003d main__705bit1__byte equ main__bits__base+0 1768 0000 main__705bit1__bit equ 0 1769 003d main__696bit1 equ main__bits__base+0 1770 003d main__696bit1__byte equ main__bits__base+0 1771 0000 main__696bit1__bit equ 0 1772 003d main__708bit1 equ main__bits__base+0 1773 003d main__708bit1__byte equ main__bits__base+0 1774 0000 main__708bit1__bit equ 0 1775 003d main__699bit1 equ main__bits__base+0 1776 003d main__699bit1__byte equ main__bits__base+0 1777 0000 main__699bit1__bit equ 0 1778 003d main__711bit1 equ main__bits__base+0 1779 003d main__711bit1__byte equ main__bits__base+0 1780 0000 main__711bit1__bit equ 0 1781 ; arguments_none 1782 003a main__command equ main__bytes__base+0 1783 003b main__temp equ main__bytes__base+1 1784 ; Initalize all of the globals : 1785 ; call reset {{ }} 1786 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1787 258 4a3 bcf pa0___byte,pa0___bit 1788 259 9ba call reset 1789 ; Process commands : 1790 ; loop_forever ... start 1791 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1792 25a 5a3 bsf pa0___byte,pa0___bit 1793 main__515loop__forever: 1794 ; Wait for command : 1795 ; command := get_byte {{ }} 1796 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1797 25b 4a3 bcf pa0___byte,pa0___bit 1798 25c 93e call get_byte 1799 25d 214 movf get_byte__0return__byte,w 1800 25e 03a movwf main__command 1801 ; Dispatch on command : 1802 ; switch { command >> 6 } 1803 25f 39a swapf main__command,w 1804 260 03c movwf main__520byte0 1805 261 33c rrf main__520byte0,f 1806 262 31c rrf main__520byte0,w 1807 263 e03 andlw 3 1808 ; case 0 1809 ; case 1 1810 ; case 2 1811 ; case 3 1812 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1813 264 5a3 bsf pa0___byte,pa0___bit 1814 265 a53 goto switch__520block_start 1815 switch__520block521: 1816 ; < Command = 00 xx xxxx > : 1817 ; switch { {{ command >> 3 }} & 7 } 1818 266 31a rrf main__command,w 1819 267 03c movwf main__523byte0 1820 268 33c rrf main__523byte0,f 1821 269 31c rrf main__523byte0,w 1822 26a e07 andlw 7 1823 ; case 0 1824 ; case 1 1825 ; case 2 1826 ; case 3 1827 ; case 4 5 6 7 1828 26b a24 goto switch__523block_start 1829 switch__523block524: 1830 ; < Command = 0000 0 xxx > : 1831 ; switch { command & 7 } 1832 26c c07 movlw 7 1833 26d 15a andwf main__command,w 1834 ; case 0 1835 ; case 1 1836 ; case 2 1837 ; case 3 1838 ; case 4 1839 ; case 5 1840 ; case 6 1841 ; case 7 1842 26e a00 goto switch__526block_start 1843 switch__526block527: 1844 ; Read Inputs Low < Command = 0000 0000 > : 1845 ; temp := inputs_low 1846 26f 20a movf inputs_low,w 1847 270 03b movwf main__temp 1848 271 a86 goto switch__526end 1849 switch__526block531: 1850 ; Read Inputs High < Command = 0000 0001 > : 1851 ; temp := inputs_high 1852 272 20b movf inputs_high,w 1853 273 03b movwf main__temp 1854 274 a86 goto switch__526end 1855 switch__526block535: 1856 ; Read Complement Mask Low < Command = 0000 0010 > : 1857 ; temp := complement_low 1858 275 20e movf complement_low,w 1859 276 03b movwf main__temp 1860 277 a86 goto switch__526end 1861 switch__526block539: 1862 ; Read Complement Mask High < Command = 0000 0011 > : 1863 ; temp := complement_high 1864 278 20f movf complement_high,w 1865 279 03b movwf main__temp 1866 27a a86 goto switch__526end 1867 switch__526block543: 1868 ; Read Direction Mask Low < Command = 0000 0100 > : 1869 ; temp := direction_low 1870 27b 210 movf direction_low,w 1871 27c 03b movwf main__temp 1872 27d a86 goto switch__526end 1873 switch__526block547: 1874 ; Read Direction Mask High < Command = 0000 0101 > : 1875 ; temp := direction_high 1876 27e 211 movf direction_high,w 1877 27f 03b movwf main__temp 1878 280 a86 goto switch__526end 1879 switch__526block551: 1880 ; Read Raw Low < Command = 0000 0110 > : 1881 ; temp := raw_low 1882 281 208 movf raw_low,w 1883 282 03b movwf main__temp 1884 283 a86 goto switch__526end 1885 switch__526block555: 1886 ; Read Raw High < Command = 0000 0111 > : 1887 ; temp := raw_high 1888 284 209 movf raw_high,w 1889 285 03b movwf main__temp 1890 switch__526end: 1891 ; call send_byte {{ temp & mask }} 1892 286 c1f movlw 31 1893 287 15b andwf main__temp,w 1894 288 037 movwf send_byte__char 1895 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1896 289 4a3 bcf pa0___byte,pa0___bit 1897 28a 96b call send_byte 1898 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1899 28b 5a3 bsf pa0___byte,pa0___bit 1900 28c b26 goto switch__523end 1901 switch__523block562: 1902 ; < Command = 0000 1 xxx > : 1903 ; switch { command & 7 } 1904 28d c07 movlw 7 1905 28e 15a andwf main__command,w 1906 ; case 0 1907 ; case 1 1908 ; case 2 1909 ; case 3 1910 ; case 4 1911 ; case 5 1912 ; case 6 1913 ; case 7 1914 28f a09 goto switch__564block_start 1915 switch__564block565: 1916 ; Read Low Mask Low < Command = 0000 1000 > : 1917 ; temp := low_low 1918 ; Switch from register bank 1 to register bank 0 (which contains low_low) 1919 290 4a4 bcf rp0___byte,rp0___bit 1920 ; Register bank is now 0 1921 291 210 movf low_low,w 1922 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1923 292 5a4 bsf rp0___byte,rp0___bit 1924 ; Register bank is now 1 1925 293 03b movwf main__temp 1926 294 ab7 goto switch__564end 1927 switch__564block569: 1928 ; Read Low Mask High < Command = 0000 1001 > : 1929 ; temp := low_high 1930 ; Switch from register bank 1 to register bank 0 (which contains low_high) 1931 295 4a4 bcf rp0___byte,rp0___bit 1932 ; Register bank is now 0 1933 296 211 movf low_high,w 1934 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1935 297 5a4 bsf rp0___byte,rp0___bit 1936 ; Register bank is now 1 1937 298 03b movwf main__temp 1938 299 ab7 goto switch__564end 1939 switch__564block573: 1940 ; Read High Mask Low < Command = 0000 1010 > : 1941 ; temp := high_low 1942 ; Switch from register bank 1 to register bank 0 (which contains high_low) 1943 29a 4a4 bcf rp0___byte,rp0___bit 1944 ; Register bank is now 0 1945 29b 212 movf high_low,w 1946 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1947 29c 5a4 bsf rp0___byte,rp0___bit 1948 ; Register bank is now 1 1949 29d 03b movwf main__temp 1950 29e ab7 goto switch__564end 1951 switch__564block577: 1952 ; Read High Mask High < Command = 0000 1011 > : 1953 ; temp := high_high 1954 ; Switch from register bank 1 to register bank 0 (which contains high_high) 1955 29f 4a4 bcf rp0___byte,rp0___bit 1956 ; Register bank is now 0 1957 2a0 213 movf high_high,w 1958 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1959 2a1 5a4 bsf rp0___byte,rp0___bit 1960 ; Register bank is now 1 1961 2a2 03b movwf main__temp 1962 2a3 ab7 goto switch__564end 1963 switch__564block581: 1964 ; Read Raising Mask Low < Command = 0000 1100 > : 1965 ; temp := raising_low 1966 ; Switch from register bank 1 to register bank 0 (which contains raising_low) 1967 2a4 4a4 bcf rp0___byte,rp0___bit 1968 ; Register bank is now 0 1969 2a5 214 movf raising_low,w 1970 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1971 2a6 5a4 bsf rp0___byte,rp0___bit 1972 ; Register bank is now 1 1973 2a7 03b movwf main__temp 1974 2a8 ab7 goto switch__564end 1975 switch__564block585: 1976 ; Read Raising Mask High < Command = 0000 1101 > : 1977 ; temp := raising_high 1978 ; Switch from register bank 1 to register bank 0 (which contains raising_high) 1979 2a9 4a4 bcf rp0___byte,rp0___bit 1980 ; Register bank is now 0 1981 2aa 215 movf raising_high,w 1982 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1983 2ab 5a4 bsf rp0___byte,rp0___bit 1984 ; Register bank is now 1 1985 2ac 03b movwf main__temp 1986 2ad ab7 goto switch__564end 1987 switch__564block589: 1988 ; Read Falling Mask Low < Command = 0000 1110 > : 1989 ; temp := falling_low 1990 ; Switch from register bank 1 to register bank 0 (which contains falling_low) 1991 2ae 4a4 bcf rp0___byte,rp0___bit 1992 ; Register bank is now 0 1993 2af 216 movf falling_low,w 1994 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1995 2b0 5a4 bsf rp0___byte,rp0___bit 1996 ; Register bank is now 1 1997 2b1 03b movwf main__temp 1998 2b2 ab7 goto switch__564end 1999 switch__564block593: 2000 ; Read Falling Mask High < Command = 0000 1111 > : 2001 ; temp := falling_high 2002 ; Switch from register bank 1 to register bank 0 (which contains falling_high) 2003 2b3 4a4 bcf rp0___byte,rp0___bit 2004 ; Register bank is now 0 2005 2b4 217 movf falling_high,w 2006 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 2007 2b5 5a4 bsf rp0___byte,rp0___bit 2008 ; Register bank is now 1 2009 2b6 03b movwf main__temp 2010 switch__564end: 2011 ; call send_byte {{ temp & mask }} 2012 2b7 c1f movlw 31 2013 2b8 15b andwf main__temp,w 2014 2b9 037 movwf send_byte__char 2015 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2016 2ba 4a3 bcf pa0___byte,pa0___bit 2017 2bb 96b call send_byte 2018 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2019 2bc 5a3 bsf pa0___byte,pa0___bit 2020 2bd b26 goto switch__523end 2021 switch__523block600: 2022 ; < Command = 0001 0 xxx > : 2023 ; switch { command & 7 } 2024 2be c07 movlw 7 2025 2bf 15a andwf main__command,w 2026 ; case 0 2027 ; case 1 2028 ; case 2 2029 ; case 3 2030 ; case 4 2031 ; case 5 2032 ; case 6 2033 ; case 7 2034 2c0 a12 goto switch__602block_start 2035 switch__602block603: 2036 ; Read Outputs Low < Command = 0001 0000 > : 2037 ; call send_byte {{ outputs_low }} 2038 2c1 20c movf outputs_low,w 2039 2c2 037 movwf send_byte__char 2040 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2041 2c3 4a3 bcf pa0___byte,pa0___bit 2042 2c4 96b call send_byte 2043 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2044 2c5 5a3 bsf pa0___byte,pa0___bit 2045 2c6 af1 goto switch__602end 2046 switch__602block607: 2047 ; Read Outputs High < Command = 0001 0001 > : 2048 ; call send_byte {{ outputs_high }} 2049 2c7 20d movf outputs_high,w 2050 2c8 037 movwf send_byte__char 2051 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2052 2c9 4a3 bcf pa0___byte,pa0___bit 2053 2ca 96b call send_byte 2054 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2055 2cb 5a3 bsf pa0___byte,pa0___bit 2056 2cc af1 goto switch__602end 2057 switch__602block611: 2058 ; Set Complement Mask Low < Command = 0001 0010 > : 2059 ; complement_low := get_byte {{ }} & mask 2060 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2061 2cd 4a3 bcf pa0___byte,pa0___bit 2062 2ce 93e call get_byte 2063 2cf 214 movf get_byte__0return__byte,w 2064 2d0 e1f andlw 31 2065 2d1 02e movwf complement_low 2066 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2067 2d2 5a3 bsf pa0___byte,pa0___bit 2068 2d3 af1 goto switch__602end 2069 switch__602block615: 2070 ; Set Complement Mask High < Command = 0001 0011 > : 2071 ; complement_high := get_byte {{ }} & mask 2072 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2073 2d4 4a3 bcf pa0___byte,pa0___bit 2074 2d5 93e call get_byte 2075 2d6 214 movf get_byte__0return__byte,w 2076 2d7 e1f andlw 31 2077 2d8 02f movwf complement_high 2078 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2079 2d9 5a3 bsf pa0___byte,pa0___bit 2080 2da af1 goto switch__602end 2081 switch__602block619: 2082 ; Set Direction Mask High < Command = 0001 0100 > : 2083 ; direction_low := get_byte {{ }} & mask 2084 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2085 2db 4a3 bcf pa0___byte,pa0___bit 2086 2dc 93e call get_byte 2087 2dd 214 movf get_byte__0return__byte,w 2088 2de e1f andlw 31 2089 2df 030 movwf direction_low 2090 ; call direction_set {{ }} 2091 2e0 99e call direction_set 2092 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2093 2e1 5a3 bsf pa0___byte,pa0___bit 2094 2e2 af1 goto switch__602end 2095 switch__602block624: 2096 ; Set Direction Mask High < Command = 0001 0101 > : 2097 ; direction_high := get_byte {{ }} & mask 2098 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2099 2e3 4a3 bcf pa0___byte,pa0___bit 2100 2e4 93e call get_byte 2101 2e5 214 movf get_byte__0return__byte,w 2102 2e6 e1f andlw 31 2103 2e7 031 movwf direction_high 2104 ; call direction_set {{ }} 2105 2e8 99e call direction_set 2106 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2107 2e9 5a3 bsf pa0___byte,pa0___bit 2108 2ea af1 goto switch__602end 2109 switch__602block629: 2110 ; Reset Everything < Command = 0001 0110 > : 2111 ; outputs_low := 0 2112 2eb 06c clrf outputs_low 2113 ; outputs_high := 0 2114 2ec 06d clrf outputs_high 2115 2ed af1 goto switch__602end 2116 switch__602block634: 2117 ; Reset Everything < Command = 0001 0110 > : 2118 ; call reset {{ }} 2119 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2120 2ee 4a3 bcf pa0___byte,pa0___bit 2121 2ef 9ba call reset 2122 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2123 2f0 5a3 bsf pa0___byte,pa0___bit 2124 switch__602end: 2125 2f1 b26 goto switch__523end 2126 switch__523block640: 2127 ; < Command = 0001 1 xxx > : 2128 ; temp := get_byte {{ }} & mask 2129 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2130 2f2 4a3 bcf pa0___byte,pa0___bit 2131 2f3 93e call get_byte 2132 2f4 214 movf get_byte__0return__byte,w 2133 2f5 e1f andlw 31 2134 2f6 03b movwf main__temp 2135 ; switch { command & 7 } 2136 2f7 c07 movlw 7 2137 2f8 15a andwf main__command,w 2138 ; case 0 2139 ; case 1 2140 ; case 2 2141 ; case 3 2142 ; case 4 2143 ; case 5 2144 ; case 6 2145 ; case 7 2146 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2147 2f9 5a3 bsf pa0___byte,pa0___bit 2148 2fa a1b goto switch__643block_start 2149 switch__643block644: 2150 ; Set Low Mask Low < Command = 0001 1000 > : 2151 ; low_low := temp 2152 2fb 21b movf main__temp,w 2153 ; Switch from register bank 1 to register bank 0 (which contains low_low) 2154 2fc 4a4 bcf rp0___byte,rp0___bit 2155 ; Register bank is now 0 2156 2fd 030 movwf low_low 2157 ; Switch from register bank 0 to register bank 1 2158 2fe 5a4 bsf rp0___byte,rp0___bit 2159 ; Register bank is now 1 2160 2ff b22 goto switch__643end 2161 switch__643block648: 2162 ; Set Low Mask High < Command = 0001 1001 > : 2163 ; low_high := temp 2164 300 21b movf main__temp,w 2165 ; Switch from register bank 1 to register bank 0 (which contains low_high) 2166 301 4a4 bcf rp0___byte,rp0___bit 2167 ; Register bank is now 0 2168 302 031 movwf low_high 2169 ; Switch from register bank 0 to register bank 1 2170 303 5a4 bsf rp0___byte,rp0___bit 2171 ; Register bank is now 1 2172 304 b22 goto switch__643end 2173 switch__643block652: 2174 ; Set High Mask Low < Command = 0001 1010 > : 2175 ; high_low := temp 2176 305 21b movf main__temp,w 2177 ; Switch from register bank 1 to register bank 0 (which contains high_low) 2178 306 4a4 bcf rp0___byte,rp0___bit 2179 ; Register bank is now 0 2180 307 032 movwf high_low 2181 ; Switch from register bank 0 to register bank 1 2182 308 5a4 bsf rp0___byte,rp0___bit 2183 ; Register bank is now 1 2184 309 b22 goto switch__643end 2185 switch__643block656: 2186 ; Set High Mask High < Command = 0001 1011 > : 2187 ; high_high := temp 2188 30a 21b movf main__temp,w 2189 ; Switch from register bank 1 to register bank 0 (which contains high_high) 2190 30b 4a4 bcf rp0___byte,rp0___bit 2191 ; Register bank is now 0 2192 30c 033 movwf high_high 2193 ; Switch from register bank 0 to register bank 1 2194 30d 5a4 bsf rp0___byte,rp0___bit 2195 ; Register bank is now 1 2196 30e b22 goto switch__643end 2197 switch__643block660: 2198 ; Set Raising Mask Low < Command = 0001 1100 > : 2199 ; raising_low := temp 2200 30f 21b movf main__temp,w 2201 ; Switch from register bank 1 to register bank 0 (which contains raising_low) 2202 310 4a4 bcf rp0___byte,rp0___bit 2203 ; Register bank is now 0 2204 311 034 movwf raising_low 2205 ; Switch from register bank 0 to register bank 1 2206 312 5a4 bsf rp0___byte,rp0___bit 2207 ; Register bank is now 1 2208 313 b22 goto switch__643end 2209 switch__643block664: 2210 ; Set Raising Mask High < Command = 0001 1101 > : 2211 ; raising_high := temp 2212 314 21b movf main__temp,w 2213 ; Switch from register bank 1 to register bank 0 (which contains raising_high) 2214 315 4a4 bcf rp0___byte,rp0___bit 2215 ; Register bank is now 0 2216 316 035 movwf raising_high 2217 ; Switch from register bank 0 to register bank 1 2218 317 5a4 bsf rp0___byte,rp0___bit 2219 ; Register bank is now 1 2220 318 b22 goto switch__643end 2221 switch__643block668: 2222 ; Set Falling Mask Low < Command = 0001 1110 > : 2223 ; falling_low := temp 2224 319 21b movf main__temp,w 2225 ; Switch from register bank 1 to register bank 0 (which contains falling_low) 2226 31a 4a4 bcf rp0___byte,rp0___bit 2227 ; Register bank is now 0 2228 31b 036 movwf falling_low 2229 ; Switch from register bank 0 to register bank 1 2230 31c 5a4 bsf rp0___byte,rp0___bit 2231 ; Register bank is now 1 2232 31d b22 goto switch__643end 2233 switch__643block672: 2234 ; Set Falling Mask High < Command = 0001 1111 > : 2235 ; falling_high := temp 2236 31e 21b movf main__temp,w 2237 ; Switch from register bank 1 to register bank 0 (which contains falling_high) 2238 31f 4a4 bcf rp0___byte,rp0___bit 2239 ; Register bank is now 0 2240 320 037 movwf falling_high 2241 ; Switch from register bank 0 to register bank 1 2242 321 5a4 bsf rp0___byte,rp0___bit 2243 ; Register bank is now 1 2244 switch__643end: 2245 322 b26 goto switch__523end 2246 switch__523block678: 2247 ; Set Outputs Low < Command = 001 x xxxx > : 2248 ; outputs_low := command & mask 2249 323 c1f movlw 31 2250 324 15a andwf main__command,w 2251 325 02c movwf outputs_low 2252 switch__523end: 2253 326 be3 goto switch__520end 2254 switch__520block684: 2255 ; < Command = 01 xx xxxx > : 2256 ; if { command @ 5 } start 2257 ; Alias variable for select command @ 5 2258 003a main__command__686select0 equ main__command+0 2259 003a main__command__686select0__byte equ main__command+0 2260 0005 main__command__686select0__bit equ 5 2261 ; expression=`{ command @ 5 }' exp_delay=0 true_delay=94 false_delay=3 true_size=83 false_size=3 2262 327 6ba btfsc main__command__686select0__byte,main__command__686select0__bit 2263 328 b2d goto label686__1true 2264 label686__1false: 2265 ; else body start 2266 ; Set Outputs High < Command = 010 o oooo > : 2267 ; outputs_high := command & mask 2268 329 c1f movlw 31 2269 32a 15a andwf main__command,w 2270 32b 02d movwf outputs_high 2271 ; else body end 2272 32c b7f goto label686__1end 2273 label686__1true: 2274 ; if { command @ 5 } body start 2275 ; Set Output Bit < Command = 011 v bbbb > : 2276 ; switch { command & 15 } 2277 32d c0f movlw 15 2278 32e 15a andwf main__command,w 2279 ; case 0 2280 ; case 1 2281 ; case 2 2282 ; case 3 2283 ; case 4 2284 ; case 5 2285 ; case 6 2286 ; case 7 2287 ; case 8 2288 ; case 9 2289 32f a2d goto switch__688block_start 2290 switch__688block689: 2291 ; outputs_low @ 0 := command @ 4 2292 ; Alias variable for select command @ 4 2293 003a main__command__690select2 equ main__command+0 2294 003a main__command__690select2__byte equ main__command+0 2295 0004 main__command__690select2__bit equ 4 2296 330 41d bcf main__690bit1__byte,main__690bit1__bit 2297 331 69a btfsc main__command__690select2__byte,main__command__690select2__bit 2298 332 51d bsf main__690bit1__byte,main__690bit1__bit 2299 ; Select variable outputs_low @ 0 2300 000c outputs_low__690select3 equ outputs_low+0 2301 000c outputs_low__690select3__byte equ outputs_low+0 2302 0000 outputs_low__690select3__bit equ 0 2303 333 71d btfss main__690bit1__byte,main__690bit1__bit 2304 334 40c bcf outputs_low__690select3__byte,outputs_low__690select3__bit 2305 335 61d btfsc main__690bit1__byte,main__690bit1__bit 2306 336 50c bsf outputs_low__690select3__byte,outputs_low__690select3__bit 2307 337 b7f goto switch__688end 2308 switch__688block692: 2309 ; outputs_low @ 1 := command @ 4 2310 ; Alias variable for select command @ 4 2311 003a main__command__693select2 equ main__command+0 2312 003a main__command__693select2__byte equ main__command+0 2313 0004 main__command__693select2__bit equ 4 2314 338 41d bcf main__693bit1__byte,main__693bit1__bit 2315 339 69a btfsc main__command__693select2__byte,main__command__693select2__bit 2316 33a 51d bsf main__693bit1__byte,main__693bit1__bit 2317 ; Select variable outputs_low @ 1 2318 000c outputs_low__693select3 equ outputs_low+0 2319 000c outputs_low__693select3__byte equ outputs_low+0 2320 0001 outputs_low__693select3__bit equ 1 2321 33b 71d btfss main__693bit1__byte,main__693bit1__bit 2322 33c 42c bcf outputs_low__693select3__byte,outputs_low__693select3__bit 2323 33d 61d btfsc main__693bit1__byte,main__693bit1__bit 2324 33e 52c bsf outputs_low__693select3__byte,outputs_low__693select3__bit 2325 33f b7f goto switch__688end 2326 switch__688block695: 2327 ; outputs_low @ 2 := command @ 4 2328 ; Alias variable for select command @ 4 2329 003a main__command__696select2 equ main__command+0 2330 003a main__command__696select2__byte equ main__command+0 2331 0004 main__command__696select2__bit equ 4 2332 340 41d bcf main__696bit1__byte,main__696bit1__bit 2333 341 69a btfsc main__command__696select2__byte,main__command__696select2__bit 2334 342 51d bsf main__696bit1__byte,main__696bit1__bit 2335 ; Select variable outputs_low @ 2 2336 000c outputs_low__696select3 equ outputs_low+0 2337 000c outputs_low__696select3__byte equ outputs_low+0 2338 0002 outputs_low__696select3__bit equ 2 2339 343 71d btfss main__696bit1__byte,main__696bit1__bit 2340 344 44c bcf outputs_low__696select3__byte,outputs_low__696select3__bit 2341 345 61d btfsc main__696bit1__byte,main__696bit1__bit 2342 346 54c bsf outputs_low__696select3__byte,outputs_low__696select3__bit 2343 347 b7f goto switch__688end 2344 switch__688block698: 2345 ; outputs_low @ 3 := command @ 4 2346 ; Alias variable for select command @ 4 2347 003a main__command__699select2 equ main__command+0 2348 003a main__command__699select2__byte equ main__command+0 2349 0004 main__command__699select2__bit equ 4 2350 348 41d bcf main__699bit1__byte,main__699bit1__bit 2351 349 69a btfsc main__command__699select2__byte,main__command__699select2__bit 2352 34a 51d bsf main__699bit1__byte,main__699bit1__bit 2353 ; Select variable outputs_low @ 3 2354 000c outputs_low__699select3 equ outputs_low+0 2355 000c outputs_low__699select3__byte equ outputs_low+0 2356 0003 outputs_low__699select3__bit equ 3 2357 34b 71d btfss main__699bit1__byte,main__699bit1__bit 2358 34c 46c bcf outputs_low__699select3__byte,outputs_low__699select3__bit 2359 34d 61d btfsc main__699bit1__byte,main__699bit1__bit 2360 34e 56c bsf outputs_low__699select3__byte,outputs_low__699select3__bit 2361 34f b7f goto switch__688end 2362 switch__688block701: 2363 ; outputs_low @ 4 := command @ 4 2364 ; Alias variable for select command @ 4 2365 003a main__command__702select2 equ main__command+0 2366 003a main__command__702select2__byte equ main__command+0 2367 0004 main__command__702select2__bit equ 4 2368 350 41d bcf main__702bit1__byte,main__702bit1__bit 2369 351 69a btfsc main__command__702select2__byte,main__command__702select2__bit 2370 352 51d bsf main__702bit1__byte,main__702bit1__bit 2371 ; Select variable outputs_low @ 4 2372 000c outputs_low__702select3 equ outputs_low+0 2373 000c outputs_low__702select3__byte equ outputs_low+0 2374 0004 outputs_low__702select3__bit equ 4 2375 353 71d btfss main__702bit1__byte,main__702bit1__bit 2376 354 48c bcf outputs_low__702select3__byte,outputs_low__702select3__bit 2377 355 61d btfsc main__702bit1__byte,main__702bit1__bit 2378 356 58c bsf outputs_low__702select3__byte,outputs_low__702select3__bit 2379 357 b7f goto switch__688end 2380 switch__688block704: 2381 ; outputs_high @ 0 := command @ 4 2382 ; Alias variable for select command @ 4 2383 003a main__command__705select2 equ main__command+0 2384 003a main__command__705select2__byte equ main__command+0 2385 0004 main__command__705select2__bit equ 4 2386 358 41d bcf main__705bit1__byte,main__705bit1__bit 2387 359 69a btfsc main__command__705select2__byte,main__command__705select2__bit 2388 35a 51d bsf main__705bit1__byte,main__705bit1__bit 2389 ; Select variable outputs_high @ 0 2390 000d outputs_high__705select3 equ outputs_high+0 2391 000d outputs_high__705select3__byte equ outputs_high+0 2392 0000 outputs_high__705select3__bit equ 0 2393 35b 71d btfss main__705bit1__byte,main__705bit1__bit 2394 35c 40d bcf outputs_high__705select3__byte,outputs_high__705select3__bit 2395 35d 61d btfsc main__705bit1__byte,main__705bit1__bit 2396 35e 50d bsf outputs_high__705select3__byte,outputs_high__705select3__bit 2397 35f b7f goto switch__688end 2398 switch__688block707: 2399 ; outputs_high @ 1 := command @ 4 2400 ; Alias variable for select command @ 4 2401 003a main__command__708select2 equ main__command+0 2402 003a main__command__708select2__byte equ main__command+0 2403 0004 main__command__708select2__bit equ 4 2404 360 41d bcf main__708bit1__byte,main__708bit1__bit 2405 361 69a btfsc main__command__708select2__byte,main__command__708select2__bit 2406 362 51d bsf main__708bit1__byte,main__708bit1__bit 2407 ; Select variable outputs_high @ 1 2408 000d outputs_high__708select3 equ outputs_high+0 2409 000d outputs_high__708select3__byte equ outputs_high+0 2410 0001 outputs_high__708select3__bit equ 1 2411 363 71d btfss main__708bit1__byte,main__708bit1__bit 2412 364 42d bcf outputs_high__708select3__byte,outputs_high__708select3__bit 2413 365 61d btfsc main__708bit1__byte,main__708bit1__bit 2414 366 52d bsf outputs_high__708select3__byte,outputs_high__708select3__bit 2415 367 b7f goto switch__688end 2416 switch__688block710: 2417 ; outputs_high @ 2 := command @ 4 2418 ; Alias variable for select command @ 4 2419 003a main__command__711select2 equ main__command+0 2420 003a main__command__711select2__byte equ main__command+0 2421 0004 main__command__711select2__bit equ 4 2422 368 41d bcf main__711bit1__byte,main__711bit1__bit 2423 369 69a btfsc main__command__711select2__byte,main__command__711select2__bit 2424 36a 51d bsf main__711bit1__byte,main__711bit1__bit 2425 ; Select variable outputs_high @ 2 2426 000d outputs_high__711select3 equ outputs_high+0 2427 000d outputs_high__711select3__byte equ outputs_high+0 2428 0002 outputs_high__711select3__bit equ 2 2429 36b 71d btfss main__711bit1__byte,main__711bit1__bit 2430 36c 44d bcf outputs_high__711select3__byte,outputs_high__711select3__bit 2431 36d 61d btfsc main__711bit1__byte,main__711bit1__bit 2432 36e 54d bsf outputs_high__711select3__byte,outputs_high__711select3__bit 2433 36f b7f goto switch__688end 2434 switch__688block713: 2435 ; outputs_high @ 3 := command @ 4 2436 ; Alias variable for select command @ 4 2437 003a main__command__714select2 equ main__command+0 2438 003a main__command__714select2__byte equ main__command+0 2439 0004 main__command__714select2__bit equ 4 2440 370 41d bcf main__714bit1__byte,main__714bit1__bit 2441 371 69a btfsc main__command__714select2__byte,main__command__714select2__bit 2442 372 51d bsf main__714bit1__byte,main__714bit1__bit 2443 ; Select variable outputs_high @ 3 2444 000d outputs_high__714select3 equ outputs_high+0 2445 000d outputs_high__714select3__byte equ outputs_high+0 2446 0003 outputs_high__714select3__bit equ 3 2447 373 71d btfss main__714bit1__byte,main__714bit1__bit 2448 374 46d bcf outputs_high__714select3__byte,outputs_high__714select3__bit 2449 375 61d btfsc main__714bit1__byte,main__714bit1__bit 2450 376 56d bsf outputs_high__714select3__byte,outputs_high__714select3__bit 2451 377 b7f goto switch__688end 2452 switch__688block716: 2453 ; outputs_high @ 4 := command @ 4 2454 ; Alias variable for select command @ 4 2455 003a main__command__717select2 equ main__command+0 2456 003a main__command__717select2__byte equ main__command+0 2457 0004 main__command__717select2__bit equ 4 2458 378 41d bcf main__717bit1__byte,main__717bit1__bit 2459 379 69a btfsc main__command__717select2__byte,main__command__717select2__bit 2460 37a 51d bsf main__717bit1__byte,main__717bit1__bit 2461 ; Select variable outputs_high @ 4 2462 000d outputs_high__717select3 equ outputs_high+0 2463 000d outputs_high__717select3__byte equ outputs_high+0 2464 0004 outputs_high__717select3__bit equ 4 2465 37b 71d btfss main__717bit1__byte,main__717bit1__bit 2466 37c 48d bcf outputs_high__717select3__byte,outputs_high__717select3__bit 2467 37d 61d btfsc main__717bit1__byte,main__717bit1__bit 2468 37e 58d bsf outputs_high__717select3__byte,outputs_high__717select3__bit 2469 switch__688end: 2470 ; if { command @ 5 } body end 2471 ; if exp=` command @ 5 ' generic 2472 label686__1end: 2473 ; Other expression=`{ command @ 5 }' delay=-1 2474 ; if { command @ 5 } end 2475 37f be3 goto switch__520end 2476 switch__520block725: 2477 ; < Command = 10 xx xxxx > : 2478 ; Do nothing : 2479 380 be3 goto switch__520end 2480 switch__520block729: 2481 ; < Command = 11 xx xxxx > : 2482 ; switch { {{ command >> 3 }} & 7 } 2483 381 31a rrf main__command,w 2484 382 03c movwf main__731byte0 2485 383 33c rrf main__731byte0,f 2486 384 31c rrf main__731byte0,w 2487 385 e07 andlw 7 2488 ; case 0 1 2 3 4 2489 ; case 5 2490 ; case 6 2491 ; case 7 2492 386 a4a goto switch__731block_start 2493 switch__731block732: 2494 ; < Command = 110 x xxxx or 1110 0 xxx > : 2495 ; Do nothing : 2496 387 be3 goto switch__731end 2497 switch__731block736: 2498 ; < Command = 1110 1 xxx > : 2499 ; if { command = 0xef } start 2500 388 cef movlw 239 2501 389 09a subwf main__command,w 2502 ; expression=`{ command = 0xef }' exp_delay=2 true_delay=6 false_delay=0 true_size=8 false_size=0 2503 38a 743 btfss z___byte,z___bit 2504 38b b98 goto label738__0end 2505 ; if { command = 0xef } body start 2506 ; Read Interrupt Bits < Command = 1110 1111 > : 2507 ; temporary := 0 2508 ; Switch from register bank 1 to register bank 0 (which contains temporary) 2509 38c 4a4 bcf rp0___byte,rp0___bit 2510 ; Register bank is now 0 2511 38d 078 clrf temporary 2512 ; if { interrupt_pending } start 2513 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2514 38e 63e btfsc interrupt_pending__byte,interrupt_pending__bit 2515 ; if { interrupt_pending } body start 2516 ; temporary @ 0 := 1 2517 ; Select temporary @ 0 2518 0018 temporary__742select0 equ temporary+0 2519 0018 temporary__742select0__byte equ temporary+0 2520 0000 temporary__742select0__bit equ 0 2521 38f 518 bsf temporary__742select0__byte,temporary__742select0__bit 2522 ; if { interrupt_pending } body end 2523 ; if exp=`interrupt_pending' false skip delay=2 2524 ; Other expression=`{ interrupt_pending }' delay=2 2525 ; if { interrupt_pending } end 2526 ; if { interrupt_enable } start 2527 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2528 390 61e btfsc interrupt_enable__byte,interrupt_enable__bit 2529 ; if { interrupt_enable } body start 2530 ; temporary @ 1 := 1 2531 ; Select temporary @ 1 2532 0018 temporary__745select0 equ temporary+0 2533 0018 temporary__745select0__byte equ temporary+0 2534 0001 temporary__745select0__bit equ 1 2535 391 538 bsf temporary__745select0__byte,temporary__745select0__bit 2536 ; if { interrupt_enable } body end 2537 ; if exp=`interrupt_enable' false skip delay=2 2538 ; Other expression=`{ interrupt_enable }' delay=2 2539 ; if { interrupt_enable } end 2540 ; call send_byte {{ temporary }} 2541 392 218 movf temporary,w 2542 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2543 393 5a4 bsf rp0___byte,rp0___bit 2544 ; Register bank is now 1 2545 394 037 movwf send_byte__char 2546 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2547 395 4a3 bcf pa0___byte,pa0___bit 2548 396 96b call send_byte 2549 ; if { command = 0xef } body end 2550 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 2551 397 5a3 bsf pa0___byte,pa0___bit 2552 label738__0end: 2553 ; if exp=` command = 0xef ' empty false 2554 ; Other expression=`{ command = 0xef }' delay=-1 2555 ; if { command = 0xef } end 2556 398 be3 goto switch__731end 2557 switch__731block750: 2558 ; < Command = 1111 0 xxx > : 2559 ; Switching between register banks generates bulky code ; 2560 ; Keep code generation in bank 0 by assigning command to 2561 ; temporary : 2562 ; temporary := command 2563 399 21a movf main__command,w 2564 ; Switch from register bank 1 to register bank 0 (which contains temporary) 2565 39a 4a4 bcf rp0___byte,rp0___bit 2566 ; Register bank is now 0 2567 39b 038 movwf temporary 2568 ; switch { temporary & 7 } 2569 39c c07 movlw 7 2570 39d 158 andwf temporary,w 2571 ; case 0 1 2 3 2572 ; case 4 5 2573 ; case 6 7 2574 ; Switch from register bank 0 to register bank 1 2575 39e 5a4 bsf rp0___byte,rp0___bit 2576 ; Register bank is now 1 2577 39f a38 goto switch__756block_start 2578 switch__756block757: 2579 ; Set Interrupt Bits < Command = 1111 00 ep > : 2580 ; interrupt_enable := temporary @ 1 2581 ; Alias variable for select temporary @ 1 2582 0018 temporary__759select0 equ temporary+0 2583 0018 temporary__759select0__byte equ temporary+0 2584 0001 temporary__759select0__bit equ 1 2585 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 2586 3a0 4a4 bcf rp0___byte,rp0___bit 2587 ; Register bank is now 0 2588 3a1 41e bcf interrupt_enable__byte,interrupt_enable__bit 2589 3a2 638 btfsc temporary__759select0__byte,temporary__759select0__bit 2590 3a3 51e bsf interrupt_enable__byte,interrupt_enable__bit 2591 ; interrupt_pending := temporary @ 0 2592 ; Alias variable for select temporary @ 0 2593 0018 temporary__760select0 equ temporary+0 2594 0018 temporary__760select0__byte equ temporary+0 2595 0000 temporary__760select0__bit equ 0 2596 3a4 43e bcf interrupt_pending__byte,interrupt_pending__bit 2597 3a5 618 btfsc temporary__760select0__byte,temporary__760select0__bit 2598 3a6 53e bsf interrupt_pending__byte,interrupt_pending__bit 2599 ; Switch from register bank 0 to register bank 1 2600 3a7 5a4 bsf rp0___byte,rp0___bit 2601 ; Register bank is now 1 2602 3a8 bb4 goto switch__756end 2603 switch__756block762: 2604 ; Set Interrupt Pending < Command = 1111 010 p > : 2605 ; interrupt_pending := temporary @ 0 2606 ; Alias variable for select temporary @ 0 2607 0018 temporary__764select0 equ temporary+0 2608 0018 temporary__764select0__byte equ temporary+0 2609 0000 temporary__764select0__bit equ 0 2610 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 2611 3a9 4a4 bcf rp0___byte,rp0___bit 2612 ; Register bank is now 0 2613 3aa 43e bcf interrupt_pending__byte,interrupt_pending__bit 2614 3ab 618 btfsc temporary__764select0__byte,temporary__764select0__bit 2615 3ac 53e bsf interrupt_pending__byte,interrupt_pending__bit 2616 ; Switch from register bank 0 to register bank 1 2617 3ad 5a4 bsf rp0___byte,rp0___bit 2618 ; Register bank is now 1 2619 3ae bb4 goto switch__756end 2620 switch__756block766: 2621 ; Set Interrupt Enable < Command = 1111 011 e > : 2622 ; interrupt_enable := temporary @ 0 2623 ; Alias variable for select temporary @ 0 2624 0018 temporary__768select0 equ temporary+0 2625 0018 temporary__768select0__byte equ temporary+0 2626 0000 temporary__768select0__bit equ 0 2627 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 2628 3af 4a4 bcf rp0___byte,rp0___bit 2629 ; Register bank is now 0 2630 3b0 41e bcf interrupt_enable__byte,interrupt_enable__bit 2631 3b1 618 btfsc temporary__768select0__byte,temporary__768select0__bit 2632 3b2 51e bsf interrupt_enable__byte,interrupt_enable__bit 2633 ; Switch from register bank 0 to register bank 1 2634 3b3 5a4 bsf rp0___byte,rp0___bit 2635 ; Register bank is now 1 2636 switch__756end: 2637 3b4 be3 goto switch__731end 2638 switch__731block772: 2639 ; switch { command & 7 } 2640 3b5 c07 movlw 7 2641 3b6 15a andwf main__command,w 2642 ; case 0 2643 ; case 1 2644 ; case 2 2645 ; case 3 2646 ; case 4 2647 ; case 5 2648 ; case 6 2649 ; case 7 2650 3b7 a41 goto switch__773block_start 2651 switch__773block774: 2652 ; Clock Decrement < Command = 1111 1000 > : 2653 ; osccal := osccal - osccal_lsb 2654 3b8 cfc movlw 252 2655 3b9 1e5 addwf osccal,f 2656 3ba be3 goto switch__773end 2657 switch__773block778: 2658 ; Clock Increment < Command = 1111 1001 > : 2659 ; osccal := osccal + osccal_lsb 2660 3bb c04 movlw 4 2661 3bc 1e5 addwf osccal,f 2662 3bd be3 goto switch__773end 2663 switch__773block782: 2664 ; Clock Read < Command = 1111 1010 > : 2665 ; call send_byte {{ osccal }} 2666 3be 205 movf osccal,w 2667 3bf 037 movwf send_byte__char 2668 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2669 3c0 4a3 bcf pa0___byte,pa0___bit 2670 3c1 96b call send_byte 2671 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2672 3c2 5a3 bsf pa0___byte,pa0___bit 2673 3c3 be3 goto switch__773end 2674 switch__773block786: 2675 ; Clock Pulse < Command = 1111 1011 > : 2676 ; call send_byte {{ 0 }} 2677 3c4 077 clrf send_byte__char 2678 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2679 3c5 4a3 bcf pa0___byte,pa0___bit 2680 3c6 96b call send_byte 2681 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2682 3c7 5a3 bsf pa0___byte,pa0___bit 2683 3c8 be3 goto switch__773end 2684 switch__773block790: 2685 ; ID Next < Command = 1111 1100 > : 2686 ; call send_byte {{ id ~~ {{ index }} }} 2687 3c9 293 incf index,w 2688 ; Switch from register bank 1 to register bank 0 2689 3ca 4a4 bcf rp0___byte,rp0___bit 2690 ; Register bank is now 0 2691 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2692 3cb 4a3 bcf pa0___byte,pa0___bit 2693 3cc 90b call id 2694 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2695 3cd 5a4 bsf rp0___byte,rp0___bit 2696 ; Register bank is now 1 2697 3ce 037 movwf send_byte__char 2698 3cf 96b call send_byte 2699 ; index := index + 1 2700 3d0 2b3 incf index,f 2701 ; if { index >= id . size } start 2702 3d1 c31 movlw 49 2703 3d2 093 subwf index,w 2704 ; expression=`{ index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2705 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) 2706 3d3 5a3 bsf pa0___byte,pa0___bit 2707 3d4 603 btfsc c___byte,c___bit 2708 ; if { index >= id . size } body start 2709 ; index := 0 2710 3d5 073 clrf index 2711 ; if { index >= id . size } body end 2712 ; if exp=` index >= id . size ' false skip delay=4 2713 ; Other expression=`{ index >= id . size }' delay=4 2714 ; if { index >= id . size } end 2715 3d6 be3 goto switch__773end 2716 switch__773block798: 2717 ; ID Reset < Command = 1111 1101 > : 2718 ; index := 0 2719 3d7 073 clrf index 2720 3d8 be3 goto switch__773end 2721 switch__773block802: 2722 ; Glitch Read < Command = 1111 1110 > : 2723 ; call send_byte {{ glitch }} 2724 3d9 212 movf glitch,w 2725 3da 037 movwf send_byte__char 2726 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2727 3db 4a3 bcf pa0___byte,pa0___bit 2728 3dc 96b call send_byte 2729 ; glitch := 0 2730 3dd 072 clrf glitch 2731 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2732 3de 5a3 bsf pa0___byte,pa0___bit 2733 3df be3 goto switch__773end 2734 switch__773block807: 2735 ; Glitch < Command = 1111 1111 > : 2736 ; if { glitch != 0xff } start 2737 3e0 292 incf glitch,w 2738 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 2739 3e1 743 btfss z___byte,z___bit 2740 ; if { glitch != 0xff } body start 2741 ; glitch := glitch + 1 2742 3e2 2b2 incf glitch,f 2743 ; if { glitch != 0xff } body end 2744 ; if exp=` glitch != 0xff ' false skip delay=3 2745 ; Other expression=`{ glitch != 0xff }' delay=3 2746 ; if { glitch != 0xff } end 2747 switch__773end: 2748 switch__731end: 2749 switch__520end: 2750 3e3 a5b goto main__515loop__forever 2751 ; loop_forever ... end 2752 ; procedure main end 2753 2754 ; Register bank 0 used 22 bytes of 24 available bytes 2755 ; Register bank 1 used 14 bytes of 16 available bytes 2756 ; Register bank 2 used 0 bytes of 16 available bytes 2757 ; Register bank 3 used 0 bytes of 16 available bytes 2758 2759 end