radix dec global__variables__bank0 equ 8 global__variables__bank1 equ 48 global__variables__bank2 equ 80 global__variables__bank3 equ 112 global__bit__variables__bank0 equ 30 global__bit__variables__bank1 equ 62 global__bit__variables__bank2 equ 80 global__bit__variables__bank3 equ 112 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers movlw 251 tris 6 movlw 255 tris 7 ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich and Bill Benson} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the Out10 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / out10 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock ; 4052=0xfd4 4095=0xfff __config 4052 configuration___address equ 4095 ; comment {Define processor constants :} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {Define serial communication control constants :} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; constant extra_instructions_per_bit 9 extra_instructions_per_bit equ 9 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit extra_instructions_per_delay equ 3 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay delay_instructions equ 135 ; comment {Register definitions :} ; comment {Status register :} status equ 3 ; bind c status @ 0 c equ status+0 c__byte equ status+0 c__bit equ 0 ; bind z status @ 2 z equ status+0 z__byte equ status+0 z__bit equ 2 ; comment {OSCCAL register :} osccal equ 5 ; constant osccal_lsb 4 osccal_lsb equ 4 ; comment {Define bit offsets :} ; constant io0_bit 0 io0_bit equ 0 ; constant io1_bit 1 io1_bit equ 1 ; constant io2_bit 2 io2_bit equ 2 ; constant io3_bit 3 io3_bit equ 3 ; constant io4_bit 4 io4_bit equ 4 ; constant io5_bit 5 io5_bit equ 5 ; constant io6_bit 4 io6_bit equ 4 ; constant io7_bit 5 io7_bit equ 5 ; constant io8_bit 0 io8_bit equ 0 ; constant io9_bit 1 io9_bit equ 1 ; constant serial_out_bit 2 serial_out_bit equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; comment {Define pin assignments and directions :} ; comment {Techically , the pins are all read_write_manual , but it} ; comment {is easier to do all of the tris register manipulation} ; comment {by hand rather than using uCL { direction } commands . We} ; comment {start with all the I / O pins set to read - only until such} ; comment {time as the user explicitly sets them to outputs :} portb equ 6 portc equ 7 io9__byte equ 6 io9__bit equ 1 io8__byte equ 6 io8__bit equ 0 io7__byte equ 6 io7__bit equ 5 io6__byte equ 6 io6__bit equ 4 io5__byte equ 7 io5__bit equ 5 io4__byte equ 7 io4__bit equ 4 io3__byte equ 7 io3__bit equ 3 io2__byte equ 7 io2__bit equ 2 io1__byte equ 7 io1__bit equ 1 io0__byte equ 7 io0__bit equ 0 serial_out__byte equ 6 serial_out__bit equ 2 serial_in__byte equ 6 serial_in__bit equ 3 ; constant mask 0x1f mask equ 31 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 13 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 8 , 0s'InOut10A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 49 retlw 49 ; 1 retlw 1 ; 0 retlw 0 ; 13 retlw 13 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 231 ; random number retlw 239 ; random number retlw 248 ; random number retlw 249 ; random number retlw 181 ; random number retlw 36 ; random number retlw 4 ; random number retlw 109 ; random number retlw 58 ; random number retlw 74 ; random number retlw 111 ; random number retlw 74 ; random number retlw 122 ; random number retlw 181 ; random number retlw 106 ; random number retlw 254 ; random number ; 8 retlw 8 ; `InOut10A' retlw 73 retlw 110 retlw 79 retlw 117 retlw 116 retlw 49 retlw 48 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; comment {Some globals : byte} raw_low equ global__variables__bank0+0 raw_high equ global__variables__bank0+1 inputs_low equ global__variables__bank0+2 inputs_high equ global__variables__bank0+3 outputs_low equ global__variables__bank0+4 outputs_high equ global__variables__bank0+5 complement_low equ global__variables__bank0+6 complement_high equ global__variables__bank0+7 low_low equ global__variables__bank0+8 low_high equ global__variables__bank0+9 high_low equ global__variables__bank0+10 high_high equ global__variables__bank0+11 raising_low equ global__variables__bank0+12 raising_high equ global__variables__bank0+13 falling_low equ global__variables__bank0+14 falling_high equ global__variables__bank0+15 temporary equ global__variables__bank0+16 interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 ; bank 1 ; Default register bank is now 1 direction_low equ global__variables__bank1+0 direction_high equ global__variables__bank1+1 glitch equ global__variables__bank1+2 index equ global__variables__bank1+3 ; comment {Note that the 12 - bit PIC ' s only have a 2 - level deep stack .} ; comment {The code starts in the main procedure < located at the end of this code >} ; comment {The next level of procedure call is either get_byte or send_byte .} ; comment {Lastly , the lowest level of procedure call is delay . It all fits ,} ; comment {but just barely .} ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank1+4 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; This procedure will wait for a byte to be received from ; serial_in_bit . It calls the delay procedure for all delays . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Why does the delay procedure wait for a third of bit ? Well , it ; has to do with the loop immediately below . If we catch the ; start bit at the beginning of a 1 / 3 bit time , we will be ; sampling data at approximately 1 / 3 of the way into each bit . ; Conversely , if we catch the start near the end of a 1 / 3 bit ; bit time , we will be sampling data at approximately 2 / 3 of the ; way into each bit . So , what this means is that our bit sample ; times will be somewhere between 1 / 3 and 2 / 3 of bit < i . e . in ; the middle of the bit . ; It would be nice to tweak the code to shorter delay times ; < 1 / 4 bit , 1 / 5 bit , etc . > but then it gets too hard to get ; the bookeeping done in the delay routine . A 12 - bit PIC ; running at 4 MHz <= 1 MIPS > , only has 138 instructions available ; for the delay routine when at 1 / 3 of bit . ; Wait for a start bit : ; receiving := 1 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bsf receiving__byte,receiving__bit ; `while serial_in ...' start ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 get_byte__155while__continue: ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__155while__break ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto get_byte__155while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__155while__break: ; `while serial_in ...' end ; Clear interrupt : ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit ; ; 1 cycle : ; char := 0 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf get_byte__char ; 2 cycles to set up loop : ; 1 + 1 + 2 = 4 ; nop extra_instructions_per_bit - 4 ; Delay 5 cycles nop nop nop nop nop ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__174_loop: ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf get_byte__char,f ; 2 cycles : ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__180select0 equ get_byte__char+0 get_byte__char__180select0__byte equ get_byte__char+0 get_byte__char__180select0__bit equ 7 bsf get_byte__char__180select0__byte,get_byte__char__180select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 2 + 2 + 3 = 7 ; nop extra_instructions_per_bit - 7 ; Delay 2 cycles nop nop ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz get_byte__count,f goto get_byte__174_loop get_byte__174_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; return char ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank1+7 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc receiving__byte,receiving__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label210__0end ; if { receiving } body start ; receiving := 0 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 label210__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; 1 cycle : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles to set up loop : ; 1 + 2 = 3 ; nop extra_instructions_per_bit - 3 ; Delay 6 cycles nop nop nop nop nop nop ; Send the data : ; `count_down count 8 ...' start movlw 8 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__count send_byte__228_loop: ; 4 cycles : ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__230select0 equ send_byte__char+0 send_byte__char__230select0__byte equ send_byte__char+0 send_byte__char__230select0__bit equ 0 btfss send_byte__char__230select0__byte,send_byte__char__230select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__230select0__byte,send_byte__char__230select0__bit bsf serial_out__byte,serial_out__bit ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 4 + 2 + 3 = 9 = no NOP ' s needed : ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz send_byte__count,f goto send_byte__228_loop send_byte__228_done: ; `count_down count 8 ...' end ; Send the stop bit : ; nop 1 ; Delay 1 cycles nop ; 1 cycle ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for call / return ; 2 cycles for argument ; 1 + 2 + 2 = 5 ; nop extra_instructions_per_bit - 5 ; Delay 4 cycles nop nop nop nop ; procedure send_byte end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 retlw 0 ; bank 1 ; Default register bank is now 1 ; procedure direction_set start direction_set: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 direction_set__variables__base equ global__variables__bank1+9 direction_set__bytes__base equ direction_set__variables__base+0 direction_set__bits__base equ direction_set__variables__base+1 direction_set__total__bytes equ 1 ; arguments_none ; This procedure will set the direction appropriately . direction_set__temp equ direction_set__bytes__base+0 ; Deal with port C : ; temp := 0 clrf direction_set__temp ; if { direction_low @ 0 } start ; Alias variable for select direction_low @ 0 direction_low__265select0 equ direction_low+0 direction_low__265select0__byte equ direction_low+0 direction_low__265select0__bit equ 0 ; expression=`{ direction_low @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_low__265select0__byte,direction_low__265select0__bit ; if { direction_low @ 0 } body start ; temp @ io0_bit := 1 ; Select temp @ io0_bit direction_set__temp__266select0 equ direction_set__temp+0 direction_set__temp__266select0__byte equ direction_set__temp+0 direction_set__temp__266select0__bit equ 0 bsf direction_set__temp__266select0__byte,direction_set__temp__266select0__bit ; if { direction_low @ 0 } body end ; if exp=` direction_low @ 0 ' false skip delay=2 ; Other expression=`{ direction_low @ 0 }' delay=2 ; if { direction_low @ 0 } end ; if { direction_low @ 1 } start ; Alias variable for select direction_low @ 1 direction_low__268select0 equ direction_low+0 direction_low__268select0__byte equ direction_low+0 direction_low__268select0__bit equ 1 ; expression=`{ direction_low @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_low__268select0__byte,direction_low__268select0__bit ; if { direction_low @ 1 } body start ; temp @ io1_bit := 1 ; Select temp @ io1_bit direction_set__temp__269select0 equ direction_set__temp+0 direction_set__temp__269select0__byte equ direction_set__temp+0 direction_set__temp__269select0__bit equ 1 bsf direction_set__temp__269select0__byte,direction_set__temp__269select0__bit ; if { direction_low @ 1 } body end ; if exp=` direction_low @ 1 ' false skip delay=2 ; Other expression=`{ direction_low @ 1 }' delay=2 ; if { direction_low @ 1 } end ; if { direction_low @ 2 } start ; Alias variable for select direction_low @ 2 direction_low__271select0 equ direction_low+0 direction_low__271select0__byte equ direction_low+0 direction_low__271select0__bit equ 2 ; expression=`{ direction_low @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_low__271select0__byte,direction_low__271select0__bit ; if { direction_low @ 2 } body start ; temp @ io2_bit := 1 ; Select temp @ io2_bit direction_set__temp__272select0 equ direction_set__temp+0 direction_set__temp__272select0__byte equ direction_set__temp+0 direction_set__temp__272select0__bit equ 2 bsf direction_set__temp__272select0__byte,direction_set__temp__272select0__bit ; if { direction_low @ 2 } body end ; if exp=` direction_low @ 2 ' false skip delay=2 ; Other expression=`{ direction_low @ 2 }' delay=2 ; if { direction_low @ 2 } end ; if { direction_low @ 3 } start ; Alias variable for select direction_low @ 3 direction_low__274select0 equ direction_low+0 direction_low__274select0__byte equ direction_low+0 direction_low__274select0__bit equ 3 ; expression=`{ direction_low @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_low__274select0__byte,direction_low__274select0__bit ; if { direction_low @ 3 } body start ; temp @ io3_bit := 1 ; Select temp @ io3_bit direction_set__temp__275select0 equ direction_set__temp+0 direction_set__temp__275select0__byte equ direction_set__temp+0 direction_set__temp__275select0__bit equ 3 bsf direction_set__temp__275select0__byte,direction_set__temp__275select0__bit ; if { direction_low @ 3 } body end ; if exp=` direction_low @ 3 ' false skip delay=2 ; Other expression=`{ direction_low @ 3 }' delay=2 ; if { direction_low @ 3 } end ; if { direction_low @ 4 } start ; Alias variable for select direction_low @ 4 direction_low__277select0 equ direction_low+0 direction_low__277select0__byte equ direction_low+0 direction_low__277select0__bit equ 4 ; expression=`{ direction_low @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_low__277select0__byte,direction_low__277select0__bit ; if { direction_low @ 4 } body start ; temp @ io4_bit := 1 ; Select temp @ io4_bit direction_set__temp__278select0 equ direction_set__temp+0 direction_set__temp__278select0__byte equ direction_set__temp+0 direction_set__temp__278select0__bit equ 4 bsf direction_set__temp__278select0__byte,direction_set__temp__278select0__bit ; if { direction_low @ 4 } body end ; if exp=` direction_low @ 4 ' false skip delay=2 ; Other expression=`{ direction_low @ 4 }' delay=2 ; if { direction_low @ 4 } end ; if { direction_high @ 0 } start ; Alias variable for select direction_high @ 0 direction_high__280select0 equ direction_high+0 direction_high__280select0__byte equ direction_high+0 direction_high__280select0__bit equ 0 ; expression=`{ direction_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_high__280select0__byte,direction_high__280select0__bit ; if { direction_high @ 0 } body start ; temp @ io5_bit := 1 ; Select temp @ io5_bit direction_set__temp__281select0 equ direction_set__temp+0 direction_set__temp__281select0__byte equ direction_set__temp+0 direction_set__temp__281select0__bit equ 5 bsf direction_set__temp__281select0__byte,direction_set__temp__281select0__bit ; if { direction_high @ 0 } body end ; if exp=` direction_high @ 0 ' false skip delay=2 ; Other expression=`{ direction_high @ 0 }' delay=2 ; if { direction_high @ 0 } end ; inline assembly statements begin movf direction_set__temp,w tris 7 ; inline assembly statements end ; Deal with port B : ; temp := 0 clrf direction_set__temp ; if { direction_high @ 1 } start ; Alias variable for select direction_high @ 1 direction_high__290select0 equ direction_high+0 direction_high__290select0__byte equ direction_high+0 direction_high__290select0__bit equ 1 ; expression=`{ direction_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_high__290select0__byte,direction_high__290select0__bit ; if { direction_high @ 1 } body start ; temp @ io6_bit := 1 ; Select temp @ io6_bit direction_set__temp__291select0 equ direction_set__temp+0 direction_set__temp__291select0__byte equ direction_set__temp+0 direction_set__temp__291select0__bit equ 4 bsf direction_set__temp__291select0__byte,direction_set__temp__291select0__bit ; if { direction_high @ 1 } body end ; if exp=` direction_high @ 1 ' false skip delay=2 ; Other expression=`{ direction_high @ 1 }' delay=2 ; if { direction_high @ 1 } end ; if { direction_high @ 2 } start ; Alias variable for select direction_high @ 2 direction_high__293select0 equ direction_high+0 direction_high__293select0__byte equ direction_high+0 direction_high__293select0__bit equ 2 ; expression=`{ direction_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_high__293select0__byte,direction_high__293select0__bit ; if { direction_high @ 2 } body start ; temp @ io7_bit := 1 ; Select temp @ io7_bit direction_set__temp__294select0 equ direction_set__temp+0 direction_set__temp__294select0__byte equ direction_set__temp+0 direction_set__temp__294select0__bit equ 5 bsf direction_set__temp__294select0__byte,direction_set__temp__294select0__bit ; if { direction_high @ 2 } body end ; if exp=` direction_high @ 2 ' false skip delay=2 ; Other expression=`{ direction_high @ 2 }' delay=2 ; if { direction_high @ 2 } end ; if { direction_high @ 3 } start ; Alias variable for select direction_high @ 3 direction_high__296select0 equ direction_high+0 direction_high__296select0__byte equ direction_high+0 direction_high__296select0__bit equ 3 ; expression=`{ direction_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_high__296select0__byte,direction_high__296select0__bit ; if { direction_high @ 3 } body start ; temp @ io8_bit := 1 ; Select temp @ io8_bit direction_set__temp__297select0 equ direction_set__temp+0 direction_set__temp__297select0__byte equ direction_set__temp+0 direction_set__temp__297select0__bit equ 0 bsf direction_set__temp__297select0__byte,direction_set__temp__297select0__bit ; if { direction_high @ 3 } body end ; if exp=` direction_high @ 3 ' false skip delay=2 ; Other expression=`{ direction_high @ 3 }' delay=2 ; if { direction_high @ 3 } end ; if { direction_high @ 4 } start ; Alias variable for select direction_high @ 4 direction_high__299select0 equ direction_high+0 direction_high__299select0__byte equ direction_high+0 direction_high__299select0__bit equ 4 ; expression=`{ direction_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc direction_high__299select0__byte,direction_high__299select0__bit ; if { direction_high @ 4 } body start ; temp @ io9_bit := 1 ; Select temp @ io9_bit direction_set__temp__300select0 equ direction_set__temp+0 direction_set__temp__300select0__byte equ direction_set__temp+0 direction_set__temp__300select0__bit equ 1 bsf direction_set__temp__300select0__byte,direction_set__temp__300select0__bit ; if { direction_high @ 4 } body end ; if exp=` direction_high @ 4 ' false skip delay=2 ; Other expression=`{ direction_high @ 4 }' delay=2 ; if { direction_high @ 4 } end ; temp @ serial_in_bit := 1 ; Select temp @ serial_in_bit direction_set__temp__302select0 equ direction_set__temp+0 direction_set__temp__302select0__byte equ direction_set__temp+0 direction_set__temp__302select0__bit equ 3 bsf direction_set__temp__302select0__byte,direction_set__temp__302select0__bit ; inline assembly statements begin movf direction_set__temp,w tris 6 ; inline assembly statements end ; procedure direction_set end retlw 0 ; procedure reset start reset: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 reset__variables__base equ global__variables__bank1+10 reset__bytes__base equ reset__variables__base+0 reset__bits__base equ reset__variables__base+0 reset__total__bytes equ 0 ; arguments_none ; This procedure will initialize all global registers : ; Initialize global registers : ; inputs_low := 0 clrf inputs_low ; inputs_high := 0 clrf inputs_high ; raw_low := 0 clrf raw_low ; raw_high := 0 clrf raw_high ; outputs_low := 0 clrf outputs_low ; outputs_high := 0 clrf outputs_high ; complement_low := 0 clrf complement_low ; complement_high := 0 clrf complement_high ; direction_low := mask movlw 31 movwf direction_low ; direction_high := mask movlw 31 movwf direction_high ; low_low := 0 ; Switch from register bank 1 to register bank 0 (which contains low_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf low_low ; low_high := 0 clrf low_high ; high_low := 0 clrf high_low ; high_high := 0 clrf high_high ; raising_low := 0 clrf raising_low ; raising_high := 0 clrf raising_high ; falling_low := 0 clrf falling_low ; falling_high := 0 clrf falling_high ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Initialize remaining registers : ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf glitch ; index := 0 clrf index ; procedure reset end retlw 0 ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+17 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+4 delay__total__bytes equ 5 delay__344byte1 equ delay__bytes__base+3 delay__408byte0 equ delay__bytes__base+3 delay__409byte0 equ delay__bytes__base+3 delay__386bit1 equ delay__bits__base+0 delay__386bit1__byte equ delay__bits__base+0 delay__386bit1__bit equ 3 delay__379bit1 equ delay__bits__base+0 delay__379bit1__byte equ delay__bits__base+0 delay__379bit1__bit equ 3 ; arguments_none ; uniform_delay delay_instructions ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; This procedure delays 1 / 3 of a bit . ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__previous_low equ delay__bytes__base+0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__previous_high equ delay__bytes__base+1 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__temp equ delay__bytes__base+2 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Set the port C outputs first : ; Uniform delay remaining = 130 Accumulated Delay = 1 ; temp := outputs_low movf outputs_low,w movwf delay__temp ; Uniform delay remaining = 128 Accumulated Delay = 3 ; if { outputs_high @ 0 } start ; Alias variable for select outputs_high @ 0 outputs_high__360select0 equ outputs_high+0 outputs_high__360select0__byte equ outputs_high+0 outputs_high__360select0__bit equ 0 ; expression=`{ outputs_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc outputs_high__360select0__byte,outputs_high__360select0__bit ; if { outputs_high @ 0 } body start ; Uniform delay remaining = 128 Accumulated Delay = 0 ; temp @ io5_bit := 1 ; Select temp @ io5_bit delay__temp__361select0 equ delay__temp+0 delay__temp__361select0__byte equ delay__temp+0 delay__temp__361select0__bit equ 5 bsf delay__temp__361select0__byte,delay__temp__361select0__bit ; Uniform delay remaining = 127 Accumulated Delay = 1 ; Uniform delay remaining = 127 Accumulated Delay = 1 ; if { outputs_high @ 0 } body end ; if exp=` outputs_high @ 0 ' false skip delay=2 ; Other expression=`{ outputs_high @ 0 }' delay=2 ; if { outputs_high @ 0 } end ; Uniform delay remaining = 126 Accumulated Delay = 5 ; portc := temp movf delay__temp,w movwf portc ; Uniform delay remaining = 124 Accumulated Delay = 7 ; Uniform delay remaining = 124 Accumulated Delay = 7 ; Set the port outputs next : ; Uniform delay remaining = 124 Accumulated Delay = 7 ; temp := 0 clrf delay__temp ; Uniform delay remaining = 123 Accumulated Delay = 8 ; if { outputs_high @ 1 } start ; Alias variable for select outputs_high @ 1 outputs_high__367select0 equ outputs_high+0 outputs_high__367select0__byte equ outputs_high+0 outputs_high__367select0__bit equ 1 ; expression=`{ outputs_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc outputs_high__367select0__byte,outputs_high__367select0__bit ; if { outputs_high @ 1 } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; temp @ io6_bit := 1 ; Select temp @ io6_bit delay__temp__368select0 equ delay__temp+0 delay__temp__368select0__byte equ delay__temp+0 delay__temp__368select0__bit equ 4 bsf delay__temp__368select0__byte,delay__temp__368select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { outputs_high @ 1 } body end ; if exp=` outputs_high @ 1 ' false skip delay=2 ; Other expression=`{ outputs_high @ 1 }' delay=2 ; if { outputs_high @ 1 } end ; Uniform delay remaining = 121 Accumulated Delay = 10 ; if { outputs_high @ 2 } start ; Alias variable for select outputs_high @ 2 outputs_high__370select0 equ outputs_high+0 outputs_high__370select0__byte equ outputs_high+0 outputs_high__370select0__bit equ 2 ; expression=`{ outputs_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc outputs_high__370select0__byte,outputs_high__370select0__bit ; if { outputs_high @ 2 } body start ; Uniform delay remaining = 121 Accumulated Delay = 0 ; temp @ io7_bit := 1 ; Select temp @ io7_bit delay__temp__371select0 equ delay__temp+0 delay__temp__371select0__byte equ delay__temp+0 delay__temp__371select0__bit equ 5 bsf delay__temp__371select0__byte,delay__temp__371select0__bit ; Uniform delay remaining = 120 Accumulated Delay = 1 ; Uniform delay remaining = 120 Accumulated Delay = 1 ; if { outputs_high @ 2 } body end ; if exp=` outputs_high @ 2 ' false skip delay=2 ; Other expression=`{ outputs_high @ 2 }' delay=2 ; if { outputs_high @ 2 } end ; Uniform delay remaining = 119 Accumulated Delay = 12 ; if { outputs_high @ 3 } start ; Alias variable for select outputs_high @ 3 outputs_high__373select0 equ outputs_high+0 outputs_high__373select0__byte equ outputs_high+0 outputs_high__373select0__bit equ 3 ; expression=`{ outputs_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc outputs_high__373select0__byte,outputs_high__373select0__bit ; if { outputs_high @ 3 } body start ; Uniform delay remaining = 119 Accumulated Delay = 0 ; temp @ io8_bit := 1 ; Select temp @ io8_bit delay__temp__374select0 equ delay__temp+0 delay__temp__374select0__byte equ delay__temp+0 delay__temp__374select0__bit equ 0 bsf delay__temp__374select0__byte,delay__temp__374select0__bit ; Uniform delay remaining = 118 Accumulated Delay = 1 ; Uniform delay remaining = 118 Accumulated Delay = 1 ; if { outputs_high @ 3 } body end ; if exp=` outputs_high @ 3 ' false skip delay=2 ; Other expression=`{ outputs_high @ 3 }' delay=2 ; if { outputs_high @ 3 } end ; Uniform delay remaining = 117 Accumulated Delay = 14 ; if { outputs_high @ 4 } start ; Alias variable for select outputs_high @ 4 outputs_high__376select0 equ outputs_high+0 outputs_high__376select0__byte equ outputs_high+0 outputs_high__376select0__bit equ 4 ; expression=`{ outputs_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc outputs_high__376select0__byte,outputs_high__376select0__bit ; if { outputs_high @ 4 } body start ; Uniform delay remaining = 117 Accumulated Delay = 0 ; temp @ io9_bit := 1 ; Select temp @ io9_bit delay__temp__377select0 equ delay__temp+0 delay__temp__377select0__byte equ delay__temp+0 delay__temp__377select0__bit equ 1 bsf delay__temp__377select0__byte,delay__temp__377select0__bit ; Uniform delay remaining = 116 Accumulated Delay = 1 ; Uniform delay remaining = 116 Accumulated Delay = 1 ; if { outputs_high @ 4 } body end ; if exp=` outputs_high @ 4 ' false skip delay=2 ; Other expression=`{ outputs_high @ 4 }' delay=2 ; if { outputs_high @ 4 } end ; Uniform delay remaining = 115 Accumulated Delay = 16 ; temp @ serial_out_bit := portb @ serial_out_bit ; Alias variable for select portb @ serial_out_bit portb__379select2 equ portb+0 portb__379select2__byte equ portb+0 portb__379select2__bit equ 2 bcf delay__379bit1__byte,delay__379bit1__bit btfsc portb__379select2__byte,portb__379select2__bit bsf delay__379bit1__byte,delay__379bit1__bit ; Select variable temp @ serial_out_bit delay__temp__379select3 equ delay__temp+0 delay__temp__379select3__byte equ delay__temp+0 delay__temp__379select3__bit equ 2 btfss delay__379bit1__byte,delay__379bit1__bit bcf delay__temp__379select3__byte,delay__temp__379select3__bit btfsc delay__379bit1__byte,delay__379bit1__bit bsf delay__temp__379select3__byte,delay__temp__379select3__bit ; Uniform delay remaining = 108 Accumulated Delay = 23 ; portb := temp movf delay__temp,w movwf portb ; Uniform delay remaining = 106 Accumulated Delay = 25 ; Uniform delay remaining = 106 Accumulated Delay = 25 ; Now read inputs : ; Uniform delay remaining = 106 Accumulated Delay = 25 ; temp := portc movf portc,w movwf delay__temp ; Uniform delay remaining = 104 Accumulated Delay = 27 ; raw_low := temp & mask movlw 31 andwf delay__temp,w movwf raw_low ; Uniform delay remaining = 101 Accumulated Delay = 30 ; raw_high := 0 clrf raw_high ; Uniform delay remaining = 100 Accumulated Delay = 31 ; raw_high @ 0 := temp @ 5 ; Alias variable for select temp @ 5 delay__temp__386select2 equ delay__temp+0 delay__temp__386select2__byte equ delay__temp+0 delay__temp__386select2__bit equ 5 bcf delay__386bit1__byte,delay__386bit1__bit btfsc delay__temp__386select2__byte,delay__temp__386select2__bit bsf delay__386bit1__byte,delay__386bit1__bit ; Select variable raw_high @ 0 raw_high__386select3 equ raw_high+0 raw_high__386select3__byte equ raw_high+0 raw_high__386select3__bit equ 0 btfss delay__386bit1__byte,delay__386bit1__bit bcf raw_high__386select3__byte,raw_high__386select3__bit btfsc delay__386bit1__byte,delay__386bit1__bit bsf raw_high__386select3__byte,raw_high__386select3__bit ; Uniform delay remaining = 93 Accumulated Delay = 38 ; temp := portb movf portb,w movwf delay__temp ; Uniform delay remaining = 91 Accumulated Delay = 40 ; if { temp @ io6_bit } start ; Alias variable for select temp @ io6_bit delay__temp__388select0 equ delay__temp+0 delay__temp__388select0__byte equ delay__temp+0 delay__temp__388select0__bit equ 4 ; expression=`{ temp @ io6_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc delay__temp__388select0__byte,delay__temp__388select0__bit ; if { temp @ io6_bit } body start ; Uniform delay remaining = 91 Accumulated Delay = 0 ; raw_high @ 1 := 1 ; Select raw_high @ 1 raw_high__389select0 equ raw_high+0 raw_high__389select0__byte equ raw_high+0 raw_high__389select0__bit equ 1 bsf raw_high__389select0__byte,raw_high__389select0__bit ; Uniform delay remaining = 90 Accumulated Delay = 1 ; Uniform delay remaining = 90 Accumulated Delay = 1 ; if { temp @ io6_bit } body end ; if exp=` temp @ io6_bit ' false skip delay=2 ; Other expression=`{ temp @ io6_bit }' delay=2 ; if { temp @ io6_bit } end ; Uniform delay remaining = 89 Accumulated Delay = 42 ; if { temp @ io7_bit } start ; Alias variable for select temp @ io7_bit delay__temp__391select0 equ delay__temp+0 delay__temp__391select0__byte equ delay__temp+0 delay__temp__391select0__bit equ 5 ; expression=`{ temp @ io7_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc delay__temp__391select0__byte,delay__temp__391select0__bit ; if { temp @ io7_bit } body start ; Uniform delay remaining = 89 Accumulated Delay = 0 ; raw_high @ 2 := 1 ; Select raw_high @ 2 raw_high__392select0 equ raw_high+0 raw_high__392select0__byte equ raw_high+0 raw_high__392select0__bit equ 2 bsf raw_high__392select0__byte,raw_high__392select0__bit ; Uniform delay remaining = 88 Accumulated Delay = 1 ; Uniform delay remaining = 88 Accumulated Delay = 1 ; if { temp @ io7_bit } body end ; if exp=` temp @ io7_bit ' false skip delay=2 ; Other expression=`{ temp @ io7_bit }' delay=2 ; if { temp @ io7_bit } end ; Uniform delay remaining = 87 Accumulated Delay = 44 ; if { temp @ io8_bit } start ; Alias variable for select temp @ io8_bit delay__temp__394select0 equ delay__temp+0 delay__temp__394select0__byte equ delay__temp+0 delay__temp__394select0__bit equ 0 ; expression=`{ temp @ io8_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc delay__temp__394select0__byte,delay__temp__394select0__bit ; if { temp @ io8_bit } body start ; Uniform delay remaining = 87 Accumulated Delay = 0 ; raw_high @ 3 := 1 ; Select raw_high @ 3 raw_high__395select0 equ raw_high+0 raw_high__395select0__byte equ raw_high+0 raw_high__395select0__bit equ 3 bsf raw_high__395select0__byte,raw_high__395select0__bit ; Uniform delay remaining = 86 Accumulated Delay = 1 ; Uniform delay remaining = 86 Accumulated Delay = 1 ; if { temp @ io8_bit } body end ; if exp=` temp @ io8_bit ' false skip delay=2 ; Other expression=`{ temp @ io8_bit }' delay=2 ; if { temp @ io8_bit } end ; Uniform delay remaining = 85 Accumulated Delay = 46 ; if { temp @ io9_bit } start ; Alias variable for select temp @ io9_bit delay__temp__397select0 equ delay__temp+0 delay__temp__397select0__byte equ delay__temp+0 delay__temp__397select0__bit equ 1 ; expression=`{ temp @ io9_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc delay__temp__397select0__byte,delay__temp__397select0__bit ; if { temp @ io9_bit } body start ; Uniform delay remaining = 85 Accumulated Delay = 0 ; raw_high @ 4 := 1 ; Select raw_high @ 4 raw_high__398select0 equ raw_high+0 raw_high__398select0__byte equ raw_high+0 raw_high__398select0__bit equ 4 bsf raw_high__398select0__byte,raw_high__398select0__bit ; Uniform delay remaining = 84 Accumulated Delay = 1 ; Uniform delay remaining = 84 Accumulated Delay = 1 ; if { temp @ io9_bit } body end ; if exp=` temp @ io9_bit ' false skip delay=2 ; Other expression=`{ temp @ io9_bit }' delay=2 ; if { temp @ io9_bit } end ; Uniform delay remaining = 83 Accumulated Delay = 48 ; Uniform delay remaining = 83 Accumulated Delay = 48 ; Process the inputs through the complements mask : ; Uniform delay remaining = 83 Accumulated Delay = 48 ; previous_low := inputs_low movf inputs_low,w movwf delay__previous_low ; Uniform delay remaining = 81 Accumulated Delay = 50 ; previous_high := inputs_high movf inputs_high,w movwf delay__previous_high ; Uniform delay remaining = 79 Accumulated Delay = 52 ; inputs_low := {{ raw_low ^ complement_low }} & mask movf raw_low,w xorwf complement_low,w andlw 31 movwf inputs_low ; Uniform delay remaining = 75 Accumulated Delay = 56 ; inputs_high := {{ raw_high ^ complement_high }} & mask movf raw_high,w xorwf complement_high,w andlw 31 movwf inputs_high ; Uniform delay remaining = 71 Accumulated Delay = 60 ; Uniform delay remaining = 71 Accumulated Delay = 60 ; Now generate any interrupts : ; Uniform delay remaining = 71 Accumulated Delay = 60 ; temp := inputs_low & high_low | inputs_high & high_high movf inputs_low,w andwf high_low,w movwf delay__408byte0 movf inputs_high,w andwf high_high,w iorwf delay__408byte0,w movwf delay__temp ; Uniform delay remaining = 64 Accumulated Delay = 67 ; temp := temp | {{ inputs_low ^ mask }} & low_low | {{ inputs_high ^ mask }} & low_high movf delay__temp,w movwf delay__409byte0 movlw 31 xorwf inputs_low,w andwf low_low,w iorwf delay__409byte0,f movlw 31 xorwf inputs_high,w andwf low_high,w iorwf delay__409byte0,w movwf delay__temp ; Uniform delay remaining = 53 Accumulated Delay = 78 ; temp := temp | {{ inputs_low ^ previous_low }} & raising_low & inputs_low movf inputs_low,w xorwf delay__previous_low,w andwf raising_low,w andwf inputs_low,w iorwf delay__temp,f ; Uniform delay remaining = 48 Accumulated Delay = 83 ; temp := temp | {{ inputs_high ^ previous_high }} & raising_high & inputs_high movf inputs_high,w xorwf delay__previous_high,w andwf raising_high,w andwf inputs_high,w iorwf delay__temp,f ; Uniform delay remaining = 43 Accumulated Delay = 88 ; temp := temp | {{ inputs_low ^ previous_low }} & falling_low & previous_low movf inputs_low,w xorwf delay__previous_low,w andwf falling_low,w andwf delay__previous_low,w iorwf delay__temp,f ; Uniform delay remaining = 38 Accumulated Delay = 93 ; temp := temp | {{ inputs_high ^ previous_high }} & falling_high & previous_high movf inputs_high,w xorwf delay__previous_high,w andwf falling_high,w andwf delay__previous_high,w iorwf delay__temp,f ; Uniform delay remaining = 33 Accumulated Delay = 98 ; if { temp != 0 } start movf delay__temp,w ; expression=`{ temp != 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { temp != 0 } body start ; Uniform delay remaining = 33 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 32 Accumulated Delay = 1 ; Uniform delay remaining = 32 Accumulated Delay = 1 ; if { temp != 0 } body end ; if exp=` temp != 0 ' false skip delay=3 ; Other expression=`{ temp != 0 }' delay=3 ; if { temp != 0 } end ; Uniform delay remaining = 30 Accumulated Delay = 101 ; if { receiving && interrupt_pending && interrupt_enable } start ; expression=`receiving' exp_delay=0 true_delay=10 false_delay=9 true_size=14 false_size=1 btfsc receiving__byte,receiving__bit goto label417__4true label417__4false: ; Delay 2 cycles nop nop goto and417__2false label417__4true: ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfss interrupt_pending__byte,interrupt_pending__bit goto label417__3false label417__3true: and417__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label417__1false label417__1true: and417__0true: ; if { receiving && interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 30 Accumulated Delay = 0 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 29 Accumulated Delay = 1 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 28 Accumulated Delay = 2 ; Uniform delay remaining = 28 Accumulated Delay = 2 ; if { receiving && interrupt_pending && interrupt_enable } body end goto label417__1end label417__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label417__1end: ; Other expression=`interrupt_enable' delay=6 goto label417__3end label417__3false: and417__2false: ; Delay 2 cycles nop nop goto and417__0false ; if exp=`interrupt_pending' total delay=10 ; if exp=`interrupt_pending' generic label417__3end: ; Other expression=`interrupt_pending' delay=10 ; if exp=`receiving' total delay=13 ; if exp=`receiving' generic label417__4end: ; Other expression=`receiving' delay=13 and417__2end: and417__0false: and417__0end: ; if { receiving && interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 17 Accumulated Delay = 114 ; Uniform delay remaining = 17 Accumulated Delay = 114 ; Soak up remaining 17 cycles ; Delay 17 cycles movlw 5 movwf delay__344byte1 delay__344delay0: decfsz delay__344byte1,f goto delay__344delay0 nop ; procedure delay end retlw 0 ; optimize 1 ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; comment {The main procedure is loaded with switch statements . On the 12 - bit} ; comment {PIC ' s , switch statements have to live in the first 256 bytes of} ; comment {each code bank . For this reason , we shove main into code bank 1 .} ; comment {If we , try to put main in code bank 0 , it pushes the first bytes} ; comment {of several routines out of the first 256 bytes , which is also a} ; comment {no - no of the 12 - bit PIC ' s .} ; procedure main start switch__455block_start: addwf pcl___register,f goto switch__455block456 goto switch__455block460 goto switch__455block464 goto switch__455block468 goto switch__455block472 goto switch__455block476 goto switch__455block480 goto switch__455block484 switch__455block_end: ; switch_check 455 switch__455block_start switch__455block_end switch__493block_start: addwf pcl___register,f goto switch__493block494 goto switch__493block498 goto switch__493block502 goto switch__493block506 goto switch__493block510 goto switch__493block514 goto switch__493block518 goto switch__493block522 switch__493block_end: ; switch_check 493 switch__493block_start switch__493block_end switch__531block_start: addwf pcl___register,f goto switch__531block532 goto switch__531block536 goto switch__531block540 goto switch__531block544 goto switch__531block548 goto switch__531block553 goto switch__531block558 goto switch__531block563 switch__531block_end: ; switch_check 531 switch__531block_start switch__531block_end switch__572block_start: addwf pcl___register,f goto switch__572block573 goto switch__572block577 goto switch__572block581 goto switch__572block585 goto switch__572block589 goto switch__572block593 goto switch__572block597 goto switch__572block601 switch__572block_end: ; switch_check 572 switch__572block_start switch__572block_end switch__452block_start: addwf pcl___register,f goto switch__452block453 goto switch__452block491 goto switch__452block529 goto switch__452block569 goto switch__452block607 goto switch__452block607 goto switch__452block607 goto switch__452block607 switch__452block_end: ; switch_check 452 switch__452block_start switch__452block_end switch__617block_start: addwf pcl___register,f goto switch__617block618 goto switch__617block621 goto switch__617block624 goto switch__617block627 goto switch__617block630 goto switch__617block633 goto switch__617block636 goto switch__617block639 goto switch__617block642 goto switch__617block645 switch__617block_end: ; switch_check 617 switch__617block_start switch__617block_end switch__685block_start: addwf pcl___register,f goto switch__685block686 goto switch__685block686 goto switch__685block686 goto switch__685block686 goto switch__685block691 goto switch__685block691 goto switch__685block695 goto switch__685block695 switch__685block_end: ; switch_check 685 switch__685block_start switch__685block_end switch__702block_start: addwf pcl___register,f goto switch__702block703 goto switch__702block707 goto switch__702block711 goto switch__702block715 goto switch__702block719 goto switch__702block727 goto switch__702block731 goto switch__702block736 switch__702block_end: ; switch_check 702 switch__702block_start switch__702block_end switch__660block_start: addwf pcl___register,f goto switch__660block661 goto switch__660block661 goto switch__660block661 goto switch__660block661 goto switch__660block661 goto switch__660block665 goto switch__660block679 goto switch__660block701 switch__660block_end: ; switch_check 660 switch__660block_start switch__660block_end switch__449block_start: addwf pcl___register,f goto switch__449block450 goto switch__449block613 goto switch__449block654 goto switch__449block658 switch__449block_end: ; switch_check 449 switch__449block_start switch__449block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+10 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+3 main__total__bytes equ 4 main__449byte0 equ main__bytes__base+2 main__452byte0 equ main__bytes__base+2 main__660byte0 equ main__bytes__base+2 main__634bit1 equ main__bits__base+0 main__634bit1__byte equ main__bits__base+0 main__634bit1__bit equ 0 main__619bit1 equ main__bits__base+0 main__619bit1__byte equ main__bits__base+0 main__619bit1__bit equ 0 main__637bit1 equ main__bits__base+0 main__637bit1__byte equ main__bits__base+0 main__637bit1__bit equ 0 main__622bit1 equ main__bits__base+0 main__622bit1__byte equ main__bits__base+0 main__622bit1__bit equ 0 main__640bit1 equ main__bits__base+0 main__640bit1__byte equ main__bits__base+0 main__640bit1__bit equ 0 main__625bit1 equ main__bits__base+0 main__625bit1__byte equ main__bits__base+0 main__625bit1__bit equ 0 main__643bit1 equ main__bits__base+0 main__643bit1__byte equ main__bits__base+0 main__643bit1__bit equ 0 main__646bit1 equ main__bits__base+0 main__646bit1__byte equ main__bits__base+0 main__646bit1__bit equ 0 main__628bit1 equ main__bits__base+0 main__628bit1__byte equ main__bits__base+0 main__628bit1__bit equ 0 main__631bit1 equ main__bits__base+0 main__631bit1__byte equ main__bits__base+0 main__631bit1__bit equ 0 ; arguments_none main__command equ main__bytes__base+0 main__temp equ main__bytes__base+1 ; Initalize all of the globals : ; call reset {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call reset ; Process commands : ; loop_forever ... start ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit main__444loop__forever: ; Wait for command : ; command := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__command ; Dispatch on command : ; switch { command >> 6 } swapf main__command,w movwf main__449byte0 rrf main__449byte0,f rrf main__449byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__449block_start switch__449block450: ; < Command = 00 xx xxxx > : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__452byte0 rrf main__452byte0,f rrf main__452byte0,w andlw 7 ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 5 6 7 goto switch__452block_start switch__452block453: ; < Command = 0000 0 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__455block_start switch__455block456: ; Read Inputs Low < Command = 0000 0000 > : ; temp := inputs_low movf inputs_low,w movwf main__temp goto switch__455end switch__455block460: ; Read Inputs High < Command = 0000 0001 > : ; temp := inputs_high movf inputs_high,w movwf main__temp goto switch__455end switch__455block464: ; Read Complement Mask Low < Command = 0000 0010 > : ; temp := complement_low movf complement_low,w movwf main__temp goto switch__455end switch__455block468: ; Read Complement Mask High < Command = 0000 0011 > : ; temp := complement_high movf complement_high,w movwf main__temp goto switch__455end switch__455block472: ; Read Direction Mask Low < Command = 0000 0100 > : ; temp := direction_low movf direction_low,w movwf main__temp goto switch__455end switch__455block476: ; Read Direction Mask High < Command = 0000 0101 > : ; temp := direction_high movf direction_high,w movwf main__temp goto switch__455end switch__455block480: ; Read Raw Low < Command = 0000 0110 > : ; temp := raw_low movf raw_low,w movwf main__temp goto switch__455end switch__455block484: ; Read Raw High < Command = 0000 0111 > : ; temp := raw_high movf raw_high,w movwf main__temp switch__455end: ; call send_byte {{ temp & mask }} movlw 31 andwf main__temp,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__452end switch__452block491: ; < Command = 0000 1 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__493block_start switch__493block494: ; Read Low Mask Low < Command = 0000 1000 > : ; temp := low_low ; Switch from register bank 1 to register bank 0 (which contains low_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf low_low,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block498: ; Read Low Mask High < Command = 0000 1001 > : ; temp := low_high ; Switch from register bank 1 to register bank 0 (which contains low_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf low_high,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block502: ; Read High Mask Low < Command = 0000 1010 > : ; temp := high_low ; Switch from register bank 1 to register bank 0 (which contains high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf high_low,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block506: ; Read High Mask High < Command = 0000 1011 > : ; temp := high_high ; Switch from register bank 1 to register bank 0 (which contains high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf high_high,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block510: ; Read Raising Mask Low < Command = 0000 1100 > : ; temp := raising_low ; Switch from register bank 1 to register bank 0 (which contains raising_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf raising_low,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block514: ; Read Raising Mask High < Command = 0000 1101 > : ; temp := raising_high ; Switch from register bank 1 to register bank 0 (which contains raising_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf raising_high,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block518: ; Read Falling Mask Low < Command = 0000 1110 > : ; temp := falling_low ; Switch from register bank 1 to register bank 0 (which contains falling_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf falling_low,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp goto switch__493end switch__493block522: ; Read Falling Mask High < Command = 0000 1111 > : ; temp := falling_high ; Switch from register bank 1 to register bank 0 (which contains falling_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf falling_high,w ; Switch from register bank 0 to register bank 1 (which contains main__temp) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__temp switch__493end: ; call send_byte {{ temp & mask }} movlw 31 andwf main__temp,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__452end switch__452block529: ; < Command = 0001 0 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__531block_start switch__531block532: ; Read Outputs Low < Command = 0001 0000 > : ; call send_byte {{ outputs_low }} movf outputs_low,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block536: ; Read Outputs High < Command = 0001 0001 > : ; call send_byte {{ outputs_high }} movf outputs_high,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block540: ; Set Complement Mask Low < Command = 0001 0010 > : ; complement_low := get_byte {{ }} & mask ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 31 movwf complement_low ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block544: ; Set Complement Mask High < Command = 0001 0011 > : ; complement_high := get_byte {{ }} & mask ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 31 movwf complement_high ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block548: ; Set Direction Mask High < Command = 0001 0100 > : ; direction_low := get_byte {{ }} & mask ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 31 movwf direction_low ; call direction_set {{ }} call direction_set ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block553: ; Set Direction Mask High < Command = 0001 0101 > : ; direction_high := get_byte {{ }} & mask ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 31 movwf direction_high ; call direction_set {{ }} call direction_set ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__531end switch__531block558: ; Reset Everything < Command = 0001 0110 > : ; outputs_low := 0 clrf outputs_low ; outputs_high := 0 clrf outputs_high goto switch__531end switch__531block563: ; Reset Everything < Command = 0001 0110 > : ; call reset {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call reset ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit switch__531end: goto switch__452end switch__452block569: ; < Command = 0001 1 xxx > : ; temp := get_byte {{ }} & mask ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w andlw 31 movwf main__temp ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__572block_start switch__572block573: ; Set Low Mask Low < Command = 0001 1000 > : ; low_low := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains low_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf low_low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block577: ; Set Low Mask High < Command = 0001 1001 > : ; low_high := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains low_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf low_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block581: ; Set High Mask Low < Command = 0001 1010 > : ; high_low := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains high_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf high_low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block585: ; Set High Mask High < Command = 0001 1011 > : ; high_high := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains high_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf high_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block589: ; Set Raising Mask Low < Command = 0001 1100 > : ; raising_low := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains raising_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf raising_low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block593: ; Set Raising Mask High < Command = 0001 1101 > : ; raising_high := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains raising_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf raising_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block597: ; Set Falling Mask Low < Command = 0001 1110 > : ; falling_low := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains falling_low) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf falling_low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__572end switch__572block601: ; Set Falling Mask High < Command = 0001 1111 > : ; falling_high := temp movf main__temp,w ; Switch from register bank 1 to register bank 0 (which contains falling_high) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf falling_high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__572end: goto switch__452end switch__452block607: ; Set Outputs Low < Command = 001 x xxxx > : ; outputs_low := command & mask movlw 31 andwf main__command,w movwf outputs_low switch__452end: goto switch__449end switch__449block613: ; < Command = 01 xx xxxx > : ; if { command @ 5 } start ; Alias variable for select command @ 5 main__command__615select0 equ main__command+0 main__command__615select0__byte equ main__command+0 main__command__615select0__bit equ 5 ; expression=`{ command @ 5 }' exp_delay=0 true_delay=94 false_delay=3 true_size=83 false_size=3 btfsc main__command__615select0__byte,main__command__615select0__bit goto label615__1true label615__1false: ; else body start ; Set Outputs High < Command = 010 o oooo > : ; outputs_high := command & mask movlw 31 andwf main__command,w movwf outputs_high ; else body end goto label615__1end label615__1true: ; if { command @ 5 } body start ; Set Output Bit < Command = 011 v bbbb > : ; switch { command & 15 } movlw 15 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 ; case 8 ; case 9 goto switch__617block_start switch__617block618: ; outputs_low @ 0 := command @ 4 ; Alias variable for select command @ 4 main__command__619select2 equ main__command+0 main__command__619select2__byte equ main__command+0 main__command__619select2__bit equ 4 bcf main__619bit1__byte,main__619bit1__bit btfsc main__command__619select2__byte,main__command__619select2__bit bsf main__619bit1__byte,main__619bit1__bit ; Select variable outputs_low @ 0 outputs_low__619select3 equ outputs_low+0 outputs_low__619select3__byte equ outputs_low+0 outputs_low__619select3__bit equ 0 btfss main__619bit1__byte,main__619bit1__bit bcf outputs_low__619select3__byte,outputs_low__619select3__bit btfsc main__619bit1__byte,main__619bit1__bit bsf outputs_low__619select3__byte,outputs_low__619select3__bit goto switch__617end switch__617block621: ; outputs_low @ 1 := command @ 4 ; Alias variable for select command @ 4 main__command__622select2 equ main__command+0 main__command__622select2__byte equ main__command+0 main__command__622select2__bit equ 4 bcf main__622bit1__byte,main__622bit1__bit btfsc main__command__622select2__byte,main__command__622select2__bit bsf main__622bit1__byte,main__622bit1__bit ; Select variable outputs_low @ 1 outputs_low__622select3 equ outputs_low+0 outputs_low__622select3__byte equ outputs_low+0 outputs_low__622select3__bit equ 1 btfss main__622bit1__byte,main__622bit1__bit bcf outputs_low__622select3__byte,outputs_low__622select3__bit btfsc main__622bit1__byte,main__622bit1__bit bsf outputs_low__622select3__byte,outputs_low__622select3__bit goto switch__617end switch__617block624: ; outputs_low @ 2 := command @ 4 ; Alias variable for select command @ 4 main__command__625select2 equ main__command+0 main__command__625select2__byte equ main__command+0 main__command__625select2__bit equ 4 bcf main__625bit1__byte,main__625bit1__bit btfsc main__command__625select2__byte,main__command__625select2__bit bsf main__625bit1__byte,main__625bit1__bit ; Select variable outputs_low @ 2 outputs_low__625select3 equ outputs_low+0 outputs_low__625select3__byte equ outputs_low+0 outputs_low__625select3__bit equ 2 btfss main__625bit1__byte,main__625bit1__bit bcf outputs_low__625select3__byte,outputs_low__625select3__bit btfsc main__625bit1__byte,main__625bit1__bit bsf outputs_low__625select3__byte,outputs_low__625select3__bit goto switch__617end switch__617block627: ; outputs_low @ 3 := command @ 4 ; Alias variable for select command @ 4 main__command__628select2 equ main__command+0 main__command__628select2__byte equ main__command+0 main__command__628select2__bit equ 4 bcf main__628bit1__byte,main__628bit1__bit btfsc main__command__628select2__byte,main__command__628select2__bit bsf main__628bit1__byte,main__628bit1__bit ; Select variable outputs_low @ 3 outputs_low__628select3 equ outputs_low+0 outputs_low__628select3__byte equ outputs_low+0 outputs_low__628select3__bit equ 3 btfss main__628bit1__byte,main__628bit1__bit bcf outputs_low__628select3__byte,outputs_low__628select3__bit btfsc main__628bit1__byte,main__628bit1__bit bsf outputs_low__628select3__byte,outputs_low__628select3__bit goto switch__617end switch__617block630: ; outputs_low @ 4 := command @ 4 ; Alias variable for select command @ 4 main__command__631select2 equ main__command+0 main__command__631select2__byte equ main__command+0 main__command__631select2__bit equ 4 bcf main__631bit1__byte,main__631bit1__bit btfsc main__command__631select2__byte,main__command__631select2__bit bsf main__631bit1__byte,main__631bit1__bit ; Select variable outputs_low @ 4 outputs_low__631select3 equ outputs_low+0 outputs_low__631select3__byte equ outputs_low+0 outputs_low__631select3__bit equ 4 btfss main__631bit1__byte,main__631bit1__bit bcf outputs_low__631select3__byte,outputs_low__631select3__bit btfsc main__631bit1__byte,main__631bit1__bit bsf outputs_low__631select3__byte,outputs_low__631select3__bit goto switch__617end switch__617block633: ; outputs_high @ 0 := command @ 4 ; Alias variable for select command @ 4 main__command__634select2 equ main__command+0 main__command__634select2__byte equ main__command+0 main__command__634select2__bit equ 4 bcf main__634bit1__byte,main__634bit1__bit btfsc main__command__634select2__byte,main__command__634select2__bit bsf main__634bit1__byte,main__634bit1__bit ; Select variable outputs_high @ 0 outputs_high__634select3 equ outputs_high+0 outputs_high__634select3__byte equ outputs_high+0 outputs_high__634select3__bit equ 0 btfss main__634bit1__byte,main__634bit1__bit bcf outputs_high__634select3__byte,outputs_high__634select3__bit btfsc main__634bit1__byte,main__634bit1__bit bsf outputs_high__634select3__byte,outputs_high__634select3__bit goto switch__617end switch__617block636: ; outputs_high @ 1 := command @ 4 ; Alias variable for select command @ 4 main__command__637select2 equ main__command+0 main__command__637select2__byte equ main__command+0 main__command__637select2__bit equ 4 bcf main__637bit1__byte,main__637bit1__bit btfsc main__command__637select2__byte,main__command__637select2__bit bsf main__637bit1__byte,main__637bit1__bit ; Select variable outputs_high @ 1 outputs_high__637select3 equ outputs_high+0 outputs_high__637select3__byte equ outputs_high+0 outputs_high__637select3__bit equ 1 btfss main__637bit1__byte,main__637bit1__bit bcf outputs_high__637select3__byte,outputs_high__637select3__bit btfsc main__637bit1__byte,main__637bit1__bit bsf outputs_high__637select3__byte,outputs_high__637select3__bit goto switch__617end switch__617block639: ; outputs_high @ 2 := command @ 4 ; Alias variable for select command @ 4 main__command__640select2 equ main__command+0 main__command__640select2__byte equ main__command+0 main__command__640select2__bit equ 4 bcf main__640bit1__byte,main__640bit1__bit btfsc main__command__640select2__byte,main__command__640select2__bit bsf main__640bit1__byte,main__640bit1__bit ; Select variable outputs_high @ 2 outputs_high__640select3 equ outputs_high+0 outputs_high__640select3__byte equ outputs_high+0 outputs_high__640select3__bit equ 2 btfss main__640bit1__byte,main__640bit1__bit bcf outputs_high__640select3__byte,outputs_high__640select3__bit btfsc main__640bit1__byte,main__640bit1__bit bsf outputs_high__640select3__byte,outputs_high__640select3__bit goto switch__617end switch__617block642: ; outputs_high @ 3 := command @ 4 ; Alias variable for select command @ 4 main__command__643select2 equ main__command+0 main__command__643select2__byte equ main__command+0 main__command__643select2__bit equ 4 bcf main__643bit1__byte,main__643bit1__bit btfsc main__command__643select2__byte,main__command__643select2__bit bsf main__643bit1__byte,main__643bit1__bit ; Select variable outputs_high @ 3 outputs_high__643select3 equ outputs_high+0 outputs_high__643select3__byte equ outputs_high+0 outputs_high__643select3__bit equ 3 btfss main__643bit1__byte,main__643bit1__bit bcf outputs_high__643select3__byte,outputs_high__643select3__bit btfsc main__643bit1__byte,main__643bit1__bit bsf outputs_high__643select3__byte,outputs_high__643select3__bit goto switch__617end switch__617block645: ; outputs_high @ 4 := command @ 4 ; Alias variable for select command @ 4 main__command__646select2 equ main__command+0 main__command__646select2__byte equ main__command+0 main__command__646select2__bit equ 4 bcf main__646bit1__byte,main__646bit1__bit btfsc main__command__646select2__byte,main__command__646select2__bit bsf main__646bit1__byte,main__646bit1__bit ; Select variable outputs_high @ 4 outputs_high__646select3 equ outputs_high+0 outputs_high__646select3__byte equ outputs_high+0 outputs_high__646select3__bit equ 4 btfss main__646bit1__byte,main__646bit1__bit bcf outputs_high__646select3__byte,outputs_high__646select3__bit btfsc main__646bit1__byte,main__646bit1__bit bsf outputs_high__646select3__byte,outputs_high__646select3__bit switch__617end: ; if { command @ 5 } body end ; if exp=` command @ 5 ' generic label615__1end: ; Other expression=`{ command @ 5 }' delay=-1 ; if { command @ 5 } end goto switch__449end switch__449block654: ; < Command = 10 xx xxxx > : ; Do nothing : goto switch__449end switch__449block658: ; < Command = 11 xx xxxx > : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__660byte0 rrf main__660byte0,f rrf main__660byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 goto switch__660block_start switch__660block661: ; < Command = 110 x xxxx or 1110 0 xxx > : ; Do nothing : goto switch__660end switch__660block665: ; < Command = 1110 1 xxx > : ; if { command = 0xef } start movlw 239 subwf main__command,w ; expression=`{ command = 0xef }' exp_delay=2 true_delay=6 false_delay=0 true_size=8 false_size=0 btfss z___byte,z___bit goto label667__0end ; if { command = 0xef } body start ; Read Interrupt Bits < Command = 1110 1111 > : ; temporary := 0 ; Switch from register bank 1 to register bank 0 (which contains temporary) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf temporary ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_pending__byte,interrupt_pending__bit ; if { interrupt_pending } body start ; temporary @ 0 := 1 ; Select temporary @ 0 temporary__671select0 equ temporary+0 temporary__671select0__byte equ temporary+0 temporary__671select0__bit equ 0 bsf temporary__671select0__byte,temporary__671select0__bit ; if { interrupt_pending } body end ; if exp=`interrupt_pending' false skip delay=2 ; Other expression=`{ interrupt_pending }' delay=2 ; if { interrupt_pending } end ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_enable__byte,interrupt_enable__bit ; if { interrupt_enable } body start ; temporary @ 1 := 1 ; Select temporary @ 1 temporary__674select0 equ temporary+0 temporary__674select0__byte equ temporary+0 temporary__674select0__bit equ 1 bsf temporary__674select0__byte,temporary__674select0__bit ; if { interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`{ interrupt_enable }' delay=2 ; if { interrupt_enable } end ; call send_byte {{ temporary }} movf temporary,w ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { command = 0xef } body end ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label667__0end: ; if exp=` command = 0xef ' empty false ; Other expression=`{ command = 0xef }' delay=-1 ; if { command = 0xef } end goto switch__660end switch__660block679: ; < Command = 1111 0 xxx > : ; Switching between register banks generates bulky code ; ; Keep code generation in bank 0 by assigning command to ; temporary : ; temporary := command movf main__command,w ; Switch from register bank 1 to register bank 0 (which contains temporary) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf temporary ; switch { temporary & 7 } movlw 7 andwf temporary,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__685block_start switch__685block686: ; Set Interrupt Bits < Command = 1111 00 ep > : ; interrupt_enable := temporary @ 1 ; Alias variable for select temporary @ 1 temporary__688select0 equ temporary+0 temporary__688select0__byte equ temporary+0 temporary__688select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit btfsc temporary__688select0__byte,temporary__688select0__bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__689select0 equ temporary+0 temporary__689select0__byte equ temporary+0 temporary__689select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc temporary__689select0__byte,temporary__689select0__bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__685end switch__685block691: ; Set Interrupt Pending < Command = 1111 010 p > : ; interrupt_pending := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__693select0 equ temporary+0 temporary__693select0__byte equ temporary+0 temporary__693select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc temporary__693select0__byte,temporary__693select0__bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__685end switch__685block695: ; Set Interrupt Enable < Command = 1111 011 e > : ; interrupt_enable := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__697select0 equ temporary+0 temporary__697select0__byte equ temporary+0 temporary__697select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit btfsc temporary__697select0__byte,temporary__697select0__bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__685end: goto switch__660end switch__660block701: ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__702block_start switch__702block703: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_lsb movlw 252 addwf osccal,f goto switch__702end switch__702block707: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_lsb movlw 4 addwf osccal,f goto switch__702end switch__702block711: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__702end switch__702block715: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__702end switch__702block719: ; ID Next < Command = 1111 1100 > : ; call send_byte {{ id ~~ {{ index }} }} incf index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; index := index + 1 incf index,f ; if { index >= id . size } start movlw 49 subwf index,w ; expression=`{ index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { index >= id . size } body start ; index := 0 clrf index ; if { index >= id . size } body end ; if exp=` index >= id . size ' false skip delay=4 ; Other expression=`{ index >= id . size }' delay=4 ; if { index >= id . size } end goto switch__702end switch__702block727: ; ID Reset < Command = 1111 1101 > : ; index := 0 clrf index goto switch__702end switch__702block731: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf glitch,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; glitch := 0 clrf glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__702end switch__702block736: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__702end: switch__660end: switch__449end: goto main__444loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 22 bytes of 24 available bytes ; Register bank 1 used 14 bytes of 16 available bytes ; Register bank 2 used 0 bytes of 16 available bytes ; Register bank 3 used 0 bytes of 16 available bytes end