radix dec global__variables__bank0 equ 7 global__variables__bank1 equ 48 global__bit__variables__bank0 equ 24 global__bit__variables__bank1 equ 53 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers movlw 216 tris 6 ; Initialize OPTION register movlw 192 option ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the In8 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See :} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / in8 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12c509 cp = off wdte = on mclre = off fosc = intrc ; 14=0xe 4095=0xfff __config 14 configuration___address equ 4095 ; comment {Define processor constants :} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {Define serial communication control constants :} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; comment {Define some registers :} osccal equ 5 ; constant osccal_unit 0x10 osccal_unit equ 16 ; comment {Define port bit assignments :} porta equ 6 out0__byte equ 6 out0__bit equ 0 out1__byte equ 6 out1__bit equ 1 out2__byte equ 6 out2__bit equ 2 in3__byte equ 6 in3__bit equ 3 serial_in__byte equ 6 serial_in__bit equ 4 serial_out__byte equ 6 serial_out__bit equ 5 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 10 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 4 , 0s'In8A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 45 retlw 45 ; 1 retlw 1 ; 0 retlw 0 ; 10 retlw 10 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 245 ; random number retlw 16 ; random number retlw 125 ; random number retlw 177 ; random number retlw 255 ; random number retlw 6 ; random number retlw 237 ; random number retlw 109 ; random number retlw 147 ; random number retlw 223 ; random number retlw 31 ; random number retlw 8 ; random number retlw 117 ; random number retlw 249 ; random number retlw 21 ; random number retlw 214 ; random number ; 4 retlw 4 ; `In8A' retlw 73 retlw 110 retlw 56 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; comment {Define some globals :} inputs equ global__variables__bank0+0 complement equ global__variables__bank0+1 ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 falling equ global__variables__bank0+2 high equ global__variables__bank0+3 low equ global__variables__bank0+4 raising equ global__variables__bank0+5 ; comment {For now put all the smaller routines first so that they can live} ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} ; comment {can only call routines that are within the first 256 bytes < i . e .} ; comment {the first half > of the code page .} ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank0+6 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 4 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__86while__continue: ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__86while__break ; call delay {{ }} call delay goto get_byte__86while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__86while__break: ; `while serial_in ...' end ; Clear any iterrupt being sent : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; char := 0 clrf get_byte__char ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__100_loop: ; call delay {{ }} call delay ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__104select0 equ get_byte__char+0 get_byte__char__104select0__byte equ get_byte__char+0 get_byte__char__104select0__bit equ 7 bsf get_byte__char__104select0__byte,get_byte__char__104select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz get_byte__count,f goto get_byte__100_loop get_byte__100_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure put_byte start put_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 put_byte__variables__base equ global__variables__bank0+10 put_byte__bytes__base equ put_byte__variables__base+0 put_byte__bits__base equ put_byte__variables__base+2 put_byte__total__bytes equ 2 put_byte__char equ put_byte__bytes__base+0 ; This procedure will send < char > to < serial_out > . put_byte__count equ put_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label133__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label133__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf put_byte__count put_byte__146_loop: ; serial_out := char @ 0 ; Alias variable for select char @ 0 put_byte__char__147select0 equ put_byte__char+0 put_byte__char__147select0__byte equ put_byte__char+0 put_byte__char__147select0__bit equ 0 btfss put_byte__char__147select0__byte,put_byte__char__147select0__bit bcf serial_out__byte,serial_out__bit btfsc put_byte__char__147select0__byte,put_byte__char__147select0__bit bsf serial_out__byte,serial_out__bit ; char := char >> 1 bcf c___byte,c___bit rrf put_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz put_byte__count,f goto put_byte__146_loop put_byte__146_done: ; `count_down count 8 ...' end ; Send the stop bit : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; procedure put_byte end retlw 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+12 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+5 delay__total__bytes equ 5 delay__161byte1 equ delay__bytes__base+4 delay__216byte0 equ delay__bytes__base+4 ; arguments_none ; uniform_delay instructions_per_delay ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; This procedure delays for 1 third of a bit time . It is responsible ; Uniform delay remaining = 134 Accumulated Delay = 0 ; for reading the inputs and dealing with interrupts . ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__changed equ delay__bytes__base+0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__previous equ delay__bytes__base+1 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__not_inputs equ delay__bytes__base+2 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__counter equ delay__bytes__base+3 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Clear the select bits : ; Uniform delay remaining = 133 Accumulated Delay = 1 ; porta := porta & 0xf8 movlw 248 andwf porta,f ; Uniform delay remaining = 131 Accumulated Delay = 3 ; Uniform delay remaining = 131 Accumulated Delay = 3 ; inputs := 0 clrf inputs ; Uniform delay remaining = 130 Accumulated Delay = 4 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 130 Accumulated Delay = 0 ; inputs @ 7 := 1 ; Select inputs @ 7 inputs__181select0 equ inputs+0 inputs__181select0__byte equ inputs+0 inputs__181select0__bit equ 7 bsf inputs__181select0__byte,inputs__181select0__bit ; Uniform delay remaining = 129 Accumulated Delay = 1 ; Uniform delay remaining = 129 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 128 Accumulated Delay = 6 ; out0 := 1 bsf out0__byte,out0__bit ; Uniform delay remaining = 127 Accumulated Delay = 7 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 127 Accumulated Delay = 0 ; inputs @ 6 := 1 ; Select inputs @ 6 inputs__185select0 equ inputs+0 inputs__185select0__byte equ inputs+0 inputs__185select0__bit equ 6 bsf inputs__185select0__byte,inputs__185select0__bit ; Uniform delay remaining = 126 Accumulated Delay = 1 ; Uniform delay remaining = 126 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 125 Accumulated Delay = 9 ; out1 := 1 bsf out1__byte,out1__bit ; Uniform delay remaining = 124 Accumulated Delay = 10 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 124 Accumulated Delay = 0 ; inputs @ 4 := 1 ; Select inputs @ 4 inputs__189select0 equ inputs+0 inputs__189select0__byte equ inputs+0 inputs__189select0__bit equ 4 bsf inputs__189select0__byte,inputs__189select0__bit ; Uniform delay remaining = 123 Accumulated Delay = 1 ; Uniform delay remaining = 123 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 122 Accumulated Delay = 12 ; out0 := 0 bcf out0__byte,out0__bit ; Uniform delay remaining = 121 Accumulated Delay = 13 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 121 Accumulated Delay = 0 ; inputs @ 5 := 1 ; Select inputs @ 5 inputs__193select0 equ inputs+0 inputs__193select0__byte equ inputs+0 inputs__193select0__bit equ 5 bsf inputs__193select0__byte,inputs__193select0__bit ; Uniform delay remaining = 120 Accumulated Delay = 1 ; Uniform delay remaining = 120 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 119 Accumulated Delay = 15 ; out2 := 1 bsf out2__byte,out2__bit ; Uniform delay remaining = 118 Accumulated Delay = 16 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 118 Accumulated Delay = 0 ; inputs @ 1 := 1 ; Select inputs @ 1 inputs__197select0 equ inputs+0 inputs__197select0__byte equ inputs+0 inputs__197select0__bit equ 1 bsf inputs__197select0__byte,inputs__197select0__bit ; Uniform delay remaining = 117 Accumulated Delay = 1 ; Uniform delay remaining = 117 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 116 Accumulated Delay = 18 ; out0 := 1 bsf out0__byte,out0__bit ; Uniform delay remaining = 115 Accumulated Delay = 19 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 115 Accumulated Delay = 0 ; inputs @ 0 := 1 ; Select inputs @ 0 inputs__201select0 equ inputs+0 inputs__201select0__byte equ inputs+0 inputs__201select0__bit equ 0 bsf inputs__201select0__byte,inputs__201select0__bit ; Uniform delay remaining = 114 Accumulated Delay = 1 ; Uniform delay remaining = 114 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 113 Accumulated Delay = 21 ; out1 := 0 bcf out1__byte,out1__bit ; Uniform delay remaining = 112 Accumulated Delay = 22 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 112 Accumulated Delay = 0 ; inputs @ 2 := 1 ; Select inputs @ 2 inputs__205select0 equ inputs+0 inputs__205select0__byte equ inputs+0 inputs__205select0__bit equ 2 bsf inputs__205select0__byte,inputs__205select0__bit ; Uniform delay remaining = 111 Accumulated Delay = 1 ; Uniform delay remaining = 111 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 110 Accumulated Delay = 24 ; out0 := 0 bcf out0__byte,out0__bit ; Uniform delay remaining = 109 Accumulated Delay = 25 ; if { in3 } start ; expression=`{ in3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc in3__byte,in3__bit ; if { in3 } body start ; Uniform delay remaining = 109 Accumulated Delay = 0 ; inputs @ 3 := 1 ; Select inputs @ 3 inputs__209select0 equ inputs+0 inputs__209select0__byte equ inputs+0 inputs__209select0__bit equ 3 bsf inputs__209select0__byte,inputs__209select0__bit ; Uniform delay remaining = 108 Accumulated Delay = 1 ; Uniform delay remaining = 108 Accumulated Delay = 1 ; if { in3 } body end ; if exp=`in3' false skip delay=2 ; Other expression=`{ in3 }' delay=2 ; if { in3 } end ; Uniform delay remaining = 107 Accumulated Delay = 27 ; out2 := 0 bcf out2__byte,out2__bit ; Uniform delay remaining = 106 Accumulated Delay = 28 ; Uniform delay remaining = 106 Accumulated Delay = 28 ; Deal with interrupts : ; Uniform delay remaining = 106 Accumulated Delay = 28 ; not_inputs := inputs ^ 0xff movlw 255 xorwf inputs,w movwf delay__not_inputs ; Uniform delay remaining = 103 Accumulated Delay = 31 ; changed := inputs ^ previous movf inputs,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 100 Accumulated Delay = 34 ; if { {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 } start movf low,w andwf delay__not_inputs,w movwf delay__216byte0 movf high,w andwf inputs,w iorwf delay__216byte0,f movf delay__changed,w andwf inputs,w andwf raising,w iorwf delay__216byte0,f movf delay__changed,w andwf delay__not_inputs,w andwf falling,w iorwf delay__216byte0,w ; expression=`{ {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 } body start ; Uniform delay remaining = 100 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 99 Accumulated Delay = 1 ; Uniform delay remaining = 99 Accumulated Delay = 1 ; if { {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 } body end ; if exp=` {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 }' delay=16 ; if { {{ low & not_inputs }} | {{ high & inputs }} | {{ changed & inputs & raising }} | {{ changed & not_inputs & falling }} != 0 } end ; Uniform delay remaining = 84 Accumulated Delay = 50 ; Remember current inputs for next time around : ; Uniform delay remaining = 84 Accumulated Delay = 50 ; previous := inputs movf inputs,w movwf delay__previous ; Uniform delay remaining = 82 Accumulated Delay = 52 ; Uniform delay remaining = 82 Accumulated Delay = 52 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 82 Accumulated Delay = 52 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label223__2true label223__2false: ; Delay 2 cycles nop nop goto and223__0false label223__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label223__1false label223__1true: and223__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 82 Accumulated Delay = 0 ; Shove serial out to low to indicate an interrupt : ; Uniform delay remaining = 82 Accumulated Delay = 0 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 81 Accumulated Delay = 1 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 80 Accumulated Delay = 2 ; Uniform delay remaining = 80 Accumulated Delay = 2 ; if { interrupt_pending && interrupt_enable } body end goto label223__1end label223__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label223__1end: ; Other expression=`interrupt_enable' delay=6 ; if exp=`interrupt_pending' total delay=9 ; if exp=`interrupt_pending' generic label223__2end: ; Other expression=`interrupt_pending' delay=9 and223__0false: and223__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 73 Accumulated Delay = 61 ; Uniform delay remaining = 73 Accumulated Delay = 61 ; Soak up remaining 73 cycles ; Delay 73 cycles movlw 24 movwf delay__161byte1 delay__161delay0: decfsz delay__161byte1,f goto delay__161delay0 ; procedure delay end retlw 0 ; optimize 1 ; comment {The main routine can span the 256 byte boundary :} ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; procedure main start switch__272block_start: addwf pcl___register,f goto switch__272block273 goto switch__272block277 goto switch__272block281 goto switch__272block285 goto switch__272block289 goto switch__272block293 goto switch__272default297 goto switch__272default297 switch__272block_end: ; switch_check 272 switch__272block_start switch__272block_end switch__304block_start: addwf pcl___register,f goto switch__304block305 goto switch__304block309 goto switch__304block313 goto switch__304block317 goto switch__304block321 goto switch__304block325 goto switch__304default329 goto switch__304default329 switch__304block_end: ; switch_check 304 switch__304block_start switch__304block_end switch__269block_start: addwf pcl___register,f goto switch__269block270 goto switch__269block302 goto switch__269default334 goto switch__269default334 goto switch__269default334 goto switch__269default334 goto switch__269default334 goto switch__269default334 switch__269block_end: ; switch_check 269 switch__269block_start switch__269block_end switch__368block_start: addwf pcl___register,f goto switch__368block369 goto switch__368block369 goto switch__368block369 goto switch__368block369 goto switch__368block374 goto switch__368block374 goto switch__368block378 goto switch__368block378 switch__368block_end: ; switch_check 368 switch__368block_start switch__368block_end switch__386block_start: addwf pcl___register,f goto switch__386block387 goto switch__386block391 goto switch__386block395 goto switch__386block399 goto switch__386block403 goto switch__386block414 goto switch__386block418 goto switch__386block423 switch__386block_end: ; switch_check 386 switch__386block_start switch__386block_end switch__347block_start: addwf pcl___register,f goto switch__347block348 goto switch__347block348 goto switch__347block348 goto switch__347block348 goto switch__347block348 goto switch__347block352 goto switch__347block366 goto switch__347block384 switch__347block_end: ; switch_check 347 switch__347block_start switch__347block_end switch__266block_start: addwf pcl___register,f goto switch__266block267 goto switch__266block339 goto switch__266block342 goto switch__266block345 switch__266block_end: ; switch_check 266 switch__266block_start switch__266block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+0 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+5 main__total__bytes equ 5 main__269byte0 equ main__bytes__base+4 main__347byte0 equ main__bytes__base+4 main__266byte0 equ main__bytes__base+4 main__354byte0 equ main__bytes__base+4 ; arguments_none ; This is the main program that is responsible for processing commands ; from the master . main__command equ main__bytes__base+0 main__glitch equ main__bytes__base+1 main__id_index equ main__bytes__base+2 main__result equ main__bytes__base+3 ; Let ROOT = http : / / web . gramlich . com / projects / robobricks . ; For Threshold4A specific commands see : ; ROOT / threshold4 / rev_a / index . html ; For shared commands see : ; ROOT / specifications . html # Software_Protocol ; For shared interruptcommands see : ; ROOT / specifications . html # Interrupts ; complement := 0 clrf complement ; interrupt_enable := 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; falling := 0 clrf falling ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; id_index := 0 clrf main__id_index ; loop_forever ... start main__264loop__forever: ; command := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__command ; switch { command >> 6 } swapf main__command,w movwf main__266byte0 rrf main__266byte0,f rrf main__266byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__266block_start switch__266block267: ; Command = 00 xx xxxx : ; switch { command >> 3 } rrf main__command,w movwf main__269byte0 rrf main__269byte0,f rrf main__269byte0,w andlw 31 ; case 0 ; case 1 goto switch__269block_start switch__269block270: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 goto switch__272block_start switch__272block273: ; Read Inputs < Command = 0000 0000 > : ; call put_byte {{ inputs ^ complement }} movf inputs,w xorwf complement,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272block277: ; Read Complement Mask < Command = 0000 0001 > : ; call put_byte {{ complement }} movf complement,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272block281: ; Read Low Mask < Command = 0000 0010 > : ; call put_byte {{ low }} movf low,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272block285: ; Read High Mask < Command = 0000 0011 > : ; call put_byte {{ high }} movf high,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272block289: ; Read Raising Mask < Command = 0000 0100 > : ; call put_byte {{ raising }} movf raising,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272block293: ; Read Falling Mask < Command = 0000 0101 > : ; call put_byte {{ falling }} movf falling,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__272end switch__272default297: ; Do Nothing < Command = 0000 011 x > : switch__272end: goto switch__269end switch__269block302: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 goto switch__304block_start switch__304block305: ; Read Raw < Command = 0000 1000 > : ; call put_byte {{ inputs }} movf inputs,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304block309: ; Read Complement < Command = 0000 1001 > : ; complement := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf complement ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304block313: ; Read Low < Command = 0000 1010 > : ; low := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304block317: ; Read High < Command = 0000 1011 > : ; high := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304block321: ; Read Raising < Command = 0000 1100 > : ; raising := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf raising ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304block325: ; Read Falling < Command = 0000 1101 > : ; falling := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf falling ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__304end switch__304default329: ; Do Nothing < Command = 0000 111 x > : switch__304end: goto switch__269end switch__269default334: ; Undefine command ; do nothing : switch__269end: goto switch__266end switch__266block339: ; do nothing < Command = 01 xx xxxx > : goto switch__266end switch__266block342: ; Do nothing < Command = 10 xx xxxx > : goto switch__266end switch__266block345: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__347byte0 rrf main__347byte0,f rrf main__347byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 goto switch__347block_start switch__347block348: ; Command = 1100 xxxx or 1110 0 xxx : ; Do nothing : goto switch__347end switch__347block352: ; Read Interrupt Bits < Command = 1110 1111 > : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__354byte0 movlw 7 subwf main__354byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=10 false_size=0 btfss z___byte,z___bit goto label354__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits : ; result := 0 clrf main__result ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_enable__byte,interrupt_enable__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label357__0end ; if { interrupt_enable } body start ; result := result | 2 movlw 2 iorwf main__result,f ; if { interrupt_enable } body end label357__0end: ; if exp=`interrupt_enable' empty false ; Other expression=`{ interrupt_enable }' delay=-1 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_pending__byte,interrupt_pending__bit bsf z___byte,z___bit ; if { interrupt_pending } body start ; result := result + 1 ; Switch from register bank 0 to register bank 1 (which contains main__result) bsf rp0___byte,rp0___bit ; Register bank is now 1 btfsc z___byte,z___bit incf main__result,f ; if { interrupt_pending } body end ; if exp=`interrupt_pending' false skip delay=2 ; Other expression=`{ interrupt_pending }' delay=2 ; if { interrupt_pending } end ; call put_byte {{ result }} movf main__result,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; if { {{ command & 7 }} = 7 } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label354__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__347end switch__347block366: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 goto switch__368block_start switch__368block369: ; Set interrupt bits < Command = 1111 00 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__371select0 equ main__command+0 main__command__371select0__byte equ main__command+0 main__command__371select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__371select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__371select0__byte,main__command__371select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__372select0 equ main__command+0 main__command__372select0__byte equ main__command+0 main__command__372select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__372select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__372select0__byte,main__command__372select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__368end switch__368block374: ; Set Interrupt Pending < Command = 1111 010 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__376select0 equ main__command+0 main__command__376select0__byte equ main__command+0 main__command__376select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__376select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__376select0__byte,main__command__376select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__368end switch__368block378: ; Set Interrupt Enable < Command = 1110 011 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__380select0 equ main__command+0 main__command__380select0__byte equ main__command+0 main__command__380select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__380select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__380select0__byte,main__command__380select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__368end: goto switch__347end switch__347block384: ; Shared commands < Command = 1111 1 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__386block_start switch__386block387: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 240 addwf osccal,f goto switch__386end switch__386block391: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 16 addwf osccal,f goto switch__386end switch__386block395: ; Clock Read < Command = 1111 1010 > : ; call put_byte {{ osccal }} movf osccal,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__386end switch__386block399: ; Clock Pulse < Command = 1111 1011 > : ; call put_byte {{ 0 }} ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__386end switch__386block403: ; ID Next < Command = 1111 1100 > : ; if { id_index >= id . size } start movlw 45 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end ; call put_byte {{ id ~~ {{ id_index }} }} incf main__id_index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id movwf put_byte__char call put_byte ; id_index := id_index + 1 ; Switch from register bank 0 to register bank 1 (which contains main__id_index) bsf rp0___byte,rp0___bit ; Register bank is now 1 incf main__id_index,f ; if { id_index >= id . size } start movlw 45 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end goto switch__386end switch__386block414: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf main__id_index goto switch__386end switch__386block418: ; Glitch Read < Command = 1111 1110 > : ; call put_byte {{ glitch }} movf main__glitch,w ; Switch from register bank 1 to register bank 0 (which contains put_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf put_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call put_byte ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__386end switch__386block423: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf main__glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf main__glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__386end: switch__347end: switch__266end: goto main__264loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 17 bytes of 25 available bytes ; Register bank 1 used 5 bytes of 16 available bytes end