radix dec global__variables__bank0 equ 8 global__variables__bank1 equ 48 global__variables__bank2 equ 80 global__variables__bank3 equ 112 global__bit__variables__bank0 equ 21 global__bit__variables__bank1 equ 54 global__bit__variables__bank2 equ 80 global__bit__variables__bank3 equ 112 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers b___tris equ global__variables__bank1+6 movlw 234 tris 6 ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf b___tris movlw 192 tris 7 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2002 by Wayne C . Gramlich and Bill Benson} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the Out10 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / compassdt1 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock ; 4052=0xfd4 4095=0xfff __config 4052 configuration___address equ 4095 ; comment {Define processor constants :} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {Define serial communication control constants :} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; constant extra_instructions_per_bit 9 extra_instructions_per_bit equ 9 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit extra_instructions_per_delay equ 3 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay delay_instructions equ 135 ; comment {Register definitions :} ; comment {Status register :} status equ 3 ; bind c status @ 0 c equ status+0 c__byte equ status+0 c__bit equ 0 ; bind z status @ 2 z equ status+0 z__byte equ status+0 z__bit equ 2 ; comment {OSCCAL register :} osccal equ 5 ; constant osccal_lsb 4 osccal_lsb equ 4 ; constant i2c_delay 3 i2c_delay equ 3 ; comment {Define bit offsets :} ; constant d1_bit 5 d1_bit equ 5 ; constant d2_bit 4 d2_bit equ 4 ; constant d3_bit 3 d3_bit equ 3 ; constant d4_bit 2 d4_bit equ 2 ; constant d5_bit 1 d5_bit equ 1 ; constant d6_bit 0 d6_bit equ 0 ; constant scl_bit 0 scl_bit equ 0 ; constant sda_bit 1 sda_bit equ 1 ; constant freq_bit 2 freq_bit equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; constant serial_out_bit 4 serial_out_bit equ 4 ; comment {Define pin assignments and directions :} portb equ 6 portc equ 7 d1__byte equ 7 d1__bit equ 5 d2__byte equ 7 d2__bit equ 4 d3__byte equ 7 d3__bit equ 3 d4__byte equ 7 d4__bit equ 2 d5__byte equ 7 d5__bit equ 1 d6__byte equ 7 d6__bit equ 0 scl__byte equ 6 scl__bit equ 0 sda__byte equ 6 sda__bit equ 1 freq__byte equ 6 freq__bit equ 2 serial_out__byte equ 6 serial_out__bit equ 4 serial_in__byte equ 6 serial_in__bit equ 3 ; constant mask 0x1f mask equ 31 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 13 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 11 , 0s'CompassDT1C' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 52 retlw 52 ; 1 retlw 1 ; 0 retlw 0 ; 13 retlw 13 ; 1 retlw 1 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 254 ; random number retlw 106 ; random number retlw 33 ; random number retlw 81 ; random number retlw 49 ; random number retlw 181 ; random number retlw 216 ; random number retlw 65 ; random number retlw 1 ; random number retlw 28 ; random number retlw 26 ; random number retlw 251 ; random number retlw 23 ; random number retlw 7 ; random number retlw 216 ; random number retlw 206 ; random number ; 11 retlw 11 ; `CompassDT1C' retlw 67 retlw 111 retlw 109 retlw 112 retlw 97 retlw 115 retlw 115 retlw 68 retlw 84 retlw 49 retlw 67 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; comment {Some globals : byte} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 ; bank 1 ; Default register bank is now 1 temporary equ global__variables__bank1+0 glitch equ global__variables__bank1+1 index equ global__variables__bank1+2 ; comment {Note that the 12 - bit PIC ' s only have a 2 - level deep stack .} ; comment {The code starts in the main procedure < located at the end of this code >} ; comment {The next level of procedure call is either get_byte or send_byte .} ; comment {Lastly , the lowest level of procedure call is delay . It all fits ,} ; comment {but just barely .} ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+1 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+1 delay__total__bytes equ 2 delay__104byte1 equ delay__bytes__base+0 ; arguments_none ; uniform_delay delay_instructions ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; This procedure delays 1 / 3 of a bit . ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; if < temp != 0 > < ; Uniform delay remaining = 130 Accumulated Delay = 1 ; interrupt_pending := 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; > ; Uniform delay remaining = 130 Accumulated Delay = 1 ; if < receiving && interrupt_pending && interrupt_enable > < ; Uniform delay remaining = 130 Accumulated Delay = 1 ; serial_out := 0 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; interrupt_enable := 0 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; > ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Soak up remaining 130 cycles ; Delay 130 cycles movlw 43 movwf delay__104byte1 delay__104delay0: decfsz delay__104byte1,f goto delay__104delay0 ; procedure delay end retlw 0 ; optimize 1 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank0+3 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; This procedure will wait for a byte to be received from ; serial_in_bit . It calls the delay procedure for all delays . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Why does the delay procedure wait for a third of bit ? Well , it ; has to do with the loop immediately below . If we catch the ; start bit at the beginning of a 1 / 3 bit time , we will be ; sampling data at approximately 1 / 3 of the way into each bit . ; Conversely , if we catch the start near the end of a 1 / 3 bit ; bit time , we will be sampling data at approximately 2 / 3 of the ; way into each bit . So , what this means is that our bit sample ; times will be somewhere between 1 / 3 and 2 / 3 of bit < i . e . in ; the middle of the bit . ; It would be nice to tweak the code to shorter delay times ; < 1 / 4 bit , 1 / 5 bit , etc . > but then it gets too hard to get ; the bookeeping done in the delay routine . A 12 - bit PIC ; running at 4 MHz <= 1 MIPS > , only has 138 instructions available ; for the delay routine when at 1 / 3 of bit . ; Wait for a start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__151while__continue: ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__151while__break ; call delay {{ }} call delay goto get_byte__151while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__151while__break: ; `while serial_in ...' end ; Clear interrupt : ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit ; ; 1 cycle : ; char := 0 clrf get_byte__char ; 2 cycles to set up loop : ; 1 + 1 + 2 = 4 ; nop extra_instructions_per_bit - 4 ; Delay 5 cycles nop nop nop nop nop ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__170_loop: ; call delay {{ }} call delay ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; 2 cycles : ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__176select0 equ get_byte__char+0 get_byte__char__176select0__byte equ get_byte__char+0 get_byte__char__176select0__bit equ 7 bsf get_byte__char__176select0__byte,get_byte__char__176select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 2 + 2 + 3 = 7 ; nop extra_instructions_per_bit - 7 ; Delay 2 cycles nop nop decfsz get_byte__count,f goto get_byte__170_loop get_byte__170_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank0+6 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label206__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label206__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; 1 cycle : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles to set up loop : ; 1 + 2 = 3 ; nop extra_instructions_per_bit - 3 ; Delay 6 cycles nop nop nop nop nop nop ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf send_byte__count send_byte__224_loop: ; 4 cycles : ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__226select0 equ send_byte__char+0 send_byte__char__226select0__byte equ send_byte__char+0 send_byte__char__226select0__bit equ 0 btfss send_byte__char__226select0__byte,send_byte__char__226select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__226select0__byte,send_byte__char__226select0__bit bsf serial_out__byte,serial_out__bit ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 4 + 2 + 3 = 9 = no NOP ' s needed : decfsz send_byte__count,f goto send_byte__224_loop send_byte__224_done: ; `count_down count 8 ...' end ; Send the stop bit : ; nop 1 ; Delay 1 cycles nop ; 1 cycle ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for call / return ; 2 cycles for argument ; 1 + 2 + 2 = 5 ; nop extra_instructions_per_bit - 5 ; Delay 4 cycles nop nop nop nop ; procedure send_byte end retlw 0 ; procedure i2c_start start i2c_start: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 i2c_start__variables__base equ global__variables__bank0+8 i2c_start__bytes__base equ i2c_start__variables__base+0 i2c_start__bits__base equ i2c_start__variables__base+0 i2c_start__total__bytes equ 0 ; arguments_none ; direction sda write ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf b___tris,sda__bit movf b___tris,w tris 6 ; sda := 0 bcf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 0 bcf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; procedure i2c_start end ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 retlw 0 ; procedure i2c_restart start i2c_restart: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 i2c_restart__variables__base equ global__variables__bank0+8 i2c_restart__bytes__base equ i2c_restart__variables__base+0 i2c_restart__bits__base equ i2c_restart__variables__base+0 i2c_restart__total__bytes equ 0 ; arguments_none ; direction sda write ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf b___tris,sda__bit movf b___tris,w tris 6 ; sda := 1 bsf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; sda := 0 bcf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 0 bcf scl__byte,scl__bit ; procedure i2c_restart end ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 retlw 0 ; procedure i2c_stop start i2c_stop: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 i2c_stop__variables__base equ global__variables__bank0+8 i2c_stop__bytes__base equ i2c_stop__variables__base+0 i2c_stop__bits__base equ i2c_stop__variables__base+0 i2c_stop__total__bytes equ 0 ; arguments_none ; direction sda write ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf b___tris,sda__bit movf b___tris,w tris 6 ; sda := 0 bcf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; sda := 1 bsf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; procedure i2c_stop end ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 retlw 0 ; procedure i2c_get_byte start i2c_get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 i2c_get_byte__variables__base equ global__variables__bank0+8 i2c_get_byte__bytes__base equ i2c_get_byte__variables__base+0 i2c_get_byte__bits__base equ i2c_get_byte__variables__base+3 i2c_get_byte__total__bytes equ 3 ; arguments_none i2c_get_byte__0return__byte equ i2c_get_byte__bytes__base+0 ; This procedure will wait for a byte to be received from ; serial_in_bit . It calls the delay procedure for all delays . i2c_get_byte__count equ i2c_get_byte__bytes__base+1 i2c_get_byte__char equ i2c_get_byte__bytes__base+2 ; direction sda read ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bsf b___tris,sda__bit movf b___tris,w tris 6 ; `count_down count 8 ...' start movlw 8 ; Switch from register bank 1 to register bank 0 (which contains i2c_get_byte__count) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf i2c_get_byte__count i2c_get_byte__299_loop: ; char := char >> 1 bcf c___byte,c___bit rrf i2c_get_byte__char,f ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 i2c_get_byte__char__304select0 equ i2c_get_byte__char+0 i2c_get_byte__char__304select0__byte equ i2c_get_byte__char+0 i2c_get_byte__char__304select0__bit equ 7 bsf i2c_get_byte__char__304select0__byte,i2c_get_byte__char__304select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; scl := 0 bcf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop decfsz i2c_get_byte__count,f goto i2c_get_byte__299_loop i2c_get_byte__299_done: ; `count_down count 8 ...' end ; direction sda write ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf b___tris,sda__bit movf b___tris,w tris 6 ; Deal with 9 th bit : ; sda := 0 bcf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 0 bcf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; return char ; Switch from register bank 1 to register bank 0 (which contains i2c_get_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf i2c_get_byte__char,w movwf i2c_get_byte__0return__byte retlw 0 ; procedure i2c_get_byte end ; procedure i2c_send_byte start i2c_send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 i2c_send_byte__variables__base equ global__variables__bank0+11 i2c_send_byte__bytes__base equ i2c_send_byte__variables__base+0 i2c_send_byte__bits__base equ i2c_send_byte__variables__base+2 i2c_send_byte__total__bytes equ 2 i2c_send_byte__data equ i2c_send_byte__bytes__base+0 ; Send < data > to compass using I2c : i2c_send_byte__count equ i2c_send_byte__bytes__base+1 ; direction sda write ; Switch from register bank 0 to register bank 1 (which contains b___tris) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf b___tris,sda__bit movf b___tris,w tris 6 ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Send 8 - bits of data : ; `count_down count 8 ...' start movlw 8 ; Switch from register bank 1 to register bank 0 (which contains i2c_send_byte__count) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf i2c_send_byte__count i2c_send_byte__337_loop: ; sda := data @ 0 ; Alias variable for select data @ 0 i2c_send_byte__data__338select0 equ i2c_send_byte__data+0 i2c_send_byte__data__338select0__byte equ i2c_send_byte__data+0 i2c_send_byte__data__338select0__bit equ 0 btfss i2c_send_byte__data__338select0__byte,i2c_send_byte__data__338select0__bit bcf sda__byte,sda__bit btfsc i2c_send_byte__data__338select0__byte,i2c_send_byte__data__338select0__bit bsf sda__byte,sda__bit ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 0 bcf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; data := data >> 1 bcf c___byte,c___bit rrf i2c_send_byte__data,f decfsz i2c_send_byte__count,f goto i2c_send_byte__337_loop i2c_send_byte__337_done: ; `count_down count 8 ...' end ; Clock 1 more bit : ; sda := 0 bcf sda__byte,sda__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 1 bsf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; scl := 0 bcf scl__byte,scl__bit ; nop i2c_delay ; Delay 3 cycles nop nop nop ; procedure i2c_send_byte end retlw 0 ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; comment {The main procedure is loaded with switch statements . On the 12 - bit} ; comment {PIC ' s , switch statements have to live in the first 256 bytes of} ; comment {each code bank . For this reason , we shove main into code bank 1 .} ; comment {If we , try to put main in code bank 0 , it pushes the first bytes} ; comment {of several routines out of the first 256 bytes , which is also a} ; comment {no - no of the 12 - bit PIC ' s .} ; procedure main start switch__389block_start: addwf pcl___register,f goto switch__389block390 goto switch__389block401 goto switch__389block404 goto switch__389block407 goto switch__389block410 goto switch__389block410 goto switch__389block410 goto switch__389block410 switch__389block_end: ; switch_check 389 switch__389block_start switch__389block_end switch__450block_start: addwf pcl___register,f goto switch__450block451 goto switch__450block451 goto switch__450block451 goto switch__450block451 goto switch__450block456 goto switch__450block456 goto switch__450block460 goto switch__450block460 switch__450block_end: ; switch_check 450 switch__450block_start switch__450block_end switch__467block_start: addwf pcl___register,f goto switch__467block468 goto switch__467block472 goto switch__467block476 goto switch__467block480 goto switch__467block484 goto switch__467block492 goto switch__467block496 goto switch__467block501 switch__467block_end: ; switch_check 467 switch__467block_start switch__467block_end switch__425block_start: addwf pcl___register,f goto switch__425block426 goto switch__425block426 goto switch__425block426 goto switch__425block426 goto switch__425block426 goto switch__425block430 goto switch__425block444 goto switch__425block466 switch__425block_end: ; switch_check 425 switch__425block_start switch__425block_end switch__386block_start: addwf pcl___register,f goto switch__386block387 goto switch__386block415 goto switch__386block419 goto switch__386block423 switch__386block_end: ; switch_check 386 switch__386block_start switch__386block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+3 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+3 main__total__bytes equ 3 main__386byte0 equ main__bytes__base+2 main__425byte0 equ main__bytes__base+2 main__389byte0 equ main__bytes__base+2 ; arguments_none main__command equ main__bytes__base+0 main__temp equ main__bytes__base+1 ; Initalize all of the globals : ; interrupt_enable := 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Initialize remaining registers : ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf glitch ; index := 0 clrf index ; Process commands : ; loop_forever ... start main__381loop__forever: ; Wait for command : ; command := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__command ; Dispatch on command : ; switch { command >> 6 } swapf main__command,w movwf main__386byte0 rrf main__386byte0,f rrf main__386byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__386block_start switch__386block387: ; < Command = 00 xx xxxx > : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__389byte0 rrf main__389byte0,f rrf main__389byte0,w andlw 7 ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 5 6 7 goto switch__389block_start switch__389block390: ; < Command = 0000 0 xxx > : ; call i2c_start {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call i2c_start ; call i2c_send_byte {{ 0xc0 }} movlw 192 movwf i2c_send_byte__data call i2c_send_byte ; call i2c_send_byte {{ 1 }} movlw 1 movwf i2c_send_byte__data call i2c_send_byte ; call i2c_restart {{ }} call i2c_restart ; call i2c_send_byte {{ 0xc1 }} movlw 193 movwf i2c_send_byte__data call i2c_send_byte ; temporary := i2c_get_byte {{ }} call i2c_get_byte movf i2c_get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains temporary) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf temporary ; call i2c_stop {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call i2c_stop ; call send_byte {{ temporary }} ; Switch from register bank 0 to register bank 1 (which contains temporary) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf temporary,w movwf send_byte__char ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__389end switch__389block401: ; < Command = 0000 1 xxx > : goto switch__389end switch__389block404: ; < Command = 0001 0 xxx > : goto switch__389end switch__389block407: ; < Command = 0001 1 xxx > : goto switch__389end switch__389block410: ; < Command = 001 x xxxx > : switch__389end: goto switch__386end switch__386block415: ; < Command = 01 xx xxxx > : ; Do nothing : goto switch__386end switch__386block419: ; < Command = 10 xx xxxx > : ; Do nothing : goto switch__386end switch__386block423: ; < Command = 11 xx xxxx > : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__425byte0 rrf main__425byte0,f rrf main__425byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 goto switch__425block_start switch__425block426: ; < Command = 110 x xxxx or 1110 0 xxx > : ; Do nothing : goto switch__425end switch__425block430: ; < Command = 1110 1 xxx > : ; if { command = 0xef } start movlw 239 subwf main__command,w ; expression=`{ command = 0xef }' exp_delay=2 true_delay=6 false_delay=0 true_size=8 false_size=0 btfss z___byte,z___bit goto label432__0end ; if { command = 0xef } body start ; Read Interrupt Bits < Command = 1110 1111 > : ; temporary := 0 clrf temporary ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc interrupt_pending__byte,interrupt_pending__bit ; if { interrupt_pending } body start ; temporary @ 0 := 1 ; Select temporary @ 0 temporary__436select0 equ temporary+0 temporary__436select0__byte equ temporary+0 temporary__436select0__bit equ 0 ; Switch from register bank 0 to register bank 1 (which contains temporary__436select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bsf temporary__436select0__byte,temporary__436select0__bit ; if { interrupt_pending } body end ; if exp=`interrupt_pending' false skip delay=2 ; Other expression=`{ interrupt_pending }' delay=2 ; if { interrupt_pending } end ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc interrupt_enable__byte,interrupt_enable__bit ; if { interrupt_enable } body start ; temporary @ 1 := 1 ; Select temporary @ 1 temporary__439select0 equ temporary+0 temporary__439select0__byte equ temporary+0 temporary__439select0__bit equ 1 ; Switch from register bank 0 to register bank 1 (which contains temporary__439select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bsf temporary__439select0__byte,temporary__439select0__bit ; if { interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`{ interrupt_enable }' delay=2 ; if { interrupt_enable } end ; call send_byte {{ temporary }} movf temporary,w movwf send_byte__char ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { command = 0xef } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label432__0end: ; if exp=` command = 0xef ' empty false ; Other expression=`{ command = 0xef }' delay=-1 ; if { command = 0xef } end goto switch__425end switch__425block444: ; < Command = 1111 0 xxx > : ; Switching between register banks generates bulky code ; ; Keep code generation in bank 0 by assigning command to ; temporary : ; temporary := command movf main__command,w movwf temporary ; switch { temporary & 7 } movlw 7 andwf temporary,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 goto switch__450block_start switch__450block451: ; Set Interrupt Bits < Command = 1111 00 ep > : ; interrupt_enable := temporary @ 1 ; Alias variable for select temporary @ 1 temporary__453select0 equ temporary+0 temporary__453select0__byte equ temporary+0 temporary__453select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains temporary__453select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc temporary__453select0__byte,temporary__453select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__454select0 equ temporary+0 temporary__454select0__byte equ temporary+0 temporary__454select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains temporary__454select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc temporary__454select0__byte,temporary__454select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__450end switch__450block456: ; Set Interrupt Pending < Command = 1111 010 p > : ; interrupt_pending := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__458select0 equ temporary+0 temporary__458select0__byte equ temporary+0 temporary__458select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains temporary__458select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc temporary__458select0__byte,temporary__458select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__450end switch__450block460: ; Set Interrupt Enable < Command = 1111 011 e > : ; interrupt_enable := temporary @ 0 ; Alias variable for select temporary @ 0 temporary__462select0 equ temporary+0 temporary__462select0__byte equ temporary+0 temporary__462select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains temporary__462select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc temporary__462select0__byte,temporary__462select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__450end: goto switch__425end switch__425block466: ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__467block_start switch__467block468: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_lsb movlw 252 addwf osccal,f goto switch__467end switch__467block472: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_lsb movlw 4 addwf osccal,f goto switch__467end switch__467block476: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w movwf send_byte__char ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__467end switch__467block480: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__467end switch__467block484: ; ID Next < Command = 1111 1100 > : ; call send_byte {{ id ~~ {{ index }} }} incf index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id movwf send_byte__char call send_byte ; index := index + 1 ; Switch from register bank 0 to register bank 1 (which contains index) bsf rp0___byte,rp0___bit ; Register bank is now 1 incf index,f ; if { index >= id . size } start movlw 52 subwf index,w ; expression=`{ index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { index >= id . size } body start ; index := 0 clrf index ; if { index >= id . size } body end ; if exp=` index >= id . size ' false skip delay=4 ; Other expression=`{ index >= id . size }' delay=4 ; if { index >= id . size } end goto switch__467end switch__467block492: ; ID Reset < Command = 1111 1101 > : ; index := 0 clrf index goto switch__467end switch__467block496: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf glitch,w movwf send_byte__char ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__467end switch__467block501: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__467end: switch__425end: switch__386end: goto main__381loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 13 bytes of 24 available bytes ; Register bank 1 used 6 bytes of 16 available bytes ; Register bank 2 used 0 bytes of 16 available bytes ; Register bank 3 used 0 bytes of 16 available bytes end