1 radix dec 2 0008 global__variables__bank0 equ 8 3 0030 global__variables__bank1 equ 48 4 0050 global__variables__bank2 equ 80 5 0070 global__variables__bank3 equ 112 6 0012 global__bit__variables__bank0 equ 18 7 0039 global__bit__variables__bank1 equ 57 8 0050 global__bit__variables__bank2 equ 80 9 0070 global__bit__variables__bank3 equ 112 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 17 0004 rp0___byte equ 4 18 0005 rp0___bit equ 5 19 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 20 0004 rp1___byte equ 4 21 0006 rp1___bit equ 6 22 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 23 0003 pa0___byte equ 3 24 0005 pa0___bit equ 5 25 0004 fsr___register equ 4 26 org 0 27 start: 28 ; Use oscillator calibration value already in register W 29 000 025 movwf 5 30 ; Initialize TRIS registers 31 0039 b___tris equ global__variables__bank1+9 32 001 ccb movlw 203 33 002 006 tris 6 34 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 35 003 5a4 bsf rp0___byte,rp0___bit 36 ; Register bank is now 1 37 004 039 movwf b___tris 38 005 cc0 movlw 192 39 006 007 tris 7 40 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 41 007 5a3 bsf pa0___byte,pa0___bit 42 008 a65 goto main 43 ; comment ############################################################################# 44 ; comment {} 45 ; comment {Copyright < c > 2002 - 2003 by Wayne C . Gramlich and Bill Benson} 46 ; comment {All rights reserved .} 47 ; comment {} 48 ; comment {Permission to use , copy , modify , distribute , and sell this software} 49 ; comment {for any purpose is hereby granted without fee provided that the above} 50 ; comment {copyright notice and this permission are retained . The author makes} 51 ; comment {no representations about the suitability of this software for any purpose .} 52 ; comment {It is provided { as is } without express or implied warranty .} 53 ; comment {} 54 ; comment {This is the code that implements the CompassDT1 RoboBrick . Basically} 55 ; comment {it just waits for commands that come in at 2400 baud and responds} 56 ; comment {to them . See} 57 ; comment {} 58 ; comment {http : / / gramlich . net / projects / robobricks / compassdt1 / index . html} 59 ; comment {} 60 ; comment {for more details .} 61 ; comment {} 62 ; comment ############################################################################# 63 ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock 64 ; 4052=0xfd4 4095=0xfff 65 __config 4052 66 0fff configuration___address equ 4095 67 ; comment {Define processor constants :} 68 ; constant clock_rate 4000000 69 3d0900 clock_rate equ 4000000 70 ; constant clocks_per_instruction 4 71 0004 clocks_per_instruction equ 4 72 ; constant instruction_rate clock_rate / clocks_per_instruction 73 f4240 instruction_rate equ 1000000 74 ; comment {Define serial communication control constants :} 75 ; constant baud_rate 2400 76 0960 baud_rate equ 2400 77 ; constant instructions_per_bit instruction_rate / baud_rate 78 01a0 instructions_per_bit equ 416 79 ; constant delays_per_bit 3 80 0003 delays_per_bit equ 3 81 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 82 008a instructions_per_delay equ 138 83 ; constant extra_instructions_per_bit 9 84 0009 extra_instructions_per_bit equ 9 85 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 86 0003 extra_instructions_per_delay equ 3 87 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 88 0087 delay_instructions equ 135 89 ; comment {Register definitions :} 90 ; comment {Status register :} 91 0003 status equ 3 92 ; bind c status @ 0 93 0003 c equ status+0 94 0003 c__byte equ status+0 95 0000 c__bit equ 0 96 ; bind z status @ 2 97 0003 z equ status+0 98 0003 z__byte equ status+0 99 0002 z__bit equ 2 100 ; comment {OSCCAL register :} 101 0005 osccal equ 5 102 ; constant osccal_lsb 4 103 0004 osccal_lsb equ 4 104 ; constant i2c_delay 3 105 0003 i2c_delay equ 3 106 ; comment {Define bit offsets :} 107 ; constant d1_bit 5 108 0005 d1_bit equ 5 109 ; constant d2_bit 4 110 0004 d2_bit equ 4 111 ; constant d3_bit 3 112 0003 d3_bit equ 3 113 ; constant d4_bit 2 114 0002 d4_bit equ 2 115 ; constant d5_bit 1 116 0001 d5_bit equ 1 117 ; constant d6_bit 0 118 0000 d6_bit equ 0 119 ; constant scl_bit 0 120 0000 scl_bit equ 0 121 ; constant sda_bit 1 122 0001 sda_bit equ 1 123 ; constant freq_bit 2 124 0002 freq_bit equ 2 125 ; constant serial_in_bit 3 126 0003 serial_in_bit equ 3 127 ; constant serial_out_bit 4 128 0004 serial_out_bit equ 4 129 ; constant trigger_bit 5 130 0005 trigger_bit equ 5 131 ; comment {Define pin assignments and directions :} 132 0006 portb equ 6 133 0007 portc equ 7 134 0007 d1__byte equ 7 135 0005 d1__bit equ 5 136 0007 d2__byte equ 7 137 0004 d2__bit equ 4 138 0007 d3__byte equ 7 139 0003 d3__bit equ 3 140 0007 d4__byte equ 7 141 0002 d4__bit equ 2 142 0007 d5__byte equ 7 143 0001 d5__bit equ 1 144 0007 d6__byte equ 7 145 0000 d6__bit equ 0 146 0006 scl__byte equ 6 147 0000 scl__bit equ 0 148 0006 sda__byte equ 6 149 0001 sda__bit equ 1 150 0006 trigger__byte equ 6 151 0005 trigger__bit equ 5 152 0006 freq__byte equ 6 153 0002 freq__bit equ 2 154 0006 serial_out__byte equ 6 155 0004 serial_out__bit equ 4 156 0006 serial_in__byte equ 6 157 0003 serial_in__bit equ 3 158 ; constant mask 0x1f 159 001f mask equ 31 160 ; string_constants Start 161 ; Switch from register bank 1 to register bank 0 162 009 4a4 bcf rp0___byte,rp0___bit 163 ; Register bank is now 0 164 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 165 00a 4a3 bcf pa0___byte,pa0___bit 166 string___fetch: 167 00b 022 movwf pcl___register 168 ; id = 1 , 0 , 13 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 11 , 0s'CompassDT1C' , 15 , 0s'Gramlich&Benson' 169 0000 id___string equ 0 170 id: 171 00c 1e2 addwf pcl___register,f 172 ; Length = 52 173 00d 834 retlw 52 174 ; 1 175 00e 801 retlw 1 176 ; 0 177 00f 800 retlw 0 178 ; 13 179 010 80d retlw 13 180 ; 1 181 011 801 retlw 1 182 ; 0 183 012 800 retlw 0 184 ; 0 185 013 800 retlw 0 186 ; 0 187 014 800 retlw 0 188 ; 0 189 015 800 retlw 0 190 ; 0r'16' 191 016 833 retlw 51 ; random number 192 017 8d3 retlw 211 ; random number 193 018 849 retlw 73 ; random number 194 019 879 retlw 121 ; random number 195 01a 8a7 retlw 167 ; random number 196 01b 864 retlw 100 ; random number 197 01c 86a retlw 106 ; random number 198 01d 823 retlw 35 ; random number 199 01e 8ad retlw 173 ; random number 200 01f 86c retlw 108 ; random number 201 020 8a1 retlw 161 ; random number 202 021 891 retlw 145 ; random number 203 022 807 retlw 7 ; random number 204 023 80a retlw 10 ; random number 205 024 82a retlw 42 ; random number 206 025 8de retlw 222 ; random number 207 ; 11 208 026 80b retlw 11 209 ; `CompassDT1C' 210 027 843 retlw 67 211 028 86f retlw 111 212 029 86d retlw 109 213 02a 870 retlw 112 214 02b 861 retlw 97 215 02c 873 retlw 115 216 02d 873 retlw 115 217 02e 844 retlw 68 218 02f 854 retlw 84 219 030 831 retlw 49 220 031 843 retlw 67 221 ; 15 222 032 80f retlw 15 223 ; `Gramlich&Benson' 224 033 847 retlw 71 225 034 872 retlw 114 226 035 861 retlw 97 227 036 86d retlw 109 228 037 86c retlw 108 229 038 869 retlw 105 230 039 863 retlw 99 231 03a 868 retlw 104 232 03b 826 retlw 38 233 03c 842 retlw 66 234 03d 865 retlw 101 235 03e 86e retlw 110 236 03f 873 retlw 115 237 040 86f retlw 111 238 041 86e retlw 110 239 ; string__constants End 240 ; comment {Some globals : byte} 241 0012 interrupt_enable equ global__bit__variables__bank0+0 242 0012 interrupt_enable__byte equ global__bit__variables__bank0+0 243 0000 interrupt_enable__bit equ 0 244 0012 interrupt_pending equ global__bit__variables__bank0+0 245 0012 interrupt_pending__byte equ global__bit__variables__bank0+0 246 0001 interrupt_pending__bit equ 1 247 0012 receiving equ global__bit__variables__bank0+0 248 0012 receiving__byte equ global__bit__variables__bank0+0 249 0002 receiving__bit equ 2 250 ; bank 1 251 ; Default register bank is now 1 252 0030 temporary equ global__variables__bank1+0 253 0031 glitch equ global__variables__bank1+1 254 0032 index equ global__variables__bank1+2 255 ; comment {Note that the 12 - bit PIC ' s only have a 2 - level deep stack .} 256 ; comment {The code starts in the main procedure < located at the end of this code >} 257 ; comment {The next level of procedure call is either get_byte or send_byte .} 258 ; comment {Lastly , the lowest level of procedure call is delay . It all fits ,} 259 ; comment {but just barely .} 260 ; bank 0 261 ; Default register bank is now 0 262 263 ; procedure i2c_start start 264 i2c_start: 265 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 266 ; Procedure must be called with PCLATH set to code bank 0 267 0009 i2c_start__variables__base equ global__variables__bank0+1 268 0009 i2c_start__bytes__base equ i2c_start__variables__base+0 269 0009 i2c_start__bits__base equ i2c_start__variables__base+0 270 0001 i2c_start__total__bytes equ 1 271 ; arguments_none 272 ; Invariant : SCL = OC & SDA = OC 273 ; nop i2c_delay 274 ; Delay 3 cycles 275 042 000 nop 276 043 000 nop 277 044 000 nop 278 ; direction sda write 279 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 280 045 5a4 bsf rp0___byte,rp0___bit 281 ; Register bank is now 1 282 046 439 bcf b___tris,sda__bit 283 047 219 movf b___tris,w 284 048 006 tris 6 285 ; nop i2c_delay 286 ; Delay 3 cycles 287 049 000 nop 288 04a 000 nop 289 04b 000 nop 290 ; direction scl write 291 04c 419 bcf b___tris,scl__bit 292 04d 219 movf b___tris,w 293 04e 006 tris 6 294 ; nop i2c_delay 295 ; Delay 3 cycles 296 04f 000 nop 297 050 000 nop 298 051 000 nop 299 ; Invariant : SCL = 0 V & SDA = 0 V 300 ; procedure i2c_start end 301 ; Switch from register bank 1 to register bank 0 302 052 4a4 bcf rp0___byte,rp0___bit 303 ; Register bank is now 0 304 053 800 retlw 0 305 306 ; procedure i2c_restart start 307 i2c_restart: 308 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 309 ; Procedure must be called with PCLATH set to code bank 0 310 000a i2c_restart__variables__base equ global__variables__bank0+2 311 000a i2c_restart__bytes__base equ i2c_restart__variables__base+0 312 000a i2c_restart__bits__base equ i2c_restart__variables__base+0 313 0000 i2c_restart__total__bytes equ 0 314 ; arguments_none 315 ; nop i2c_delay 316 ; Delay 3 cycles 317 054 000 nop 318 055 000 nop 319 056 000 nop 320 ; direction sda read 321 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 322 057 5a4 bsf rp0___byte,rp0___bit 323 ; Register bank is now 1 324 058 539 bsf b___tris,sda__bit 325 059 219 movf b___tris,w 326 05a 006 tris 6 327 ; nop i2c_delay 328 ; Delay 3 cycles 329 05b 000 nop 330 05c 000 nop 331 05d 000 nop 332 ; direction scl read 333 05e 519 bsf b___tris,scl__bit 334 05f 219 movf b___tris,w 335 060 006 tris 6 336 ; nop i2c_delay 337 ; Delay 3 cycles 338 061 000 nop 339 062 000 nop 340 063 000 nop 341 ; direction sda write 342 064 439 bcf b___tris,sda__bit 343 065 219 movf b___tris,w 344 066 006 tris 6 345 ; nop i2c_delay 346 ; Delay 3 cycles 347 067 000 nop 348 068 000 nop 349 069 000 nop 350 ; direction scl write 351 06a 419 bcf b___tris,scl__bit 352 06b 219 movf b___tris,w 353 06c 006 tris 6 354 ; procedure i2c_restart end 355 ; Switch from register bank 1 to register bank 0 356 06d 4a4 bcf rp0___byte,rp0___bit 357 ; Register bank is now 0 358 06e 800 retlw 0 359 360 ; procedure i2c_stop start 361 i2c_stop: 362 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 363 ; Procedure must be called with PCLATH set to code bank 0 364 000a i2c_stop__variables__base equ global__variables__bank0+2 365 000a i2c_stop__bytes__base equ i2c_stop__variables__base+0 366 000a i2c_stop__bits__base equ i2c_stop__variables__base+0 367 0000 i2c_stop__total__bytes equ 0 368 ; arguments_none 369 ; Invariant : SCL = 0 V & SDA = 0 V 370 ; nop i2c_delay 371 ; Delay 3 cycles 372 06f 000 nop 373 070 000 nop 374 071 000 nop 375 ; direction scl read 376 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 377 072 5a4 bsf rp0___byte,rp0___bit 378 ; Register bank is now 1 379 073 519 bsf b___tris,scl__bit 380 074 219 movf b___tris,w 381 075 006 tris 6 382 ; nop i2c_delay 383 ; Delay 3 cycles 384 076 000 nop 385 077 000 nop 386 078 000 nop 387 ; direction sda read 388 079 539 bsf b___tris,sda__bit 389 07a 219 movf b___tris,w 390 07b 006 tris 6 391 ; nop i2c_delay 392 ; Delay 3 cycles 393 07c 000 nop 394 07d 000 nop 395 07e 000 nop 396 ; Invariant : SCL = OC & SDA = OC 397 ; procedure i2c_stop end 398 ; Switch from register bank 1 to register bank 0 399 07f 4a4 bcf rp0___byte,rp0___bit 400 ; Register bank is now 0 401 080 800 retlw 0 402 403 ; procedure i2c_get_byte start 404 i2c_get_byte: 405 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 406 ; Procedure must be called with PCLATH set to code bank 0 407 000a i2c_get_byte__variables__base equ global__variables__bank0+2 408 000a i2c_get_byte__bytes__base equ i2c_get_byte__variables__base+0 409 000d i2c_get_byte__bits__base equ i2c_get_byte__variables__base+3 410 0003 i2c_get_byte__total__bytes equ 3 411 ; arguments_none 412 000a i2c_get_byte__0return__byte equ i2c_get_byte__bytes__base+0 413 ; This procedure will wait for a byte to be received from 414 ; serial_in_bit . It calls the delay procedure for all delays . 415 000b i2c_get_byte__count equ i2c_get_byte__bytes__base+1 416 000c i2c_get_byte__char equ i2c_get_byte__bytes__base+2 417 ; Invariant : SCL = 0 V & SDA = 0 V 418 ; direction sda read 419 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 420 081 5a4 bsf rp0___byte,rp0___bit 421 ; Register bank is now 1 422 082 539 bsf b___tris,sda__bit 423 083 219 movf b___tris,w 424 084 006 tris 6 425 ; `count_down count 8 ...' start 426 085 c08 movlw 8 427 086 02b movwf i2c_get_byte__count 428 ; Switch from register bank 1 to register bank 0 429 087 4a4 bcf rp0___byte,rp0___bit 430 ; Register bank is now 0 431 i2c_get_byte__158_loop: 432 ; char := char << 1 433 088 403 bcf c___byte,c___bit 434 089 36c rlf i2c_get_byte__char,f 435 ; nop i2c_delay 436 ; Delay 3 cycles 437 08a 000 nop 438 08b 000 nop 439 08c 000 nop 440 ; direction scl read 441 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 442 08d 5a4 bsf rp0___byte,rp0___bit 443 ; Register bank is now 1 444 08e 519 bsf b___tris,scl__bit 445 08f 219 movf b___tris,w 446 090 006 tris 6 447 ; nop i2c_delay 448 ; Delay 3 cycles 449 091 000 nop 450 092 000 nop 451 093 000 nop 452 ; if { sda } start 453 ; expression=`{ sda }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 454 094 626 btfsc sda__byte,sda__bit 455 ; if { sda } body start 456 ; char @ 0 := 1 457 ; Select char @ 0 458 000c i2c_get_byte__char__165select0 equ i2c_get_byte__char+0 459 000c i2c_get_byte__char__165select0__byte equ i2c_get_byte__char+0 460 0000 i2c_get_byte__char__165select0__bit equ 0 461 095 50c bsf i2c_get_byte__char__165select0__byte,i2c_get_byte__char__165select0__bit 462 ; if { sda } body end 463 ; if exp=`sda' false skip delay=2 464 ; Other expression=`{ sda }' delay=2 465 ; if { sda } end 466 ; direction scl write 467 096 419 bcf b___tris,scl__bit 468 097 219 movf b___tris,w 469 098 006 tris 6 470 ; nop i2c_delay 471 ; Delay 3 cycles 472 099 000 nop 473 09a 000 nop 474 09b 000 nop 475 ; Switch from register bank 1 to register bank 0 476 09c 4a4 bcf rp0___byte,rp0___bit 477 ; Register bank is now 0 478 ; Request switch to bank 0 479 09d 2eb decfsz i2c_get_byte__count,f 480 09e a88 goto i2c_get_byte__158_loop 481 i2c_get_byte__158_done: 482 ; `count_down count 8 ...' end 483 ; Clock in ACK bit : 484 ; direction sda write 485 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 486 09f 5a4 bsf rp0___byte,rp0___bit 487 ; Register bank is now 1 488 0a0 439 bcf b___tris,sda__bit 489 0a1 219 movf b___tris,w 490 0a2 006 tris 6 491 ; nop i2c_delay 492 ; Delay 3 cycles 493 0a3 000 nop 494 0a4 000 nop 495 0a5 000 nop 496 ; direction scl read 497 0a6 519 bsf b___tris,scl__bit 498 0a7 219 movf b___tris,w 499 0a8 006 tris 6 500 ; nop i2c_delay 501 ; Delay 3 cycles 502 0a9 000 nop 503 0aa 000 nop 504 0ab 000 nop 505 ; direction scl write 506 0ac 419 bcf b___tris,scl__bit 507 0ad 219 movf b___tris,w 508 0ae 006 tris 6 509 ; nop i2c_delay 510 ; Delay 3 cycles 511 0af 000 nop 512 0b0 000 nop 513 0b1 000 nop 514 ; Invariant : SCL = 0 V & SDA = 0 V 515 ; return char 516 0b2 20c movf i2c_get_byte__char,w 517 0b3 02a movwf i2c_get_byte__0return__byte 518 ; Switch from register bank 1 to register bank 0 519 0b4 4a4 bcf rp0___byte,rp0___bit 520 ; Register bank is now 0 521 0b5 800 retlw 0 522 ; procedure i2c_get_byte end 523 524 ; procedure i2c_send_byte start 525 i2c_send_byte: 526 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 527 ; Procedure must be called with PCLATH set to code bank 0 528 000d i2c_send_byte__variables__base equ global__variables__bank0+5 529 000d i2c_send_byte__bytes__base equ i2c_send_byte__variables__base+0 530 000f i2c_send_byte__bits__base equ i2c_send_byte__variables__base+2 531 0002 i2c_send_byte__total__bytes equ 2 532 000d i2c_send_byte__data equ i2c_send_byte__bytes__base+0 533 ; Send < data > to compass using I2c : 534 000e i2c_send_byte__count equ i2c_send_byte__bytes__base+1 535 ; Invariant : SCL = 0 V & SDA = 0 V 536 ; Send 8 - bits of data : 537 ; `count_down count 8 ...' start 538 0b6 c08 movlw 8 539 0b7 02e movwf i2c_send_byte__count 540 i2c_send_byte__194_loop: 541 ; if { data @ 7 } start 542 ; Alias variable for select data @ 7 543 000d i2c_send_byte__data__195select0 equ i2c_send_byte__data+0 544 000d i2c_send_byte__data__195select0__byte equ i2c_send_byte__data+0 545 0007 i2c_send_byte__data__195select0__bit equ 7 546 ; expression=`{ data @ 7 }' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=2 547 0b8 7ed btfss i2c_send_byte__data__195select0__byte,i2c_send_byte__data__195select0__bit 548 0b9 abe goto label195__1false 549 label195__1true: 550 ; if { data @ 7 } body start 551 ; direction sda read 552 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 553 0ba 5a4 bsf rp0___byte,rp0___bit 554 ; Register bank is now 1 555 0bb 539 bsf b___tris,sda__bit 556 ; 2 instructions found for sharing 557 ; Switch from register bank 1 to register bank 0 558 0bc 4a4 bcf rp0___byte,rp0___bit 559 ; Register bank is now 0 560 0bd ac1 goto label195__1end 561 label195__1false: 562 ; else body start 563 ; direction sda write 564 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 565 0be 5a4 bsf rp0___byte,rp0___bit 566 ; Register bank is now 1 567 0bf 439 bcf b___tris,sda__bit 568 ; 2 instructions found for sharing 569 ; if exp=` data @ 7 ' generic 570 ; Switch from register bank 1 to register bank 0 571 0c0 4a4 bcf rp0___byte,rp0___bit 572 ; Register bank is now 0 573 label195__1end: 574 ; Other expression=`{ data @ 7 }' delay=-1 575 ; 2 shared instructions follow 576 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 577 0c1 5a4 bsf rp0___byte,rp0___bit 578 ; Register bank is now 1 579 0c2 219 movf b___tris,w 580 0c3 006 tris 6 581 ; if { data @ 7 } end 582 ; data := data << 1 583 0c4 403 bcf c___byte,c___bit 584 0c5 36d rlf i2c_send_byte__data,f 585 ; nop i2c_delay 586 ; Delay 3 cycles 587 0c6 000 nop 588 0c7 000 nop 589 0c8 000 nop 590 ; direction scl write 591 0c9 419 bcf b___tris,scl__bit 592 0ca 219 movf b___tris,w 593 0cb 006 tris 6 594 ; nop i2c_delay 595 ; Delay 3 cycles 596 0cc 000 nop 597 0cd 000 nop 598 0ce 000 nop 599 ; direction sda read 600 0cf 539 bsf b___tris,sda__bit 601 0d0 219 movf b___tris,w 602 0d1 006 tris 6 603 ; nop i2c_delay 604 ; Delay 3 cycles 605 0d2 000 nop 606 0d3 000 nop 607 0d4 000 nop 608 ; Switch from register bank 1 to register bank 0 609 0d5 4a4 bcf rp0___byte,rp0___bit 610 ; Register bank is now 0 611 ; Request switch to bank 0 612 0d6 2ee decfsz i2c_send_byte__count,f 613 0d7 ab8 goto i2c_send_byte__194_loop 614 i2c_send_byte__194_done: 615 ; `count_down count 8 ...' end 616 ; Clock in ACK bit : 617 ; direction sda read 618 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 619 0d8 5a4 bsf rp0___byte,rp0___bit 620 ; Register bank is now 1 621 0d9 539 bsf b___tris,sda__bit 622 0da 219 movf b___tris,w 623 0db 006 tris 6 624 ; nop i2c_delay 625 ; Delay 3 cycles 626 0dc 000 nop 627 0dd 000 nop 628 0de 000 nop 629 ; direction scl read 630 0df 519 bsf b___tris,scl__bit 631 0e0 219 movf b___tris,w 632 0e1 006 tris 6 633 ; count := 255 634 0e2 cff movlw 255 635 0e3 02e movwf i2c_send_byte__count 636 ; `while sda && count != 0 ...' start 637 ; Switch from register bank 1 to register bank 0 638 0e4 4a4 bcf rp0___byte,rp0___bit 639 ; Register bank is now 0 640 i2c_send_byte__213while__continue: 641 ; expression=`sda' exp_delay=0 true_delay=-1 false_delay=4 true_size=5 false_size=1 642 0e5 726 btfss sda__byte,sda__bit 643 0e6 ae9 goto and213__0false 644 0e7 20e movf i2c_send_byte__count,w 645 ; expression=`count != 0' exp_delay=1 true_delay=3 false_delay=2 true_size=2 false_size=1 646 0e8 643 btfsc z___byte,z___bit 647 and213__0false: 648 0e9 aec goto i2c_send_byte__213while__break 649 and213__0true: 650 ; count := count - 1 651 0ea 0ee decf i2c_send_byte__count,f 652 0eb ae5 goto i2c_send_byte__213while__continue 653 ; if exp=`count != 0' false goto 654 ; Other expression=`count != 0' delay=-1 655 ; if exp=`sda' false goto 656 ; Other expression=`sda' delay=-1 657 and213__0end: 658 i2c_send_byte__213while__break: 659 ; `while sda && count != 0 ...' end 660 ; direction scl write 661 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 662 0ec 5a4 bsf rp0___byte,rp0___bit 663 ; Register bank is now 1 664 0ed 419 bcf b___tris,scl__bit 665 0ee 219 movf b___tris,w 666 0ef 006 tris 6 667 ; count := 255 668 0f0 cff movlw 255 669 0f1 02e movwf i2c_send_byte__count 670 ; `while ! sda && count != 0 ...' start 671 ; Switch from register bank 1 to register bank 0 672 0f2 4a4 bcf rp0___byte,rp0___bit 673 ; Register bank is now 0 674 i2c_send_byte__218while__continue: 675 ; expression=`sda' exp_delay=0 true_delay=4 false_delay=-1 true_size=1 false_size=5 676 0f3 626 btfsc sda__byte,sda__bit 677 0f4 af7 goto and218__0false 678 0f5 20e movf i2c_send_byte__count,w 679 ; expression=`count != 0' exp_delay=1 true_delay=3 false_delay=2 true_size=2 false_size=1 680 0f6 643 btfsc z___byte,z___bit 681 and218__0false: 682 0f7 afa goto i2c_send_byte__218while__break 683 and218__0true: 684 ; count := count - 1 685 0f8 0ee decf i2c_send_byte__count,f 686 0f9 af3 goto i2c_send_byte__218while__continue 687 ; if exp=`count != 0' false goto 688 ; Other expression=`count != 0' delay=-1 689 ; if exp=`sda' true goto 690 ; Other expression=`sda' delay=-1 691 and218__0end: 692 i2c_send_byte__218while__break: 693 ; `while ! sda && count != 0 ...' end 694 ; Grab the SDA back again : 695 ; direction sda write 696 ; Switch from register bank 0 to register bank 1 (which contains b___tris) 697 0fa 5a4 bsf rp0___byte,rp0___bit 698 ; Register bank is now 1 699 0fb 439 bcf b___tris,sda__bit 700 0fc 219 movf b___tris,w 701 0fd 006 tris 6 702 ; Invariant : SCL = 0 V & SDA = 0 V 703 ; procedure i2c_send_byte end 704 ; Switch from register bank 1 to register bank 0 705 0fe 4a4 bcf rp0___byte,rp0___bit 706 ; Register bank is now 0 707 0ff 800 retlw 0 708 709 ; procedure get_byte start 710 get_byte: 711 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 712 ; Procedure must be called with PCLATH set to code bank 0 713 000f get_byte__variables__base equ global__variables__bank0+7 714 000f get_byte__bytes__base equ get_byte__variables__base+0 715 0012 get_byte__bits__base equ get_byte__variables__base+3 716 0003 get_byte__total__bytes equ 3 717 ; arguments_none 718 000f get_byte__0return__byte equ get_byte__bytes__base+0 719 ; This procedure will wait for a byte to be received from 720 ; serial_in_bit . It calls the delay procedure for all delays . 721 0010 get_byte__count equ get_byte__bytes__base+1 722 0011 get_byte__char equ get_byte__bytes__base+2 723 ; Why does the delay procedure wait for a third of bit ? Well , it 724 ; has to do with the loop immediately below . If we catch the 725 ; start bit at the beginning of a 1 / 3 bit time , we will be 726 ; sampling data at approximately 1 / 3 of the way into each bit . 727 ; Conversely , if we catch the start near the end of a 1 / 3 bit 728 ; bit time , we will be sampling data at approximately 2 / 3 of the 729 ; way into each bit . So , what this means is that our bit sample 730 ; times will be somewhere between 1 / 3 and 2 / 3 of bit < i . e . in 731 ; the middle of the bit . 732 ; It would be nice to tweak the code to shorter delay times 733 ; < 1 / 4 bit , 1 / 5 bit , etc . > but then it gets too hard to get 734 ; the bookeeping done in the delay routine . A 12 - bit PIC 735 ; running at 4 MHz <= 1 MIPS > , only has 138 instructions available 736 ; for the delay routine when at 1 / 3 of bit . 737 ; Wait for a start bit : 738 ; receiving := 1 739 100 552 bsf receiving__byte,receiving__bit 740 ; `while serial_in ...' start 741 get_byte__255while__continue: 742 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 743 101 766 btfss serial_in__byte,serial_in__bit 744 102 b09 goto get_byte__255while__break 745 ; call delay {{ }} 746 ; Switch from register bank 0 to register bank 1 747 103 5a4 bsf rp0___byte,rp0___bit 748 ; Register bank is now 1 749 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 750 104 5a3 bsf pa0___byte,pa0___bit 751 105 92d call delay 752 ; Switch from register bank 1 to register bank 0 753 106 4a4 bcf rp0___byte,rp0___bit 754 ; Register bank is now 0 755 ; Switch from code bank 1 to code bank 0 before possible transfer (goto) 756 107 4a3 bcf pa0___byte,pa0___bit 757 108 b01 goto get_byte__255while__continue 758 ; if exp=`serial_in' false goto 759 ; Other expression=`serial_in' delay=-1 760 get_byte__255while__break: 761 ; `while serial_in ...' end 762 ; Clear interrupt : 763 ; 1 cycle : 764 ; serial_out := 1 765 109 586 bsf serial_out__byte,serial_out__bit 766 ; Skip over start bit : 767 ; call delay {{ }} 768 ; Switch from register bank 0 to register bank 1 769 10a 5a4 bsf rp0___byte,rp0___bit 770 ; Register bank is now 1 771 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 772 10b 5a3 bsf pa0___byte,pa0___bit 773 10c 92d call delay 774 ; call delay {{ }} 775 10d 92d call delay 776 ; call delay {{ }} 777 10e 92d call delay 778 ; Sample in the middle third of each data bit ; 779 ; 1 cycle : 780 ; char := 0 781 ; Switch from register bank 1 to register bank 0 (which contains get_byte__char) 782 10f 4a4 bcf rp0___byte,rp0___bit 783 ; Register bank is now 0 784 110 071 clrf get_byte__char 785 ; 2 cycles to set up loop : 786 ; 1 + 1 + 2 = 4 787 ; nop extra_instructions_per_bit - 4 788 ; Delay 5 cycles 789 111 000 nop 790 112 000 nop 791 113 000 nop 792 114 000 nop 793 115 000 nop 794 ; `count_down count 8 ...' start 795 116 c08 movlw 8 796 117 030 movwf get_byte__count 797 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 798 118 4a3 bcf pa0___byte,pa0___bit 799 get_byte__274_loop: 800 ; call delay {{ }} 801 ; Switch from register bank 0 to register bank 1 802 119 5a4 bsf rp0___byte,rp0___bit 803 ; Register bank is now 1 804 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 805 11a 5a3 bsf pa0___byte,pa0___bit 806 11b 92d call delay 807 ; 2 cycles : 808 ; char := char >> 1 809 11c 403 bcf c___byte,c___bit 810 ; Switch from register bank 1 to register bank 0 (which contains get_byte__char) 811 11d 4a4 bcf rp0___byte,rp0___bit 812 ; Register bank is now 0 813 11e 331 rrf get_byte__char,f 814 ; 2 cycles : 815 ; if { serial_in } start 816 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 817 ; Switch from code bank 1 to code bank 0 before possible transfer (btfsc) 818 11f 4a3 bcf pa0___byte,pa0___bit 819 120 666 btfsc serial_in__byte,serial_in__bit 820 ; if { serial_in } body start 821 ; char @ 7 := 1 822 ; Select char @ 7 823 0011 get_byte__char__280select0 equ get_byte__char+0 824 0011 get_byte__char__280select0__byte equ get_byte__char+0 825 0007 get_byte__char__280select0__bit equ 7 826 121 5f1 bsf get_byte__char__280select0__byte,get_byte__char__280select0__bit 827 ; if { serial_in } body end 828 ; if exp=`serial_in' false skip delay=2 829 ; Other expression=`{ serial_in }' delay=2 830 ; if { serial_in } end 831 ; call delay {{ }} 832 ; Switch from register bank 0 to register bank 1 833 122 5a4 bsf rp0___byte,rp0___bit 834 ; Register bank is now 1 835 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 836 123 5a3 bsf pa0___byte,pa0___bit 837 124 92d call delay 838 ; call delay {{ }} 839 125 92d call delay 840 ; 3 cycles at end of loop : 841 ; 2 + 2 + 3 = 7 842 ; nop extra_instructions_per_bit - 7 843 ; Delay 2 cycles 844 126 000 nop 845 127 000 nop 846 ; Switch from register bank 1 to register bank 0 (which contains get_byte__count) 847 128 4a4 bcf rp0___byte,rp0___bit 848 ; Register bank is now 0 849 ; Switch from code bank 1 to code bank 0 before possible transfer (decfsz) 850 129 4a3 bcf pa0___byte,pa0___bit 851 12a 2f0 decfsz get_byte__count,f 852 12b b19 goto get_byte__274_loop 853 get_byte__274_done: 854 ; `count_down count 8 ...' end 855 ; Skip over 2 / 3 ' s of stop bit : 856 ; call delay {{ }} 857 ; Switch from register bank 0 to register bank 1 858 12c 5a4 bsf rp0___byte,rp0___bit 859 ; Register bank is now 1 860 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 861 12d 5a3 bsf pa0___byte,pa0___bit 862 12e 92d call delay 863 ; call delay {{ }} 864 12f 92d call delay 865 ; return char 866 ; Switch from register bank 1 to register bank 0 (which contains get_byte__char) 867 130 4a4 bcf rp0___byte,rp0___bit 868 ; Register bank is now 0 869 131 211 movf get_byte__char,w 870 132 02f movwf get_byte__0return__byte 871 ; Switch from code bank 1 to code bank 0 before possible transfer (retlw) 872 133 4a3 bcf pa0___byte,pa0___bit 873 134 800 retlw 0 874 ; procedure get_byte end 875 ; origin 0x200 876 org 512 877 ; bank 1 878 ; Default register bank is now 1 879 880 ; procedure send_byte start 881 send_byte: 882 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 883 ; Procedure must be called with PCLATH set to code bank 0 884 0033 send_byte__variables__base equ global__variables__bank1+3 885 0033 send_byte__bytes__base equ send_byte__variables__base+0 886 0035 send_byte__bits__base equ send_byte__variables__base+2 887 0002 send_byte__total__bytes equ 2 888 0033 send_byte__char equ send_byte__bytes__base+0 889 ; Send < char > to < tx > : 890 0034 send_byte__count equ send_byte__bytes__base+1 891 ; < receiving > will be 1 if the last get / put routine was a get . 892 ; Before we start transmitting a response back , we want to ensure 893 ; that there has been enough time to turn the line around . 894 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 895 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 896 ; for good measure . Technically , the second call to delay < > 897 ; is not really needed . 898 ; if { receiving } start 899 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 900 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 901 200 4a4 bcf rp0___byte,rp0___bit 902 ; Register bank is now 0 903 201 443 bcf z___byte,z___bit 904 202 652 btfsc receiving__byte,receiving__bit 905 203 543 bsf z___byte,z___bit 906 ; Switch from register bank 0 to register bank 1 907 204 5a4 bsf rp0___byte,rp0___bit 908 ; Register bank is now 1 909 205 743 btfss z___byte,z___bit 910 206 a0c goto label313__0end 911 ; if { receiving } body start 912 ; receiving := 0 913 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 914 207 4a4 bcf rp0___byte,rp0___bit 915 ; Register bank is now 0 916 208 452 bcf receiving__byte,receiving__bit 917 ; call delay {{ }} 918 ; Switch from register bank 0 to register bank 1 919 209 5a4 bsf rp0___byte,rp0___bit 920 ; Register bank is now 1 921 20a 92d call delay 922 ; call delay {{ }} 923 20b 92d call delay 924 ; if { receiving } body end 925 label313__0end: 926 ; if exp=`receiving' empty false 927 ; Other expression=`{ receiving }' delay=-1 928 ; if { receiving } end 929 ; Send the start bit : 930 ; 1 cycle : 931 ; serial_out := 0 932 20c 486 bcf serial_out__byte,serial_out__bit 933 ; call delay {{ }} 934 20d 92d call delay 935 ; call delay {{ }} 936 20e 92d call delay 937 ; call delay {{ }} 938 20f 92d call delay 939 ; 2 cycles to set up loop : 940 ; 1 + 2 = 3 941 ; nop extra_instructions_per_bit - 3 942 ; Delay 6 cycles 943 210 000 nop 944 211 000 nop 945 212 000 nop 946 213 000 nop 947 214 000 nop 948 215 000 nop 949 ; Send the data : 950 ; `count_down count 8 ...' start 951 216 c08 movlw 8 952 217 034 movwf send_byte__count 953 send_byte__331_loop: 954 ; 4 cycles : 955 ; serial_out := char @ 0 956 ; Alias variable for select char @ 0 957 0033 send_byte__char__333select0 equ send_byte__char+0 958 0033 send_byte__char__333select0__byte equ send_byte__char+0 959 0000 send_byte__char__333select0__bit equ 0 960 218 713 btfss send_byte__char__333select0__byte,send_byte__char__333select0__bit 961 219 486 bcf serial_out__byte,serial_out__bit 962 21a 613 btfsc send_byte__char__333select0__byte,send_byte__char__333select0__bit 963 21b 586 bsf serial_out__byte,serial_out__bit 964 ; 2 cycles : 965 ; char := char >> 1 966 21c 403 bcf c___byte,c___bit 967 21d 333 rrf send_byte__char,f 968 ; call delay {{ }} 969 21e 92d call delay 970 ; call delay {{ }} 971 21f 92d call delay 972 ; call delay {{ }} 973 220 92d call delay 974 ; 3 cycles at end of loop : 975 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 976 221 2f4 decfsz send_byte__count,f 977 222 a18 goto send_byte__331_loop 978 send_byte__331_done: 979 ; `count_down count 8 ...' end 980 ; Send the stop bit : 981 ; nop 1 982 ; Delay 1 cycles 983 223 000 nop 984 ; 1 cycle 985 ; serial_out := 1 986 224 586 bsf serial_out__byte,serial_out__bit 987 ; call delay {{ }} 988 225 92d call delay 989 ; call delay {{ }} 990 226 92d call delay 991 ; call delay {{ }} 992 227 92d call delay 993 ; 2 cycles for call / return 994 ; 2 cycles for argument 995 ; 1 + 2 + 2 = 5 996 ; nop extra_instructions_per_bit - 5 997 ; Delay 4 cycles 998 228 000 nop 999 229 000 nop 1000 22a 000 nop 1001 22b 000 nop 1002 ; procedure send_byte end 1003 22c 800 retlw 0 1004 1005 ; procedure delay start 1006 ; optimize 0 1007 delay: 1008 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1009 ; Procedure must be called with PCLATH set to code bank 0 1010 0035 delay__variables__base equ global__variables__bank1+5 1011 0035 delay__bytes__base equ delay__variables__base+0 1012 0036 delay__bits__base equ delay__variables__base+1 1013 0001 delay__total__bytes equ 1 1014 0035 delay__356byte1 equ delay__bytes__base+0 1015 ; arguments_none 1016 ; uniform_delay delay_instructions 1017 ; Uniform delay remaining = 131 Accumulated Delay = 0 1018 ; Uniform delay remaining = 131 Accumulated Delay = 0 1019 ; This procedure delays 1 / 3 of a bit . 1020 ; Uniform delay remaining = 131 Accumulated Delay = 0 1021 ; Uniform delay remaining = 131 Accumulated Delay = 0 1022 ; Kick the dog : 1023 ; Uniform delay remaining = 131 Accumulated Delay = 0 1024 ; watch_dog_reset 1025 22d 004 clrwdt 1026 ; Uniform delay remaining = 130 Accumulated Delay = 1 1027 ; Uniform delay remaining = 130 Accumulated Delay = 1 1028 ; Soak up remaining 130 cycles 1029 ; Delay 130 cycles 1030 22e c2b movlw 43 1031 22f 035 movwf delay__356byte1 1032 delay__356delay0: 1033 230 2f5 decfsz delay__356byte1,f 1034 231 a30 goto delay__356delay0 1035 ; procedure delay end 1036 232 800 retlw 0 1037 ; optimize 1 1038 ; comment {The main procedure is loaded with switch statements . On the 12 - bit} 1039 ; comment {PIC ' s , switch statements have to live in the first 256 bytes of} 1040 ; comment {each code bank . For this reason , we shove main into code bank 1 .} 1041 ; comment {If we , try to put main in code bank 0 , it pushes the first bytes} 1042 ; comment {of several routines out of the first 256 bytes , which is also a} 1043 ; comment {no - no of the 12 - bit PIC ' s .} 1044 1045 ; procedure main start 1046 switch__424block_start: 1047 233 1e2 addwf pcl___register,f 1048 234 aa2 goto switch__424block425 1049 235 ac0 goto switch__424block438 1050 236 adb goto switch__424block450 1051 237 ae2 goto switch__424block455 1052 238 b1e goto switch__424block475 1053 239 b1e goto switch__424block475 1054 23a b1e goto switch__424block475 1055 23b b1e goto switch__424block475 1056 switch__424block_end: 1057 ; switch_check 424 switch__424block_start switch__424block_end 1058 switch__421block_start: 1059 23c 1e2 addwf pcl___register,f 1060 23d a9f goto switch__421block422 1061 23e b1f goto switch__421block480 1062 23f b20 goto switch__421block483 1063 240 b21 goto switch__421block486 1064 241 b22 goto switch__421block489 1065 242 b22 goto switch__421block489 1066 243 b22 goto switch__421block489 1067 244 b22 goto switch__421block489 1068 switch__421block_end: 1069 ; switch_check 421 switch__421block_start switch__421block_end 1070 switch__529block_start: 1071 245 1e2 addwf pcl___register,f 1072 246 b42 goto switch__529block530 1073 247 b42 goto switch__529block530 1074 248 b42 goto switch__529block530 1075 249 b42 goto switch__529block530 1076 24a b55 goto switch__529block535 1077 24b b55 goto switch__529block535 1078 24c b60 goto switch__529block539 1079 24d b60 goto switch__529block539 1080 switch__529block_end: 1081 ; switch_check 529 switch__529block_start switch__529block_end 1082 switch__546block_start: 1083 24e 1e2 addwf pcl___register,f 1084 24f b6e goto switch__546block547 1085 250 b71 goto switch__546block551 1086 251 b74 goto switch__546block555 1087 252 b78 goto switch__546block559 1088 253 b7b goto switch__546block563 1089 254 b89 goto switch__546block571 1090 255 b8b goto switch__546block575 1091 256 b90 goto switch__546block580 1092 switch__546block_end: 1093 ; switch_check 546 switch__546block_start switch__546block_end 1094 switch__504block_start: 1095 257 1e2 addwf pcl___register,f 1096 258 b2b goto switch__504block505 1097 259 b2b goto switch__504block505 1098 25a b2b goto switch__504block505 1099 25b b2b goto switch__504block505 1100 25c b2b goto switch__504block505 1101 25d b2c goto switch__504block509 1102 25e b3d goto switch__504block523 1103 25f b6b goto switch__504block545 1104 switch__504block_end: 1105 ; switch_check 504 switch__504block_start switch__504block_end 1106 switch__418block_start: 1107 260 1e2 addwf pcl___register,f 1108 261 a99 goto switch__418block419 1109 262 b23 goto switch__418block494 1110 263 b24 goto switch__418block498 1111 264 b25 goto switch__418block502 1112 switch__418block_end: 1113 ; switch_check 418 switch__418block_start switch__418block_end 1114 main: 1115 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1116 ; Procedure must be called with PCLATH set to code bank 0 1117 0036 main__variables__base equ global__variables__bank1+6 1118 0036 main__bytes__base equ main__variables__base+0 1119 0039 main__bits__base equ main__variables__base+3 1120 0003 main__total__bytes equ 3 1121 0038 main__504byte0 equ main__bytes__base+2 1122 0038 main__418byte0 equ main__bytes__base+2 1123 0038 main__467byte1 equ main__bytes__base+2 1124 0038 main__464byte1 equ main__bytes__base+2 1125 0038 main__421byte0 equ main__bytes__base+2 1126 0038 main__461byte1 equ main__bytes__base+2 1127 0038 main__403byte1 equ main__bytes__base+2 1128 0038 main__397byte1 equ main__bytes__base+2 1129 ; arguments_none 1130 0036 main__command equ main__bytes__base+0 1131 0037 main__temp equ main__bytes__base+1 1132 ; Initalize all of the globals : 1133 ; interrupt_enable := 0 1134 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1135 265 4a4 bcf rp0___byte,rp0___bit 1136 ; Register bank is now 0 1137 266 412 bcf interrupt_enable__byte,interrupt_enable__bit 1138 ; interrupt_pending := 0 1139 267 432 bcf interrupt_pending__byte,interrupt_pending__bit 1140 ; Initialize remaining registers : 1141 ; glitch := 0 1142 ; Switch from register bank 0 to register bank 1 (which contains glitch) 1143 268 5a4 bsf rp0___byte,rp0___bit 1144 ; Register bank is now 1 1145 269 071 clrf glitch 1146 ; index := 0 1147 26a 072 clrf index 1148 ; Set up the SCL bus : 1149 ; direction sda read 1150 26b 539 bsf b___tris,sda__bit 1151 26c 219 movf b___tris,w 1152 26d 006 tris 6 1153 ; direction scl read 1154 26e 519 bsf b___tris,scl__bit 1155 26f 219 movf b___tris,w 1156 270 006 tris 6 1157 ; sda := 0 1158 271 426 bcf sda__byte,sda__bit 1159 ; scl := 0 1160 272 406 bcf scl__byte,scl__bit 1161 ; trigger := 0 1162 273 4a6 bcf trigger__byte,trigger__bit 1163 ; loop_forever ... start 1164 main__396loop__forever: 1165 ; nop 40 1166 ; Delay 40 cycles 1167 274 c0d movlw 13 1168 275 038 movwf main__397byte1 1169 main__397delay0: 1170 276 2f8 decfsz main__397byte1,f 1171 277 a76 goto main__397delay0 1172 ; trigger := 0 1173 278 4a6 bcf trigger__byte,trigger__bit 1174 ; sda := 0 1175 279 426 bcf sda__byte,sda__bit 1176 ; scl := 0 1177 27a 406 bcf scl__byte,scl__bit 1178 ; direction scl read 1179 27b 519 bsf b___tris,scl__bit 1180 27c 219 movf b___tris,w 1181 27d 006 tris 6 1182 ; direction sda read 1183 27e 539 bsf b___tris,sda__bit 1184 27f 219 movf b___tris,w 1185 280 006 tris 6 1186 ; nop 60 1187 ; Delay 60 cycles 1188 281 c13 movlw 19 1189 282 038 movwf main__403byte1 1190 main__403delay0: 1191 283 2f8 decfsz main__403byte1,f 1192 284 a83 goto main__403delay0 1193 285 000 nop 1194 286 000 nop 1195 ; trigger := 1 1196 287 5a6 bsf trigger__byte,trigger__bit 1197 ; sda := 0 1198 288 426 bcf sda__byte,sda__bit 1199 ; scl := 0 1200 289 406 bcf scl__byte,scl__bit 1201 ; direction scl write 1202 28a 419 bcf b___tris,scl__bit 1203 28b 219 movf b___tris,w 1204 28c 006 tris 6 1205 ; direction sda write 1206 28d 439 bcf b___tris,sda__bit 1207 28e 219 movf b___tris,w 1208 28f 006 tris 6 1209 290 a74 goto main__396loop__forever 1210 ; loop_forever ... end 1211 ; Process commands : 1212 ; loop_forever ... start 1213 main__412loop__forever: 1214 ; Wait for command : 1215 ; command := get_byte < > 1216 ; command := 3 1217 291 c03 movlw 3 1218 292 036 movwf main__command 1219 ; Dispatch on command : 1220 ; switch { command >> 6 } 1221 293 396 swapf main__command,w 1222 294 038 movwf main__418byte0 1223 295 338 rrf main__418byte0,f 1224 296 318 rrf main__418byte0,w 1225 297 e03 andlw 3 1226 ; case 0 1227 ; case 1 1228 ; case 2 1229 ; case 3 1230 298 a60 goto switch__418block_start 1231 switch__418block419: 1232 ; < Command = 00 xx xxxx > : 1233 ; switch { {{ command >> 3 }} & 7 } 1234 299 316 rrf main__command,w 1235 29a 038 movwf main__421byte0 1236 29b 338 rrf main__421byte0,f 1237 29c 318 rrf main__421byte0,w 1238 29d e07 andlw 7 1239 ; case 0 1240 ; case 1 1241 ; case 2 1242 ; case 3 1243 ; case 4 5 6 7 1244 29e a3c goto switch__421block_start 1245 switch__421block422: 1246 ; < Command = 0000 0 xxx > : 1247 ; switch { command & 7 } 1248 29f c07 movlw 7 1249 2a0 156 andwf main__command,w 1250 ; case 0 1251 ; case 1 1252 ; case 2 1253 ; case 3 1254 ; case 4 5 6 7 1255 2a1 a33 goto switch__424block_start 1256 switch__424block425: 1257 ; < Command = 0000 0000 > : 1258 ; call send_byte {{ 0xa4 }} 1259 2a2 ca4 movlw 164 1260 2a3 033 movwf send_byte__char 1261 2a4 900 call send_byte 1262 ; call i2c_start {{ }} 1263 ; Switch from register bank 1 to register bank 0 1264 2a5 4a4 bcf rp0___byte,rp0___bit 1265 ; Register bank is now 0 1266 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1267 2a6 4a3 bcf pa0___byte,pa0___bit 1268 2a7 942 call i2c_start 1269 ; call i2c_send_byte {{ 0xc0 }} 1270 2a8 cc0 movlw 192 1271 2a9 02d movwf i2c_send_byte__data 1272 2aa 9b6 call i2c_send_byte 1273 ; call i2c_send_byte {{ 1 }} 1274 2ab c01 movlw 1 1275 2ac 02d movwf i2c_send_byte__data 1276 2ad 9b6 call i2c_send_byte 1277 ; call i2c_restart {{ }} 1278 2ae 954 call i2c_restart 1279 ; call i2c_send_byte {{ 0xc1 }} 1280 2af cc1 movlw 193 1281 2b0 02d movwf i2c_send_byte__data 1282 2b1 9b6 call i2c_send_byte 1283 ; temporary := i2c_get_byte {{ }} 1284 2b2 981 call i2c_get_byte 1285 2b3 20a movf i2c_get_byte__0return__byte,w 1286 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1287 2b4 5a4 bsf rp0___byte,rp0___bit 1288 ; Register bank is now 1 1289 2b5 030 movwf temporary 1290 ; call i2c_stop {{ }} 1291 ; Switch from register bank 1 to register bank 0 1292 2b6 4a4 bcf rp0___byte,rp0___bit 1293 ; Register bank is now 0 1294 2b7 96f call i2c_stop 1295 ; call send_byte {{ temporary }} 1296 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1297 2b8 5a4 bsf rp0___byte,rp0___bit 1298 ; Register bank is now 1 1299 2b9 210 movf temporary,w 1300 2ba 033 movwf send_byte__char 1301 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 1302 2bb 5a3 bsf pa0___byte,pa0___bit 1303 2bc 900 call send_byte 1304 ; portc := temporary 1305 2bd 210 movf temporary,w 1306 2be 027 movwf portc 1307 2bf b1e goto switch__424end 1308 switch__424block438: 1309 ; < Command = 0000 0001 > : 1310 ; call send_byte {{ 0xa5 }} 1311 2c0 ca5 movlw 165 1312 2c1 033 movwf send_byte__char 1313 2c2 900 call send_byte 1314 ; call i2c_start {{ }} 1315 ; Switch from register bank 1 to register bank 0 1316 2c3 4a4 bcf rp0___byte,rp0___bit 1317 ; Register bank is now 0 1318 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1319 2c4 4a3 bcf pa0___byte,pa0___bit 1320 2c5 942 call i2c_start 1321 ; call i2c_send_byte {{ 0xc0 }} 1322 2c6 cc0 movlw 192 1323 2c7 02d movwf i2c_send_byte__data 1324 2c8 9b6 call i2c_send_byte 1325 ; call i2c_send_byte {{ 0 }} 1326 2c9 06d clrf i2c_send_byte__data 1327 2ca 9b6 call i2c_send_byte 1328 ; call i2c_restart {{ }} 1329 2cb 954 call i2c_restart 1330 ; call i2c_send_byte {{ 0xc1 }} 1331 2cc cc1 movlw 193 1332 2cd 02d movwf i2c_send_byte__data 1333 2ce 9b6 call i2c_send_byte 1334 ; temporary := i2c_get_byte {{ }} 1335 2cf 981 call i2c_get_byte 1336 2d0 20a movf i2c_get_byte__0return__byte,w 1337 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1338 2d1 5a4 bsf rp0___byte,rp0___bit 1339 ; Register bank is now 1 1340 2d2 030 movwf temporary 1341 ; call i2c_stop {{ }} 1342 ; Switch from register bank 1 to register bank 0 1343 2d3 4a4 bcf rp0___byte,rp0___bit 1344 ; Register bank is now 0 1345 2d4 96f call i2c_stop 1346 ; call send_byte {{ temporary }} 1347 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1348 2d5 5a4 bsf rp0___byte,rp0___bit 1349 ; Register bank is now 1 1350 2d6 210 movf temporary,w 1351 2d7 033 movwf send_byte__char 1352 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 1353 2d8 5a3 bsf pa0___byte,pa0___bit 1354 2d9 900 call send_byte 1355 2da b1e goto switch__424end 1356 switch__424block450: 1357 ; < Command = 0001 0 xxx > : 1358 ; call send_byte {{ 2 }} 1359 2db c02 movlw 2 1360 2dc 033 movwf send_byte__char 1361 2dd 900 call send_byte 1362 ; call send_byte {{ 3 }} 1363 2de c03 movlw 3 1364 2df 033 movwf send_byte__char 1365 2e0 900 call send_byte 1366 2e1 b1e goto switch__424end 1367 switch__424block455: 1368 ; loop_forever ... start 1369 main__456loop__forever: 1370 ; trigger := 1 1371 2e2 5a6 bsf trigger__byte,trigger__bit 1372 ; nop 5 1373 ; Delay 5 cycles 1374 2e3 000 nop 1375 2e4 000 nop 1376 2e5 000 nop 1377 2e6 000 nop 1378 2e7 000 nop 1379 ; call i2c_start {{ }} 1380 ; Switch from register bank 1 to register bank 0 1381 2e8 4a4 bcf rp0___byte,rp0___bit 1382 ; Register bank is now 0 1383 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1384 2e9 4a3 bcf pa0___byte,pa0___bit 1385 2ea 942 call i2c_start 1386 ; call i2c_send_byte {{ 0xc0 }} 1387 2eb cc0 movlw 192 1388 2ec 02d movwf i2c_send_byte__data 1389 2ed 9b6 call i2c_send_byte 1390 ; nop 50 1391 ; Delay 50 cycles 1392 2ee c10 movlw 16 1393 ; Switch from register bank 0 to register bank 1 (which contains main__461byte1) 1394 2ef 5a4 bsf rp0___byte,rp0___bit 1395 ; Register bank is now 1 1396 2f0 038 movwf main__461byte1 1397 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1398 2f1 5a3 bsf pa0___byte,pa0___bit 1399 main__461delay0: 1400 2f2 2f8 decfsz main__461byte1,f 1401 2f3 af2 goto main__461delay0 1402 2f4 000 nop 1403 ; call i2c_send_byte {{ 0 }} 1404 2f5 06d clrf i2c_send_byte__data 1405 ; Switch from register bank 1 to register bank 0 1406 2f6 4a4 bcf rp0___byte,rp0___bit 1407 ; Register bank is now 0 1408 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1409 2f7 4a3 bcf pa0___byte,pa0___bit 1410 2f8 9b6 call i2c_send_byte 1411 ; call i2c_stop {{ }} 1412 2f9 96f call i2c_stop 1413 ; nop 50 1414 ; Delay 50 cycles 1415 2fa c10 movlw 16 1416 ; Switch from register bank 0 to register bank 1 (which contains main__464byte1) 1417 2fb 5a4 bsf rp0___byte,rp0___bit 1418 ; Register bank is now 1 1419 2fc 038 movwf main__464byte1 1420 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1421 2fd 5a3 bsf pa0___byte,pa0___bit 1422 main__464delay0: 1423 2fe 2f8 decfsz main__464byte1,f 1424 2ff afe goto main__464delay0 1425 300 000 nop 1426 ; call i2c_start {{ }} 1427 ; Switch from register bank 1 to register bank 0 1428 301 4a4 bcf rp0___byte,rp0___bit 1429 ; Register bank is now 0 1430 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1431 302 4a3 bcf pa0___byte,pa0___bit 1432 303 942 call i2c_start 1433 ; call i2c_send_byte {{ 0xc1 }} 1434 304 cc1 movlw 193 1435 305 02d movwf i2c_send_byte__data 1436 306 9b6 call i2c_send_byte 1437 ; nop 50 1438 ; Delay 50 cycles 1439 307 c10 movlw 16 1440 ; Switch from register bank 0 to register bank 1 (which contains main__467byte1) 1441 308 5a4 bsf rp0___byte,rp0___bit 1442 ; Register bank is now 1 1443 309 038 movwf main__467byte1 1444 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1445 30a 5a3 bsf pa0___byte,pa0___bit 1446 main__467delay0: 1447 30b 2f8 decfsz main__467byte1,f 1448 30c b0b goto main__467delay0 1449 30d 000 nop 1450 ; temporary := i2c_get_byte {{ }} 1451 ; Switch from register bank 1 to register bank 0 1452 30e 4a4 bcf rp0___byte,rp0___bit 1453 ; Register bank is now 0 1454 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1455 30f 4a3 bcf pa0___byte,pa0___bit 1456 310 981 call i2c_get_byte 1457 311 20a movf i2c_get_byte__0return__byte,w 1458 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1459 312 5a4 bsf rp0___byte,rp0___bit 1460 ; Register bank is now 1 1461 313 030 movwf temporary 1462 ; call i2c_stop {{ }} 1463 ; Switch from register bank 1 to register bank 0 1464 314 4a4 bcf rp0___byte,rp0___bit 1465 ; Register bank is now 0 1466 315 96f call i2c_stop 1467 ; portc := temporary 1468 ; Switch from register bank 0 to register bank 1 (which contains temporary) 1469 316 5a4 bsf rp0___byte,rp0___bit 1470 ; Register bank is now 1 1471 317 210 movf temporary,w 1472 318 027 movwf portc 1473 ; trigger := 0 1474 319 4a6 bcf trigger__byte,trigger__bit 1475 ; call delay {{ }} 1476 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 1477 31a 5a3 bsf pa0___byte,pa0___bit 1478 31b 92d call delay 1479 31c ae2 goto main__456loop__forever 1480 ; loop_forever ... end 1481 31d b1e goto switch__424end 1482 switch__424block475: 1483 ; < Command = = < 0000 01 xx > : 1484 switch__424end: 1485 31e b22 goto switch__421end 1486 switch__421block480: 1487 ; < Command = 0000 1 xxx > : 1488 31f b22 goto switch__421end 1489 switch__421block483: 1490 ; < Command = 0001 0 xxx > : 1491 320 b22 goto switch__421end 1492 switch__421block486: 1493 ; < Command = 0001 1 xxx > : 1494 321 b22 goto switch__421end 1495 switch__421block489: 1496 ; < Command = 001 x xxxx > : 1497 switch__421end: 1498 322 b93 goto switch__418end 1499 switch__418block494: 1500 ; < Command = 01 xx xxxx > : 1501 ; Do nothing : 1502 323 b93 goto switch__418end 1503 switch__418block498: 1504 ; < Command = 10 xx xxxx > : 1505 ; Do nothing : 1506 324 b93 goto switch__418end 1507 switch__418block502: 1508 ; < Command = 11 xx xxxx > : 1509 ; switch { {{ command >> 3 }} & 7 } 1510 325 316 rrf main__command,w 1511 326 038 movwf main__504byte0 1512 327 338 rrf main__504byte0,f 1513 328 318 rrf main__504byte0,w 1514 329 e07 andlw 7 1515 ; case 0 1 2 3 4 1516 ; case 5 1517 ; case 6 1518 ; case 7 1519 32a a57 goto switch__504block_start 1520 switch__504block505: 1521 ; < Command = 110 x xxxx or 1110 0 xxx > : 1522 ; Do nothing : 1523 32b b93 goto switch__504end 1524 switch__504block509: 1525 ; < Command = 1110 1 xxx > : 1526 ; if { command = 0xef } start 1527 32c cef movlw 239 1528 32d 096 subwf main__command,w 1529 ; expression=`{ command = 0xef }' exp_delay=2 true_delay=6 false_delay=0 true_size=8 false_size=0 1530 32e 743 btfss z___byte,z___bit 1531 32f b3c goto label511__0end 1532 ; if { command = 0xef } body start 1533 ; Read Interrupt Bits < Command = 1110 1111 > : 1534 ; temporary := 0 1535 330 070 clrf temporary 1536 ; if { interrupt_pending } start 1537 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1538 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1539 331 4a4 bcf rp0___byte,rp0___bit 1540 ; Register bank is now 0 1541 332 632 btfsc interrupt_pending__byte,interrupt_pending__bit 1542 ; if { interrupt_pending } body start 1543 ; temporary @ 0 := 1 1544 ; Select temporary @ 0 1545 0030 temporary__515select0 equ temporary+0 1546 0030 temporary__515select0__byte equ temporary+0 1547 0000 temporary__515select0__bit equ 0 1548 ; Switch from register bank 0 to register bank 1 (which contains temporary__515select0__byte) 1549 333 5a4 bsf rp0___byte,rp0___bit 1550 ; Register bank is now 1 1551 334 510 bsf temporary__515select0__byte,temporary__515select0__bit 1552 ; if { interrupt_pending } body end 1553 ; if exp=`interrupt_pending' false skip delay=2 1554 ; Other expression=`{ interrupt_pending }' delay=2 1555 ; if { interrupt_pending } end 1556 ; if { interrupt_enable } start 1557 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1558 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1559 335 4a4 bcf rp0___byte,rp0___bit 1560 ; Register bank is now 0 1561 336 612 btfsc interrupt_enable__byte,interrupt_enable__bit 1562 ; if { interrupt_enable } body start 1563 ; temporary @ 1 := 1 1564 ; Select temporary @ 1 1565 0030 temporary__518select0 equ temporary+0 1566 0030 temporary__518select0__byte equ temporary+0 1567 0001 temporary__518select0__bit equ 1 1568 ; Switch from register bank 0 to register bank 1 (which contains temporary__518select0__byte) 1569 337 5a4 bsf rp0___byte,rp0___bit 1570 ; Register bank is now 1 1571 338 530 bsf temporary__518select0__byte,temporary__518select0__bit 1572 ; if { interrupt_enable } body end 1573 ; if exp=`interrupt_enable' false skip delay=2 1574 ; Other expression=`{ interrupt_enable }' delay=2 1575 ; if { interrupt_enable } end 1576 ; call send_byte {{ temporary }} 1577 339 210 movf temporary,w 1578 33a 033 movwf send_byte__char 1579 33b 900 call send_byte 1580 ; if { command = 0xef } body end 1581 label511__0end: 1582 ; if exp=` command = 0xef ' empty false 1583 ; Other expression=`{ command = 0xef }' delay=-1 1584 ; if { command = 0xef } end 1585 33c b93 goto switch__504end 1586 switch__504block523: 1587 ; < Command = 1111 0 xxx > : 1588 ; Switching between register banks generates bulky code ; 1589 ; Keep code generation in bank 0 by assigning command to 1590 ; temporary : 1591 ; temporary := command 1592 33d 216 movf main__command,w 1593 33e 030 movwf temporary 1594 ; switch { temporary & 7 } 1595 33f c07 movlw 7 1596 340 150 andwf temporary,w 1597 ; case 0 1 2 3 1598 ; case 4 5 1599 ; case 6 7 1600 341 a45 goto switch__529block_start 1601 switch__529block530: 1602 ; Set Interrupt Bits < Command = 1111 00 ep > : 1603 ; interrupt_enable := temporary @ 1 1604 ; Alias variable for select temporary @ 1 1605 0030 temporary__532select0 equ temporary+0 1606 0030 temporary__532select0__byte equ temporary+0 1607 0001 temporary__532select0__bit equ 1 1608 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1609 342 4a4 bcf rp0___byte,rp0___bit 1610 ; Register bank is now 0 1611 343 412 bcf interrupt_enable__byte,interrupt_enable__bit 1612 ; Switch from register bank 0 to register bank 1 (which contains temporary__532select0__byte) 1613 344 5a4 bsf rp0___byte,rp0___bit 1614 ; Register bank is now 1 1615 345 443 bcf z___byte,z___bit 1616 346 630 btfsc temporary__532select0__byte,temporary__532select0__bit 1617 347 543 bsf z___byte,z___bit 1618 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1619 348 4a4 bcf rp0___byte,rp0___bit 1620 ; Register bank is now 0 1621 349 643 btfsc z___byte,z___bit 1622 34a 512 bsf interrupt_enable__byte,interrupt_enable__bit 1623 ; interrupt_pending := temporary @ 0 1624 ; Alias variable for select temporary @ 0 1625 0030 temporary__533select0 equ temporary+0 1626 0030 temporary__533select0__byte equ temporary+0 1627 0000 temporary__533select0__bit equ 0 1628 34b 432 bcf interrupt_pending__byte,interrupt_pending__bit 1629 ; Switch from register bank 0 to register bank 1 (which contains temporary__533select0__byte) 1630 34c 5a4 bsf rp0___byte,rp0___bit 1631 ; Register bank is now 1 1632 34d 443 bcf z___byte,z___bit 1633 34e 610 btfsc temporary__533select0__byte,temporary__533select0__bit 1634 34f 543 bsf z___byte,z___bit 1635 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1636 350 4a4 bcf rp0___byte,rp0___bit 1637 ; Register bank is now 0 1638 351 643 btfsc z___byte,z___bit 1639 352 532 bsf interrupt_pending__byte,interrupt_pending__bit 1640 ; Switch from register bank 0 to register bank 1 1641 353 5a4 bsf rp0___byte,rp0___bit 1642 ; Register bank is now 1 1643 354 b6a goto switch__529end 1644 switch__529block535: 1645 ; Set Interrupt Pending < Command = 1111 010 p > : 1646 ; interrupt_pending := temporary @ 0 1647 ; Alias variable for select temporary @ 0 1648 0030 temporary__537select0 equ temporary+0 1649 0030 temporary__537select0__byte equ temporary+0 1650 0000 temporary__537select0__bit equ 0 1651 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1652 355 4a4 bcf rp0___byte,rp0___bit 1653 ; Register bank is now 0 1654 356 432 bcf interrupt_pending__byte,interrupt_pending__bit 1655 ; Switch from register bank 0 to register bank 1 (which contains temporary__537select0__byte) 1656 357 5a4 bsf rp0___byte,rp0___bit 1657 ; Register bank is now 1 1658 358 443 bcf z___byte,z___bit 1659 359 610 btfsc temporary__537select0__byte,temporary__537select0__bit 1660 35a 543 bsf z___byte,z___bit 1661 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1662 35b 4a4 bcf rp0___byte,rp0___bit 1663 ; Register bank is now 0 1664 35c 643 btfsc z___byte,z___bit 1665 35d 532 bsf interrupt_pending__byte,interrupt_pending__bit 1666 ; Switch from register bank 0 to register bank 1 1667 35e 5a4 bsf rp0___byte,rp0___bit 1668 ; Register bank is now 1 1669 35f b6a goto switch__529end 1670 switch__529block539: 1671 ; Set Interrupt Enable < Command = 1111 011 e > : 1672 ; interrupt_enable := temporary @ 0 1673 ; Alias variable for select temporary @ 0 1674 0030 temporary__541select0 equ temporary+0 1675 0030 temporary__541select0__byte equ temporary+0 1676 0000 temporary__541select0__bit equ 0 1677 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1678 360 4a4 bcf rp0___byte,rp0___bit 1679 ; Register bank is now 0 1680 361 412 bcf interrupt_enable__byte,interrupt_enable__bit 1681 ; Switch from register bank 0 to register bank 1 (which contains temporary__541select0__byte) 1682 362 5a4 bsf rp0___byte,rp0___bit 1683 ; Register bank is now 1 1684 363 443 bcf z___byte,z___bit 1685 364 610 btfsc temporary__541select0__byte,temporary__541select0__bit 1686 365 543 bsf z___byte,z___bit 1687 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1688 366 4a4 bcf rp0___byte,rp0___bit 1689 ; Register bank is now 0 1690 367 643 btfsc z___byte,z___bit 1691 368 512 bsf interrupt_enable__byte,interrupt_enable__bit 1692 ; Switch from register bank 0 to register bank 1 1693 369 5a4 bsf rp0___byte,rp0___bit 1694 ; Register bank is now 1 1695 switch__529end: 1696 36a b93 goto switch__504end 1697 switch__504block545: 1698 ; switch { command & 7 } 1699 36b c07 movlw 7 1700 36c 156 andwf main__command,w 1701 ; case 0 1702 ; case 1 1703 ; case 2 1704 ; case 3 1705 ; case 4 1706 ; case 5 1707 ; case 6 1708 ; case 7 1709 36d a4e goto switch__546block_start 1710 switch__546block547: 1711 ; Clock Decrement < Command = 1111 1000 > : 1712 ; osccal := osccal - osccal_lsb 1713 36e cfc movlw 252 1714 36f 1e5 addwf osccal,f 1715 370 b93 goto switch__546end 1716 switch__546block551: 1717 ; Clock Increment < Command = 1111 1001 > : 1718 ; osccal := osccal + osccal_lsb 1719 371 c04 movlw 4 1720 372 1e5 addwf osccal,f 1721 373 b93 goto switch__546end 1722 switch__546block555: 1723 ; Clock Read < Command = 1111 1010 > : 1724 ; call send_byte {{ osccal }} 1725 374 205 movf osccal,w 1726 375 033 movwf send_byte__char 1727 376 900 call send_byte 1728 377 b93 goto switch__546end 1729 switch__546block559: 1730 ; Clock Pulse < Command = 1111 1011 > : 1731 ; call send_byte {{ 0 }} 1732 378 073 clrf send_byte__char 1733 379 900 call send_byte 1734 37a b93 goto switch__546end 1735 switch__546block563: 1736 ; ID Next < Command = 1111 1100 > : 1737 ; call send_byte {{ id ~~ {{ index }} }} 1738 37b 292 incf index,w 1739 ; Switch from register bank 1 to register bank 0 1740 37c 4a4 bcf rp0___byte,rp0___bit 1741 ; Register bank is now 0 1742 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1743 37d 4a3 bcf pa0___byte,pa0___bit 1744 37e 90c call id 1745 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 1746 37f 5a4 bsf rp0___byte,rp0___bit 1747 ; Register bank is now 1 1748 380 033 movwf send_byte__char 1749 ; Switch from code bank 0 to code bank 1 before possible transfer (call) 1750 381 5a3 bsf pa0___byte,pa0___bit 1751 382 900 call send_byte 1752 ; index := index + 1 1753 383 2b2 incf index,f 1754 ; if { index >= id . size } start 1755 384 c34 movlw 52 1756 385 092 subwf index,w 1757 ; expression=`{ index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1758 386 603 btfsc c___byte,c___bit 1759 ; if { index >= id . size } body start 1760 ; index := 0 1761 387 072 clrf index 1762 ; if { index >= id . size } body end 1763 ; if exp=` index >= id . size ' false skip delay=4 1764 ; Other expression=`{ index >= id . size }' delay=4 1765 ; if { index >= id . size } end 1766 388 b93 goto switch__546end 1767 switch__546block571: 1768 ; ID Reset < Command = 1111 1101 > : 1769 ; index := 0 1770 389 072 clrf index 1771 38a b93 goto switch__546end 1772 switch__546block575: 1773 ; Glitch Read < Command = 1111 1110 > : 1774 ; call send_byte {{ glitch }} 1775 38b 211 movf glitch,w 1776 38c 033 movwf send_byte__char 1777 38d 900 call send_byte 1778 ; glitch := 0 1779 38e 071 clrf glitch 1780 38f b93 goto switch__546end 1781 switch__546block580: 1782 ; Glitch < Command = 1111 1111 > : 1783 ; if { glitch != 0xff } start 1784 390 291 incf glitch,w 1785 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1786 391 743 btfss z___byte,z___bit 1787 ; if { glitch != 0xff } body start 1788 ; glitch := glitch + 1 1789 392 2b1 incf glitch,f 1790 ; if { glitch != 0xff } body end 1791 ; if exp=` glitch != 0xff ' false skip delay=3 1792 ; Other expression=`{ glitch != 0xff }' delay=3 1793 ; if { glitch != 0xff } end 1794 switch__546end: 1795 switch__504end: 1796 switch__418end: 1797 393 a91 goto main__412loop__forever 1798 ; loop_forever ... end 1799 ; procedure main end 1800 1801 ; Register bank 0 used 10 bytes of 24 available bytes 1802 ; Register bank 1 used 9 bytes of 16 available bytes 1803 ; Register bank 2 used 0 bytes of 16 available bytes 1804 ; Register bank 3 used 0 bytes of 16 available bytes 1805 1806 end