radix dec global__variables__bank0 equ 7 global__variables__bank1 equ 48 global__bit__variables__bank0 equ 23 global__bit__variables__bank1 equ 58 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) rp0___byte equ 4 rp0___bit equ 5 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) rp1___byte equ 4 rp1___bit equ 6 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) pa0___byte equ 3 pa0___bit equ 5 fsr___register equ 4 org 0 start: ; Use oscillator calibration value already in register W movwf 5 ; Initialize TRIS registers movlw 218 tris 6 ; Initialize OPTION register movlw 192 option ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the BIROD2 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / birod2 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12c509 cp = off wdte = on mclre = off fosc = intrc ; 14=0xe 4095=0xfff __config 14 configuration___address equ 4095 ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {Define serial communication control constants :} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; constant extra_instructions_per_bit 9 extra_instructions_per_bit equ 9 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit extra_instructions_per_delay equ 3 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay delay_instructions equ 135 ; comment {Register definitions :} ; comment {Status register :} status equ 3 ; bind c status @ 0 c equ status+0 c__byte equ status+0 c__bit equ 0 ; bind z status @ 2 z equ status+0 z__byte equ status+0 z__bit equ 2 ; comment {OSCCAL register :} osccal equ 5 ; constant osccal_unit 4 osccal_unit equ 4 ; comment {constant osccal_unit 0x10} ; comment {Define I / O port bit assignments :} porta equ 6 out0__byte equ 6 out0__bit equ 0 in0__byte equ 6 in0__bit equ 1 out1__byte equ 6 out1__bit equ 2 in1__byte equ 6 in1__bit equ 3 serial_in__byte equ 6 serial_in__bit equ 4 serial_out__byte equ 6 serial_out__bit equ 5 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (label) bcf pa0___byte,pa0___bit string___fetch: movwf pcl___register ; id = 1 , 0 , 11 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'BIROD2B' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 48 retlw 48 ; 1 retlw 1 ; 0 retlw 0 ; 11 retlw 11 ; 1 retlw 1 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 10 ; random number retlw 46 ; random number retlw 60 ; random number retlw 156 ; random number retlw 25 ; random number retlw 122 ; random number retlw 12 ; random number retlw 184 ; random number retlw 102 ; random number retlw 174 ; random number retlw 240 ; random number retlw 223 ; random number retlw 192 ; random number retlw 38 ; random number retlw 5 ; random number retlw 61 ; random number ; 7 retlw 7 ; `BIROD2B' retlw 66 retlw 73 retlw 82 retlw 79 retlw 68 retlw 50 retlw 66 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 alternate equ global__bit__variables__bank0+0 alternate__byte equ global__bit__variables__bank0+0 alternate__bit equ 2 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 3 ; comment {Various masks < low order two bits only > :} inputs equ global__variables__bank0+0 enable equ global__variables__bank0+1 complement equ global__variables__bank0+2 falling equ global__variables__bank0+3 high equ global__variables__bank0+4 low equ global__variables__bank0+5 raising equ global__variables__bank0+6 ; comment {For now put all the smaller routines first so that they can live} ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} ; comment {can only call routines that are within the first 256 bytes < i . e .} ; comment {the first half > of the code page .} ; bank 1 ; Default register bank is now 1 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank1+0 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bsf receiving__byte,receiving__bit ; `while serial_in ...' start ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 get_byte__101while__continue: ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__101while__break ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto get_byte__101while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__101while__break: ; `while serial_in ...' end ; Clear interrupt : ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; 1 cycle : ; char := 0 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf get_byte__char ; 2 cycles to set up loop : ; 1 + 1 + 2 = 4 ; nop extra_instructions_per_bit - 4 ; Delay 5 cycles nop nop nop nop nop ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__120_loop: ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf get_byte__char,f ; 2 cycles : ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__126select0 equ get_byte__char+0 get_byte__char__126select0__byte equ get_byte__char+0 get_byte__char__126select0__bit equ 7 bsf get_byte__char__126select0__byte,get_byte__char__126select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; nop extra_instructions_per_bit - 7 ; Delay 2 cycles nop nop ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz get_byte__count,f goto get_byte__120_loop get_byte__120_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; return char ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank1+3 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc receiving__byte,receiving__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label156__0end ; if { receiving } body start ; receiving := 0 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 label156__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Send the data : ; `count_down count 8 ...' start movlw 8 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__count send_byte__169_loop: ; 4 cycles : ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__171select0 equ send_byte__char+0 send_byte__char__171select0__byte equ send_byte__char+0 send_byte__char__171select0__bit equ 0 btfss send_byte__char__171select0__byte,send_byte__char__171select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__171select0__byte,send_byte__char__171select0__bit bsf serial_out__byte,serial_out__bit ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 4 + 2 + 3 = 9 = no NOP ' s needed : ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) bsf rp0___byte,rp0___bit ; Register bank is now 1 decfsz send_byte__count,f goto send_byte__169_loop send_byte__169_done: ; `count_down count 8 ...' end ; Send the stop bit : ; 1 cycle to close out previous loop : ; nop 1 ; Delay 1 cycles nop ; 1 cylce : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for call / return : ; 2 cycles for argument : ; 1 + 2 + 2 = 5 ; nop extra_instructions_per_bit - 5 ; Delay 4 cycles nop nop nop nop ; procedure send_byte end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 retlw 0 ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+7 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+8 delay__total__bytes equ 9 delay__264byte0 equ delay__bytes__base+7 delay__197byte1 equ delay__bytes__base+7 delay__239bit0 equ delay__bits__base+0 delay__239bit0__byte equ delay__bits__base+0 delay__239bit0__bit equ 4 delay__243bit0 equ delay__bits__base+0 delay__243bit0__byte equ delay__bits__base+0 delay__243bit0__bit equ 4 ; arguments_none ; uniform_delay delay_instructions ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Delay 1 / 3 of a bit : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__changed equ delay__bytes__base+0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__current equ delay__bytes__base+1 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__previous equ delay__bytes__base+2 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__not_current equ delay__bytes__base+3 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__counter1 equ delay__bytes__base+4 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__counter2 equ delay__bytes__base+5 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__counter3 equ delay__bytes__base+6 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; We need to pulse OUTn low for 56 ms ; read INn ; and restore OUTn high ; Uniform delay remaining = 130 Accumulated Delay = 1 ; for 3 ms . 1 / 3 of a bit time is 1 / < 3 * 2400 > = 138 us . 56 ms / 138 ms = 406 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; ticks . 3 ms / 138 us = 7 . 2 ticks which is rounded up to 8 ticks . Round ; Uniform delay remaining = 130 Accumulated Delay = 1 ; 406 up to 408 so it is divisible by 8 < 408 / 8 = 51 > . ; Uniform delay remaining = 130 Accumulated Delay = 1 ; counter1 := counter1 - 1 decf delay__counter1,f ; Uniform delay remaining = 129 Accumulated Delay = 2 ; if { z } start ; expression=`{ z }' exp_delay=0 true_delay=32 false_delay=37 true_size=109 false_size=41 btfss z__byte,z__bit goto label220__0false label220__0true: ; if { z } body start ; Uniform delay remaining = 129 Accumulated Delay = 0 ; counter1 := 8 movlw 8 movwf delay__counter1 ; Uniform delay remaining = 127 Accumulated Delay = 2 ; counter2 := counter2 + 1 incf delay__counter2,f ; Uniform delay remaining = 126 Accumulated Delay = 3 ; if { counter2 = 1 } start decf delay__counter2,w ; expression=`{ counter2 = 1 }' exp_delay=1 true_delay=25 false_delay=21 true_size=43 false_size=56 btfsc z___byte,z___bit goto label223__0true label223__0false: movlw 51 subwf delay__counter2,w ; expression=`{ counter2 = 51 }' exp_delay=2 true_delay=16 false_delay=12 true_size=30 false_size=18 btfsc z___byte,z___bit goto label232__0true label232__0false: movlw 52 subwf delay__counter2,w ; expression=`{ counter2 = 52 }' exp_delay=2 true_delay=7 false_delay=0 true_size=7 false_size=0 btfsc z___byte,z___bit goto label247__0true label247__0false: ; Delay 6 cycles nop nop nop nop nop nop goto label247__0end label247__0true: ; else_if { counter2 = 52 } body start ; Uniform delay remaining = 126 Accumulated Delay = 0 ; The 3 ms have elpased , next time we trigger again : ; Uniform delay remaining = 126 Accumulated Delay = 0 ; inputs := inputs & 3 movlw 3 andwf inputs,f ; Uniform delay remaining = 124 Accumulated Delay = 2 ; if { ! {{ enable @ 0 }} } start ; Alias variable for select enable @ 0 enable__250select0 equ enable+0 enable__250select0__byte equ enable+0 enable__250select0__bit equ 0 ; expression=`{{ enable @ 0 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 btfss enable__250select0__byte,enable__250select0__bit ; if { ! {{ enable @ 0 }} } body start ; Uniform delay remaining = 124 Accumulated Delay = 0 ; inputs @ 0 := 0 ; Select inputs @ 0 inputs__251select0 equ inputs+0 inputs__251select0__byte equ inputs+0 inputs__251select0__bit equ 0 bcf inputs__251select0__byte,inputs__251select0__bit ; Uniform delay remaining = 123 Accumulated Delay = 1 ; Uniform delay remaining = 123 Accumulated Delay = 1 ; if { ! {{ enable @ 0 }} } body end ; if exp=` enable @ 0 ' true skip delay=2 ; Other expression=`{{ enable @ 0 }}' delay=2 ; if { ! {{ enable @ 0 }} } end ; Uniform delay remaining = 122 Accumulated Delay = 4 ; if { ! {{ enable @ 1 }} } start ; Alias variable for select enable @ 1 enable__253select0 equ enable+0 enable__253select0__byte equ enable+0 enable__253select0__bit equ 1 ; expression=`{{ enable @ 1 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 btfss enable__253select0__byte,enable__253select0__bit ; if { ! {{ enable @ 1 }} } body start ; Uniform delay remaining = 122 Accumulated Delay = 0 ; inputs @ 1 := 0 ; Select inputs @ 1 inputs__254select0 equ inputs+0 inputs__254select0__byte equ inputs+0 inputs__254select0__bit equ 1 bcf inputs__254select0__byte,inputs__254select0__bit ; Uniform delay remaining = 121 Accumulated Delay = 1 ; Uniform delay remaining = 121 Accumulated Delay = 1 ; if { ! {{ enable @ 1 }} } body end ; if exp=` enable @ 1 ' true skip delay=2 ; Other expression=`{{ enable @ 1 }}' delay=2 ; if { ! {{ enable @ 1 }} } end ; Uniform delay remaining = 120 Accumulated Delay = 6 ; counter2 := 0 clrf delay__counter2 ; Uniform delay remaining = 119 Accumulated Delay = 7 ; Uniform delay remaining = 119 Accumulated Delay = 7 ; else_if { counter2 = 52 } body end ; if exp=` counter2 = 52 ' total delay=12 ; if exp=` counter2 = 52 ' generic label247__0end: ; Other expression=`{ counter2 = 52 }' delay=12 ; Delay 3 cycles nop nop nop goto label232__0end label232__0true: ; else_if { counter2 = 51 } body start ; Uniform delay remaining = 126 Accumulated Delay = 0 ; Approximately 56 ms have elpased ; ; Uniform delay remaining = 126 Accumulated Delay = 0 ; Time to read data and reset any triggers : ; Uniform delay remaining = 126 Accumulated Delay = 0 ; Note : the compiler is generating pretty awful code ; Uniform delay remaining = 126 Accumulated Delay = 0 ; for th next couple of statements . It works , but it ; Uniform delay remaining = 126 Accumulated Delay = 0 ; is not pretty . ; Uniform delay remaining = 126 Accumulated Delay = 0 ; if { ! out0 } start ; expression=`out0' exp_delay=0 true_delay=0 false_delay=5 true_size=0 false_size=8 btfss out0__byte,out0__bit goto label238__0false label238__0true: ; Delay 4 cycles nop nop nop nop goto label238__0end label238__0false: ; if { ! out0 } body start ; Uniform delay remaining = 126 Accumulated Delay = 0 ; inputs @ 0 := ! in0 bcf delay__239bit0__byte,delay__239bit0__bit btfss in0__byte,in0__bit bsf delay__239bit0__byte,delay__239bit0__bit ; Select variable inputs @ 0 inputs__239select1 equ inputs+0 inputs__239select1__byte equ inputs+0 inputs__239select1__bit equ 0 btfss delay__239bit0__byte,delay__239bit0__bit bcf inputs__239select1__byte,inputs__239select1__bit btfsc delay__239bit0__byte,delay__239bit0__bit bsf inputs__239select1__byte,inputs__239select1__bit ; Uniform delay remaining = 122 Accumulated Delay = 4 ; out0 := 1 bsf out0__byte,out0__bit ; Uniform delay remaining = 121 Accumulated Delay = 5 ; Uniform delay remaining = 121 Accumulated Delay = 5 ; if { ! out0 } body end ; if exp=`out0' total delay=8 ; if exp=`out0' generic label238__0end: ; Other expression=`out0' delay=8 ; if { ! out0 } end ; Uniform delay remaining = 118 Accumulated Delay = 8 ; if { ! out1 } start ; expression=`out1' exp_delay=0 true_delay=0 false_delay=5 true_size=0 false_size=8 btfss out1__byte,out1__bit goto label242__0false label242__0true: ; Delay 4 cycles nop nop nop nop goto label242__0end label242__0false: ; if { ! out1 } body start ; Uniform delay remaining = 118 Accumulated Delay = 0 ; inputs @ 1 := ! in1 bcf delay__243bit0__byte,delay__243bit0__bit btfss in1__byte,in1__bit bsf delay__243bit0__byte,delay__243bit0__bit ; Select variable inputs @ 1 inputs__243select1 equ inputs+0 inputs__243select1__byte equ inputs+0 inputs__243select1__bit equ 1 btfss delay__243bit0__byte,delay__243bit0__bit bcf inputs__243select1__byte,inputs__243select1__bit btfsc delay__243bit0__byte,delay__243bit0__bit bsf inputs__243select1__byte,inputs__243select1__bit ; Uniform delay remaining = 114 Accumulated Delay = 4 ; out1 := 1 bsf out1__byte,out1__bit ; Uniform delay remaining = 113 Accumulated Delay = 5 ; Uniform delay remaining = 113 Accumulated Delay = 5 ; if { ! out1 } body end ; if exp=`out1' total delay=8 ; if exp=`out1' generic label242__0end: ; Other expression=`out1' delay=8 ; if { ! out1 } end ; Uniform delay remaining = 110 Accumulated Delay = 16 ; Now wait an additional 3 ms before triggering again : ; Uniform delay remaining = 110 Accumulated Delay = 16 ; Uniform delay remaining = 110 Accumulated Delay = 16 ; else_if { counter2 = 51 } body end ; if exp=` counter2 = 51 ' total delay=21 ; if exp=` counter2 = 51 ' generic label232__0end: ; Other expression=`{ counter2 = 51 }' delay=21 ; Delay 3 cycles nop nop nop goto label223__0end label223__0true: ; if { counter2 = 1 } body start ; Uniform delay remaining = 126 Accumulated Delay = 0 ; Trigger the appropriate enabled IROD ' s : ; Uniform delay remaining = 126 Accumulated Delay = 0 ; counter3 := counter3 + 1 incf delay__counter3,f ; Uniform delay remaining = 125 Accumulated Delay = 1 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } start ; Alias variable for select enable @ 0 enable__226select7 equ enable+0 enable__226select7__byte equ enable+0 enable__226select7__bit equ 0 ; expression=`enable @ 0' exp_delay=0 true_delay=9 false_delay=5 true_size=13 false_size=1 btfsc enable__226select7__byte,enable__226select7__bit goto label226__8true label226__8false: ; Delay 5 cycles nop nop nop nop nop goto and226__0false label226__8true: ; expression=`alternate' exp_delay=0 true_delay=5 false_delay=3 true_size=6 false_size=1 btfss alternate__byte,alternate__bit goto label226__6false label226__6true: ; expression=`alternate' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 btfsc alternate__byte,alternate__bit goto label226__5true label226__5false: ; Delay 1 cycles nop goto and226__2false label226__5true: ; Alias variable for select counter3 @ 0 delay__counter3__226select3 equ delay__counter3+0 delay__counter3__226select3__byte equ delay__counter3+0 delay__counter3__226select3__bit equ 0 ; expression=`counter3 @ 0' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc delay__counter3__226select3__byte,delay__counter3__226select3__bit and226__2true: or226__1true: and226__0true: ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; out0 := 0 bcf out0__byte,out0__bit ; Uniform delay remaining = 124 Accumulated Delay = 1 ; Uniform delay remaining = 124 Accumulated Delay = 1 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } body end ; if exp=`counter3 @ 0' false skip delay=2 ; Other expression=`counter3 @ 0' delay=2 ; if exp=`alternate' total delay=5 ; if exp=`alternate' generic label226__5end: ; Other expression=`alternate' delay=5 and226__2false: and226__2end: goto label226__6end label226__6false: ; Delay 3 cycles nop nop nop goto or226__1true ; if exp=`alternate' total delay=9 ; if exp=`alternate' generic label226__6end: ; Other expression=`alternate' delay=9 or226__1false: or226__1end: ; if exp=`enable @ 0' total delay=12 ; if exp=`enable @ 0' generic label226__8end: ; Other expression=`enable @ 0' delay=12 and226__0false: and226__0end: ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } end ; Uniform delay remaining = 113 Accumulated Delay = 13 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } start ; Alias variable for select enable @ 1 enable__229select7 equ enable+0 enable__229select7__byte equ enable+0 enable__229select7__bit equ 1 ; expression=`enable @ 1' exp_delay=0 true_delay=9 false_delay=5 true_size=13 false_size=1 btfsc enable__229select7__byte,enable__229select7__bit goto label229__8true label229__8false: ; Delay 5 cycles nop nop nop nop nop goto and229__0false label229__8true: ; expression=`alternate' exp_delay=0 true_delay=5 false_delay=3 true_size=6 false_size=1 btfss alternate__byte,alternate__bit goto label229__6false label229__6true: ; expression=`alternate' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 btfsc alternate__byte,alternate__bit goto label229__5true label229__5false: ; Delay 1 cycles nop goto and229__2false label229__5true: ; Alias variable for select counter3 @ 0 delay__counter3__229select3 equ delay__counter3+0 delay__counter3__229select3__byte equ delay__counter3+0 delay__counter3__229select3__bit equ 0 ; expression=`{{ counter3 @ 0 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 btfss delay__counter3__229select3__byte,delay__counter3__229select3__bit and229__2true: or229__1true: and229__0true: ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } body start ; Uniform delay remaining = 113 Accumulated Delay = 0 ; out1 := 0 bcf out1__byte,out1__bit ; Uniform delay remaining = 112 Accumulated Delay = 1 ; Uniform delay remaining = 112 Accumulated Delay = 1 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } body end ; if exp=` counter3 @ 0 ' true skip delay=2 ; Other expression=`{{ counter3 @ 0 }}' delay=2 ; if exp=`alternate' total delay=5 ; if exp=`alternate' generic label229__5end: ; Other expression=`alternate' delay=5 and229__2false: and229__2end: goto label229__6end label229__6false: ; Delay 3 cycles nop nop nop goto or229__1true ; if exp=`alternate' total delay=9 ; if exp=`alternate' generic label229__6end: ; Other expression=`alternate' delay=9 or229__1false: or229__1end: ; if exp=`enable @ 1' total delay=12 ; if exp=`enable @ 1' generic label229__8end: ; Other expression=`enable @ 1' delay=12 and229__0false: and229__0end: ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } end ; Uniform delay remaining = 101 Accumulated Delay = 25 ; Uniform delay remaining = 101 Accumulated Delay = 25 ; if { counter2 = 1 } body end ; if exp=` counter2 = 1 ' total delay=29 ; if exp=` counter2 = 1 ' generic label223__0end: ; Other expression=`{ counter2 = 1 }' delay=29 ; if { counter2 = 1 } end ; Uniform delay remaining = 97 Accumulated Delay = 32 ; Uniform delay remaining = 97 Accumulated Delay = 32 ; if { z } body end ; Delay 4 cycles nop nop nop nop goto label220__0end label220__0false: ; else body start ; Uniform delay remaining = 129 Accumulated Delay = 0 ; Compute the interrupts : ; Uniform delay remaining = 129 Accumulated Delay = 0 ; previous := current movf delay__current,w movwf delay__previous ; Uniform delay remaining = 127 Accumulated Delay = 2 ; current := {{ inputs ^ complement }} & 3 movf inputs,w xorwf complement,w andlw 3 movwf delay__current ; Uniform delay remaining = 123 Accumulated Delay = 6 ; not_current := current ^ 3 movlw 3 xorwf delay__current,w movwf delay__not_current ; Uniform delay remaining = 120 Accumulated Delay = 9 ; changed := current ^ previous movf delay__current,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 117 Accumulated Delay = 12 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } start movf low,w andwf delay__not_current,w movwf delay__264byte0 movf high,w andwf delay__current,w iorwf delay__264byte0,f movf delay__changed,w andwf delay__current,w andwf raising,w iorwf delay__264byte0,f movf delay__changed,w andwf delay__previous,w andwf falling,w iorwf delay__264byte0,w ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } body start ; Uniform delay remaining = 117 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 116 Accumulated Delay = 1 ; Uniform delay remaining = 116 Accumulated Delay = 1 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } body end ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 }' delay=16 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } end ; Uniform delay remaining = 101 Accumulated Delay = 28 ; Uniform delay remaining = 101 Accumulated Delay = 28 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 101 Accumulated Delay = 28 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label269__2true label269__2false: ; Delay 2 cycles nop nop goto and269__0false label269__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label269__1false label269__1true: and269__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 101 Accumulated Delay = 0 ; Shove serial out to low : ; Uniform delay remaining = 101 Accumulated Delay = 0 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 100 Accumulated Delay = 1 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 99 Accumulated Delay = 2 ; Uniform delay remaining = 99 Accumulated Delay = 2 ; if { interrupt_pending && interrupt_enable } body end goto label269__1end label269__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label269__1end: ; Other expression=`interrupt_enable' delay=6 ; if exp=`interrupt_pending' total delay=9 ; if exp=`interrupt_pending' generic label269__2end: ; Other expression=`interrupt_pending' delay=9 and269__0false: and269__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 92 Accumulated Delay = 37 ; Uniform delay remaining = 92 Accumulated Delay = 37 ; else body end ; if exp=`z' total delay=40 ; if exp=`z' generic label220__0end: ; Other expression=`{ z }' delay=40 ; if { z } end ; Uniform delay remaining = 89 Accumulated Delay = 42 ; Uniform delay remaining = 89 Accumulated Delay = 42 ; Soak up remaining 89 cycles ; Delay 89 cycles movlw 29 movwf delay__197byte1 delay__197delay0: decfsz delay__197byte1,f goto delay__197delay0 nop ; procedure delay end retlw 0 ; optimize 1 ; comment {The main routine can span the 256 byte boundary at 0x300 :} ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; procedure main start switch__329block_start: addwf pcl___register,f goto switch__329block330 goto switch__329block334 goto switch__329block338 goto switch__329block346 goto switch__329block350 goto switch__329block354 goto switch__329block358 goto switch__329block358 switch__329block_end: ; switch_check 329 switch__329block_start switch__329block_end switch__326block_start: addwf pcl___register,f goto switch__326block327 goto switch__326block364 goto switch__326block367 goto switch__326block367 goto switch__326block372 goto switch__326block372 goto switch__326block377 goto switch__326block377 switch__326block_end: ; switch_check 326 switch__326block_start switch__326block_end switch__406block_start: addwf pcl___register,f goto switch__406block407 goto switch__406block407 goto switch__406block407 goto switch__406block407 goto switch__406block412 goto switch__406block412 goto switch__406block416 goto switch__406block416 switch__406block_end: ; switch_check 406 switch__406block_start switch__406block_end switch__424block_start: addwf pcl___register,f goto switch__424block425 goto switch__424block429 goto switch__424block433 goto switch__424block437 goto switch__424block441 goto switch__424block452 goto switch__424block456 goto switch__424block461 switch__424block_end: ; switch_check 424 switch__424block_start switch__424block_end switch__389block_start: addwf pcl___register,f goto switch__389end goto switch__389end goto switch__389end goto switch__389end goto switch__389end goto switch__389block390 goto switch__389block404 goto switch__389block422 switch__389block_end: ; switch_check 389 switch__389block_start switch__389block_end switch__323block_start: addwf pcl___register,f goto switch__323block324 goto switch__323block384 goto switch__323block384 goto switch__323block387 switch__323block_end: ; switch_check 323 switch__323block_start switch__323block_end main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+5 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+5 main__total__bytes equ 5 main__392byte0 equ main__bytes__base+4 main__374byte0 equ main__bytes__base+4 main__369byte0 equ main__bytes__base+4 main__356byte0 equ main__bytes__base+4 main__352byte0 equ main__bytes__base+4 main__379byte0 equ main__bytes__base+4 main__348byte0 equ main__bytes__base+4 main__326byte0 equ main__bytes__base+4 main__389byte0 equ main__bytes__base+4 main__323byte0 equ main__bytes__base+4 ; arguments_none main__command equ main__bytes__base+0 main__glitch equ main__bytes__base+1 main__id_index equ main__bytes__base+2 main__result equ main__bytes__base+3 ; Let ROOT be http : / / web . gramlich . com / projects / robobricks ; For BIROD2 specific commands see : ; ROOT / birod2 / rev_a / index . html ; For shared commands see : ; ROOT / specifications . html # Software_Protocol ; For shared interrupt commands see : ; ROOT / specifications . html # Interrupts ; Initialize output pins : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; out0 := 1 bsf out0__byte,out0__bit ; out1 := 1 bsf out1__byte,out1__bit ; Initialize everything else : ; interrupt_enable := 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; alternate := 0 bcf alternate__byte,alternate__bit ; enable := 3 movlw 3 movwf enable ; complement := 0 clrf complement ; falling := 0 clrf falling ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; id_index := 0 clrf main__id_index ; Infinite command loop : ; loop_forever ... start main__318loop__forever: ; Wait for command : ; command := get_byte {{ }} ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call get_byte movf get_byte__0return__byte,w movwf main__command ; Dispatch on command : ; switch { command >> 6 } swapf main__command,w movwf main__323byte0 rrf main__323byte0,f rrf main__323byte0,w andlw 3 ; case 0 ; case 1 2 ; case 3 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__323block_start switch__323block324: ; Command = 00 xx xxxx : ; switch { command >> 3 } rrf main__command,w movwf main__326byte0 rrf main__326byte0,f rrf main__326byte0,w andlw 31 ; case 0 ; case 1 ; case 2 3 ; case 4 5 ; case 6 7 goto switch__326block_start switch__326block327: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 7 goto switch__329block_start switch__329block330: ; Read Inputs < Command = 0000 0000 > : ; call send_byte {{ {{ inputs ^ complement }} & 0xf }} movf inputs,w xorwf complement,w andlw 15 movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block334: ; Read Raw < Command = 0000 0001 > : ; call send_byte {{ inputs }} movf inputs,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block338: ; Read Alternate < Command = 0000 0010 > : ; if { alternate } start ; expression=`{ alternate }' exp_delay=0 true_delay=0 false_delay=-1 true_size=2 false_size=1 ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc alternate__byte,alternate__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfsc z___byte,z___bit goto label340__0true label340__0false: ; else body start ; call send_byte {{ 0 }} clrf send_byte__char ; 1 instructions found for sharing goto label340__0end label340__0true: ; if { alternate } body start ; call send_byte {{ 1 }} movlw 1 movwf send_byte__char ; 1 instructions found for sharing ; if exp=`alternate' generic label340__0end: ; Other expression=`{ alternate }' delay=-1 ; 1 shared instructions follow ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { alternate } end ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block346: ; Read Enable Complement Masks < Command = 0000 0011 > : ; call send_byte {{ {{ enable << 2 }} | complement }} rlf enable,w movwf main__348byte0 rlf main__348byte0,w andlw 252 iorwf complement,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block350: ; Read High Low Masks < Command = 0000 0100 > : ; call send_byte {{ {{ high << 2 }} | low }} rlf high,w movwf main__352byte0 rlf main__352byte0,w andlw 252 iorwf low,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block354: ; Read Raising Falling Masks < Command = 0000 0101 > : ; call send_byte {{ {{ raising << 2 }} | falling }} rlf raising,w movwf main__356byte0 rlf main__356byte0,w andlw 252 iorwf falling,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__329end switch__329block358: ; Set alternate bit < Command = 0000 011 a > : ; alternate := command @ 0 ; Alias variable for select command @ 0 main__command__360select0 equ main__command+0 main__command__360select0__byte equ main__command+0 main__command__360select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf alternate__byte,alternate__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__360select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__360select0__byte,main__command__360select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf alternate__byte,alternate__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__329end: goto switch__326end switch__326block364: ; Undefinded command ; do nothing : goto switch__326end switch__326block367: ; Set Enable Complement Masks < Command = 0001 eecc > : ; enable := {{ command >> 2 }} & 3 rrf main__command,w movwf main__369byte0 rrf main__369byte0,w andlw 3 movwf enable ; complement := command & 3 movlw 3 andwf main__command,w movwf complement goto switch__326end switch__326block372: ; Set High Low Masks < Command = 0010 hhll > : ; high := {{ command >> 2 }} & 3 rrf main__command,w movwf main__374byte0 rrf main__374byte0,w andlw 3 movwf high ; low := command & 3 movlw 3 andwf main__command,w movwf low goto switch__326end switch__326block377: ; Set Raising Falling Mask < Command = 0011 rrff > : ; raising := {{ command >> 2 }} & 3 rrf main__command,w movwf main__379byte0 rrf main__379byte0,w andlw 3 movwf raising ; falling := command & 3 movlw 3 andwf main__command,w movwf falling switch__326end: goto switch__323end switch__323block384: ; Do nothing < Command = 01 xx xxxx or 10 xx xxxx > : goto switch__323end switch__323block387: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } rrf main__command,w movwf main__389byte0 rrf main__389byte0,f rrf main__389byte0,w andlw 7 ; case 5 ; case 6 ; case 7 goto switch__389block_start switch__389block390: ; Command = 1110 1 xxx : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__392byte0 movlw 7 subwf main__392byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 btfss z___byte,z___bit goto label392__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits < Command = 1110 1111 > : ; result := 0 clrf main__result ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_enable__byte,interrupt_enable__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label395__0end ; if { interrupt_enable } body start ; result := result | 2 movlw 2 iorwf main__result,f ; if { interrupt_enable } body end label395__0end: ; if exp=`interrupt_enable' empty false ; Other expression=`{ interrupt_enable }' delay=-1 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_pending__byte,interrupt_pending__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label398__0end ; if { interrupt_pending } body start ; result := result | 1 movlw 1 iorwf main__result,f ; if { interrupt_pending } body end label398__0end: ; if exp=`interrupt_pending' empty false ; Other expression=`{ interrupt_pending }' delay=-1 ; if { interrupt_pending } end ; call send_byte {{ result }} movf main__result,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; if { {{ command & 7 }} = 7 } body end ; Switch from code bank 0 to code bank 1 before possible transfer (label) bsf pa0___byte,pa0___bit label392__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__389end switch__389block404: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 goto switch__406block_start switch__406block407: ; Set interrupt enable and pending < Command = 1111 00 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__409select0 equ main__command+0 main__command__409select0__byte equ main__command+0 main__command__409select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__409select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__409select0__byte,main__command__409select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__410select0 equ main__command+0 main__command__410select0__byte equ main__command+0 main__command__410select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__410select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__410select0__byte,main__command__410select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__406end switch__406block412: ; Set Interrupt pending bit only < Command = 1111 010 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__414select0 equ main__command+0 main__command__414select0__byte equ main__command+0 main__command__414select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__414select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__414select0__byte,main__command__414select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__406end switch__406block416: ; Set Interrupt pending bit only < Command = 1111 011 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__418select0 equ main__command+0 main__command__418select0__byte equ main__command+0 main__command__418select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__418select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__418select0__byte,main__command__418select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__406end: goto switch__389end switch__389block422: ; Shared commands . ; switch { command & 7 } movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 goto switch__424block_start switch__424block425: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 252 addwf osccal,f goto switch__424end switch__424block429: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 4 addwf osccal,f goto switch__424end switch__424block433: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__424end switch__424block437: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__424end switch__424block441: ; ID Next < Command = 1111 1100 > : ; if { id_index >= id . size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end ; call send_byte {{ id ~~ {{ id_index }} }} incf main__id_index,w ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call id ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf send_byte__char call send_byte ; id_index := id_index + 1 incf main__id_index,f ; if { id_index >= id . size } start movlw 48 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) bsf pa0___byte,pa0___bit btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end goto switch__424end switch__424block452: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf main__id_index goto switch__424end switch__424block456: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf main__glitch,w movwf send_byte__char ; Switch from code bank 1 to code bank 0 before possible transfer (call) bcf pa0___byte,pa0___bit call send_byte ; glitch := 0 clrf main__glitch ; Switch from code bank 0 to code bank 1 before possible transfer (goto) bsf pa0___byte,pa0___bit goto switch__424end switch__424block461: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf main__glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf main__glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__424end: switch__389end: switch__323end: goto main__318loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 16 bytes of 25 available bytes ; Register bank 1 used 10 bytes of 16 available bytes end