radix dec global__variables__bank0 equ 32 global__variables__bank1 equ 160 global__bit__variables__bank0 equ 73 global__bit__variables__bank1 equ 160 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 rp0___byte equ 3 rp0___bit equ 5 rp1___byte equ 3 rp1___bit equ 6 irp___byte equ 3 irp___bit equ 7 trisa___register equ 0x85 trisb___register equ 0x86 fsr___register equ 4 pclath___register equ 10 org 0 start: nop nop nop goto skip___interrupt interrupt___vector: retfie skip___interrupt: ; Use oscillator calibration stored in high memory call 2047 ; Switch from register bank 0 to register bank 1 (which contains 143) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf 143 ; Initialize A/D system to allow digital I/O movlw 7 movwf 159 ; Switch from register bank 1 to register bank 0 (which contains 31) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf 31 ; Initialize TRIS registers movlw 223 tris 5 clrf pclath___register goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the AnalogIn4 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / analogin4 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12ce674 cp = off pwrte = off wdte = on mclre = off fosc = intrc_no_clock ; 16252=0x3f7c 8199=0x2007 __config 16252 configuration___address equ 8199 ; comment {processor pic12f675 cpd = off cp = off boden = off mclre = off pwrte = off wdte = off fosc = intrc_no_clock} ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {define serial communication control constants} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; constant extra_instructions_per_bit 9 extra_instructions_per_bit equ 9 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit extra_instructions_per_delay equ 3 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay delay_instructions equ 135 ; comment {Oscillator Mask :} osccal equ 143 ; constant osccal_unit 0x10 osccal_unit equ 16 ; comment {Analog to digital conversion result register :} addres equ 30 ; comment {Analog to digital conversion register 0 :} addcon0 equ 31 ; bind adon addcon0 @ 0 adon equ addcon0+0 adon__byte equ addcon0+0 adon__bit equ 0 ; bind go_done addcon0 @ 2 go_done equ addcon0+0 go_done__byte equ addcon0+0 go_done__bit equ 2 ; bind chs0 addcon0 @ 3 chs0 equ addcon0+0 chs0__byte equ addcon0+0 chs0__bit equ 3 ; bind chs1 addcon0 @ 4 chs1 equ addcon0+0 chs1__byte equ addcon0+0 chs1__bit equ 4 ; bind adcs0 addcon0 @ 6 adcs0 equ addcon0+0 adcs0__byte equ addcon0+0 adcs0__bit equ 6 ; bind adcs1 addcon0 @ 7 adcs1 equ addcon0+0 adcs1__byte equ addcon0+0 adcs1__bit equ 7 ; comment {Interrupt Control Register :} intcon equ 11 ; bind gpif intcon @ 0 gpif equ intcon+0 gpif__byte equ intcon+0 gpif__bit equ 0 ; bind intf intcon @ 1 intf equ intcon+0 intf__byte equ intcon+0 intf__bit equ 1 ; bind toif intcon @ 2 toif equ intcon+0 toif__byte equ intcon+0 toif__bit equ 2 ; bind gpie intcon @ 3 gpie equ intcon+0 gpie__byte equ intcon+0 gpie__bit equ 3 ; bind inte intcon @ 4 inte equ intcon+0 inte__byte equ intcon+0 inte__bit equ 4 ; bind toie intcon @ 5 toie equ intcon+0 toie__byte equ intcon+0 toie__bit equ 5 ; bind peie intcon @ 6 peie equ intcon+0 peie__byte equ intcon+0 peie__bit equ 6 ; bind gie intcon @ 7 gie equ intcon+0 gie__byte equ intcon+0 gie__bit equ 7 pir1 equ 12 ; bind adif pir1 @ 6 adif equ pir1+0 adif__byte equ pir1+0 adif__bit equ 6 pie1 equ 140 ; bind adie pie1 @ 6 adie equ pie1+0 adie__byte equ pie1+0 adie__bit equ 6 ; comment {Analog to digital conversion register 1 :} addcon1 equ 159 ; bind pcfg0 addcon1 @ 0 pcfg0 equ addcon1+0 pcfg0__byte equ addcon1+0 pcfg0__bit equ 0 ; bind pcfg1 addcon1 @ 1 pcfg1 equ addcon1+0 pcfg1__byte equ addcon1+0 pcfg1__bit equ 1 ; bind pcfg2 addcon1 @ 2 pcfg2 equ addcon1+0 pcfg2__byte equ addcon1+0 pcfg2__bit equ 2 ; constant ain_bit0 0 ain_bit0 equ 0 ; constant ain_bit1 1 ain_bit1 equ 1 ; constant ain_bit2 2 ain_bit2 equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; constant ain_bit3 4 ain_bit3 equ 4 ; constant serial_out_bit 5 serial_out_bit equ 5 ; constant ain_mask0 {{ 1 << ain_bit0 }} ain_mask0 equ 1 ; constant ain_mask1 {{ 1 << ain_bit1 }} ain_mask1 equ 2 ; constant ain_mask2 {{ 1 << ain_bit2 }} ain_mask2 equ 4 ; constant ain_mask3 {{ 1 << ain_bit3 }} ain_mask3 equ 16 ; constant serial_in_mask {{ 1 << serial_in_bit }} serial_in_mask equ 8 ; constant serial_out_mask {{ 1 << serial_out_bit }} serial_out_mask equ 32 ; constant io_mask 0xf io_mask equ 15 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} ain_mask equ 23 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} serial_mask equ 40 ; comment {define port bit assignments} porta equ 5 ain0__byte equ 5 ain0__bit equ 0 ain1__byte equ 5 ain1__bit equ 1 ain2__byte equ 5 ain2__bit equ 2 ain3__byte equ 5 ain3__bit equ 4 serial_in__byte equ 5 serial_in__bit equ 3 serial_out__byte equ 5 serial_out__bit equ 5 ; constant analogs_size 4 analogs_size equ 4 ; string_constants Start string___fetch: movwf pcl___register ; id = 1 , 0 , 12 , 4 , 0 , 0 , 0 , 0 , 0r'16' , 10 , 0s'AnalogIn4D' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 51 retlw 51 ; 1 retlw 1 ; 0 retlw 0 ; 12 retlw 12 ; 4 retlw 4 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 149 ; random number retlw 181 ; random number retlw 5 ; random number retlw 1 ; random number retlw 255 ; random number retlw 9 ; random number retlw 128 ; random number retlw 152 ; random number retlw 45 ; random number retlw 171 ; random number retlw 35 ; random number retlw 147 ; random number retlw 149 ; random number retlw 47 ; random number retlw 27 ; random number retlw 157 ; random number ; 10 retlw 10 ; `AnalogIn4D' retlw 65 retlw 110 retlw 97 retlw 108 retlw 111 retlw 103 retlw 73 retlw 110 retlw 52 retlw 68 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; bank 0 ; Default register bank is now 0 analogs equ global__variables__bank0+0 thresholds_low equ global__variables__bank0+4 thresholds_high equ global__variables__bank0+8 inputs equ global__variables__bank0+12 complement equ global__variables__bank0+13 glitch equ global__variables__bank0+14 id_index equ global__variables__bank0+15 vref_mode equ global__bit__variables__bank0+0 vref_mode__byte equ global__bit__variables__bank0+0 vref_mode__bit equ 0 ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 1 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 2 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 3 falling equ global__variables__bank0+16 high equ global__variables__bank0+17 low equ global__variables__bank0+18 raising equ global__variables__bank0+19 ; procedure main start main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 main__variables__base equ global__variables__bank0+20 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+4 main__total__bytes equ 5 main__287byte0 equ main__bytes__base+3 main__230byte0 equ main__bytes__base+3 main__294byte0 equ main__bytes__base+3 main__245byte0 equ main__bytes__base+3 main__241byte0 equ main__bytes__base+3 main__159byte0 equ main__bytes__base+3 main__156byte0 equ main__bytes__base+3 ; arguments_none main__bit equ main__bytes__base+0 main__command equ main__bytes__base+1 main__temporary equ main__bytes__base+2 ; Initialize the A / D module : ; Select all 4 inputs as A / D : ; addcon1 := 0 ; Switch from register bank 0 to register bank 1 (which contains addcon1) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf addcon1 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : ; addcon0 := 0x41 movlw 65 ; Switch from register bank 1 to register bank 0 (which contains addcon0) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf addcon0 ; adif := 0 bcf adif__byte,adif__bit ; adie := 0 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf adie__byte,adie__bit ; gie := 0 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf gie__byte,gie__bit ; call reset {{ }} call reset ; Set the direction : ; loop_forever ... start main__151loop__forever: ; Wait for a command : ; command := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__command ; Dispatch on command : ; switch { command >> 6 } movlw HIGH switch__156block_start movwf pclath___register swapf main__command,w movwf main__156byte0 rrf main__156byte0,f rrf main__156byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__156block_start: addwf pcl___register,f goto switch__156block157 goto switch__156block258 goto switch__156block282 goto switch__156block285 switch__156block_end: ; switch_check 156 switch__156block_start switch__156block_end switch__156block157: ; Command = 00 xx xxxx : ; switch { command >> 3 } movlw HIGH switch__159block_start movwf pclath___register rrf main__command,w movwf main__159byte0 rrf main__159byte0,f rrf main__159byte0,w andlw 31 ; case 0 ; case 1 ; case 2 3 ; case 4 5 switch__159block_start: addwf pcl___register,f goto switch__159block160 goto switch__159block184 goto switch__159block227 goto switch__159block227 goto switch__159block249 goto switch__159block249 goto switch__159default253 goto switch__159default253 switch__159block_end: ; switch_check 159 switch__159block_start switch__159block_end switch__159block160: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw HIGH switch__162block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 ; case 5 ; case 6 switch__162block_start: addwf pcl___register,f goto switch__162block163 goto switch__162block163 goto switch__162block163 goto switch__162block163 goto switch__162block167 goto switch__162block171 goto switch__162block175 goto switch__162default179 switch__162block_end: ; switch_check 162 switch__162block_start switch__162block_end switch__162block163: ; Read Pin < Command = 0000 00 bb > : ; call send_byte {{ analogs ~~ {{ command }} }} movlw LOW analogs addwf main__command,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__162end switch__162block167: ; Read Binary Values < Command = 0000 0100 > : ; call send_byte {{ inputs ^ complement }} movf inputs,w xorwf complement,w movwf send_byte__char call send_byte goto switch__162end switch__162block171: ; Read Raw Binary < Command = 0000 0101 > : ; call send_byte {{ inputs }} movf inputs,w movwf send_byte__char call send_byte goto switch__162end switch__162block175: ; Reset < Command = 0000 0110 > : ; call reset {{ }} call reset goto switch__162end switch__162default179: ; Undefined command : switch__162end: goto switch__159end switch__159block184: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw HIGH switch__186block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 7 switch__186block_start: addwf pcl___register,f goto switch__186block187 goto switch__186block191 goto switch__186block195 goto switch__186block199 goto switch__186block203 goto switch__186block207 goto switch__186block215 goto switch__186block215 switch__186block_end: ; switch_check 186 switch__186block_start switch__186block_end switch__186block187: ; Read Complement Mask < Command = 0000 1000 > : ; call send_byte {{ complement }} movf complement,w movwf send_byte__char call send_byte goto switch__186end switch__186block191: ; Read High Mask < Command = 0000 1001 > : ; call send_byte {{ high }} movf high,w movwf send_byte__char call send_byte goto switch__186end switch__186block195: ; Read Low Mask < Command = 0000 1010 > : ; call send_byte {{ low }} movf low,w movwf send_byte__char call send_byte goto switch__186end switch__186block199: ; Read Raising Mask < Command = 0000 1011 > : ; call send_byte {{ raising }} movf raising,w movwf send_byte__char call send_byte goto switch__186end switch__186block203: ; Read Falling Mask < Command = 0000 1100 > : ; call send_byte {{ falling }} movf falling,w movwf send_byte__char call send_byte goto switch__186end switch__186block207: ; Read Vref Mode < Command = 0000 1101 > : ; temporary := 0 clrf main__temporary ; if { vref_mode } start ; expression=`{ vref_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc vref_mode__byte,vref_mode__bit ; if { vref_mode } body start ; temporary @ 0 := 1 ; Select temporary @ 0 main__temporary__211select0 equ main__temporary+0 main__temporary__211select0__byte equ main__temporary+0 main__temporary__211select0__bit equ 0 bsf main__temporary__211select0__byte,main__temporary__211select0__bit ; if { vref_mode } body end ; if exp=`vref_mode' false skip delay=2 ; Other expression=`{ vref_mode }' delay=2 ; if { vref_mode } end ; call send_byte {{ temporary }} movf main__temporary,w movwf send_byte__char call send_byte goto switch__186end switch__186block215: ; Set Vref Mode < Command = 0000 111 v > : ; temporary := 0 clrf main__temporary ; vref_mode := 0 bcf vref_mode__byte,vref_mode__bit ; if { command @ 0 } start ; Alias variable for select command @ 0 main__command__219select0 equ main__command+0 main__command__219select0__byte equ main__command+0 main__command__219select0__bit equ 0 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=0 true_size=3 false_size=0 btfss main__command__219select0__byte,main__command__219select0__bit goto label219__1end ; if { command @ 0 } body start ; vref_mode := 1 bsf vref_mode__byte,vref_mode__bit ; temporary := 1 movlw 1 movwf main__temporary ; if { command @ 0 } body end label219__1end: ; if exp=` command @ 0 ' empty false ; Other expression=`{ command @ 0 }' delay=-1 ; if { command @ 0 } end ; addcon1 := temporary movf main__temporary,w ; Switch from register bank 0 to register bank 1 (which contains addcon1) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf addcon1 ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 switch__186end: goto switch__159end switch__159block227: ; Command = 0001 xxxx : ; bit := command & 3 movlw 3 andwf main__command,w movwf main__bit ; switch { {{ command >> 2 }} & 3 } movlw HIGH switch__230block_start movwf pclath___register rrf main__command,w movwf main__230byte0 rrf main__230byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__230block_start: addwf pcl___register,f goto switch__230block231 goto switch__230block235 goto switch__230block239 goto switch__230block243 switch__230block_end: ; switch_check 230 switch__230block_start switch__230block_end switch__230block231: ; Read High Threshold < Command = 0001 00 bb > : ; call send_byte {{ thresholds_high ~~ {{ bit }} }} movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__230end switch__230block235: ; Read Low Threshold < Command = 0001 01 bb > : ; call send_byte {{ thresholds_low ~~ {{ bit }} }} movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__230end switch__230block239: ; Set High Threshold < Command = 0001 10 bb > : ; thresholds_high ~~ {{ bit }} := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__241byte0 movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf main__241byte0,w movwf indf___register goto switch__230end switch__230block243: ; Set Low Threshold < Command = 0001 11 bb > : ; thresholds_low ~~ {{ bit }} := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__245byte0 movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf main__245byte0,w movwf indf___register switch__230end: goto switch__159end switch__159block249: ; Set Complement Mask < Command = 0010 cccc > : ; complement := command & io_mask movlw 15 andwf main__command,w movwf complement goto switch__159end switch__159default253: ; Do nothing : switch__159end: goto switch__156end switch__156block258: ; Command = 01 xx xxxx : ; temporary := command & io_mask movlw 15 andwf main__command,w movwf main__temporary ; Kludge : to get switch so it does not span 256 byte boundary : ; nop 3 ; Delay 3 cycles nop nop nop ; switch { {{ command >> 4 }} & 3 } movlw HIGH switch__263block_start movwf pclath___register swapf main__command,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__263block_start: addwf pcl___register,f goto switch__263block264 goto switch__263block268 goto switch__263block272 goto switch__263block276 switch__263block_end: ; switch_check 263 switch__263block_start switch__263block_end switch__263block264: ; Set High Mask < Command = 0100 hhhh > : ; high := temporary movf main__temporary,w movwf high goto switch__263end switch__263block268: ; Set Low Mask < Command = 0101 llll > : ; low := temporary movf main__temporary,w movwf low goto switch__263end switch__263block272: ; Set Raising Mask < Command = 0110 rrrr > : ; raising := temporary movf main__temporary,w movwf raising goto switch__263end switch__263block276: ; Set Falling Mask < Command = 0111 ffff > : ; falling := temporary movf main__temporary,w movwf falling switch__263end: goto switch__156end switch__156block282: ; Do nothing < Command = 10 xx xxxx > : goto switch__156end switch__156block285: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } movlw HIGH switch__287block_start movwf pclath___register rrf main__command,w movwf main__287byte0 rrf main__287byte0,f rrf main__287byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 switch__287block_start: addwf pcl___register,f goto switch__287block288 goto switch__287block288 goto switch__287block288 goto switch__287block288 goto switch__287block288 goto switch__287block292 goto switch__287block306 goto switch__287block324 switch__287block_end: ; switch_check 287 switch__287block_start switch__287block_end switch__287block288: ; Command = 1100 xxxx or 1110 0 xxx : ; Do nothing : goto switch__287end switch__287block292: ; Read Interrupt Bits < Command = 1110 1111 > : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__294byte0 movlw 7 subwf main__294byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 btfss z___byte,z___bit goto label294__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits : ; temporary := 0 clrf main__temporary ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_enable__byte,interrupt_enable__bit ; if { interrupt_enable } body start ; temporary @ 1 := 1 ; Select temporary @ 1 main__temporary__298select0 equ main__temporary+0 main__temporary__298select0__byte equ main__temporary+0 main__temporary__298select0__bit equ 1 bsf main__temporary__298select0__byte,main__temporary__298select0__bit ; if { interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`{ interrupt_enable }' delay=2 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_pending__byte,interrupt_pending__bit ; if { interrupt_pending } body start ; temporary @ 0 := 1 ; Select temporary @ 0 main__temporary__301select0 equ main__temporary+0 main__temporary__301select0__byte equ main__temporary+0 main__temporary__301select0__bit equ 0 bsf main__temporary__301select0__byte,main__temporary__301select0__bit ; if { interrupt_pending } body end ; if exp=`interrupt_pending' false skip delay=2 ; Other expression=`{ interrupt_pending }' delay=2 ; if { interrupt_pending } end ; call send_byte {{ temporary }} movf main__temporary,w movwf send_byte__char call send_byte ; if { {{ command & 7 }} = 7 } body end label294__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__287end switch__287block306: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw HIGH switch__308block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 switch__308block_start: addwf pcl___register,f goto switch__308block309 goto switch__308block309 goto switch__308block309 goto switch__308block309 goto switch__308block314 goto switch__308block314 goto switch__308block318 goto switch__308block318 switch__308block_end: ; switch_check 308 switch__308block_start switch__308block_end switch__308block309: ; Set interrupt bits < Command = 1111 10 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__311select0 equ main__command+0 main__command__311select0__byte equ main__command+0 main__command__311select0__bit equ 1 bcf interrupt_enable__byte,interrupt_enable__bit btfsc main__command__311select0__byte,main__command__311select0__bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__312select0 equ main__command+0 main__command__312select0__byte equ main__command+0 main__command__312select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc main__command__312select0__byte,main__command__312select0__bit bsf interrupt_pending__byte,interrupt_pending__bit goto switch__308end switch__308block314: ; Set Interrupt Pending < Command = 1111 110 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__316select0 equ main__command+0 main__command__316select0__byte equ main__command+0 main__command__316select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc main__command__316select0__byte,main__command__316select0__bit bsf interrupt_pending__byte,interrupt_pending__bit goto switch__308end switch__308block318: ; Set Interrupt Enable < Command = 1110 111 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__320select0 equ main__command+0 main__command__320select0__byte equ main__command+0 main__command__320select0__bit equ 0 bcf interrupt_enable__byte,interrupt_enable__bit btfsc main__command__320select0__byte,main__command__320select0__bit bsf interrupt_enable__byte,interrupt_enable__bit switch__308end: goto switch__287end switch__287block324: ; Shared commands < Command = 1111 1 xxx > : ; switch { command & 7 } movlw HIGH switch__326block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 switch__326block_start: addwf pcl___register,f goto switch__326block327 goto switch__326block331 goto switch__326block335 goto switch__326block339 goto switch__326block343 goto switch__326block351 goto switch__326block355 goto switch__326block360 switch__326block_end: ; switch_check 326 switch__326block_start switch__326block_end switch__326block327: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 240 ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 addwf osccal,f ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 goto switch__326end switch__326block331: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 16 ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 addwf osccal,f ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 goto switch__326end switch__326block335: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf osccal,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte goto switch__326end switch__326block339: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char call send_byte goto switch__326end switch__326block343: ; ID Next < Command = 1111 1100 > : ; call send_byte {{ id ~~ {{ id_index }} }} incf id_index,w clrf pclath___register call id movwf send_byte__char call send_byte ; id_index := id_index + 1 incf id_index,f ; if { id_index >= id . size } start movlw 51 subwf id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end goto switch__326end switch__326block351: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf id_index goto switch__326end switch__326block355: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf glitch,w movwf send_byte__char call send_byte ; glitch := 0 clrf glitch goto switch__326end switch__326block360: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__326end: switch__287end: switch__156end: goto main__151loop__forever ; loop_forever ... end ; procedure main end ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 delay__variables__base equ global__variables__bank0+25 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+9 delay__total__bytes equ 9 delay__374byte1 equ delay__bytes__base+8 delay__438byte0 equ delay__bytes__base+8 delay__407byte0 equ delay__bytes__base+8 delay__398byte0 equ delay__bytes__base+8 delay__396byte3 equ delay__bytes__base+8 delay__436byte1 equ delay__bytes__base+8 ; arguments_none ; uniform_delay delay_instructions ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; This procedure will delay for one third of a bit time . ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__channel equ delay__bytes__base+0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__current equ delay__bytes__base+1 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__changed equ delay__bytes__base+2 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__previous equ delay__bytes__base+3 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__not_current equ delay__bytes__base+4 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__counter equ delay__bytes__base+5 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__mask equ delay__bytes__base+6 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__result equ delay__bytes__base+7 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; channel := {{ counter >> 1 }} & 3 bcf c___byte,c___bit rrf delay__counter,w andlw 3 movwf delay__channel ; Uniform delay remaining = 126 Accumulated Delay = 5 ; counter := counter + 1 incf delay__counter,f ; Uniform delay remaining = 125 Accumulated Delay = 6 ; if { counter @ 0 } start ; Alias variable for select counter @ 0 delay__counter__396select0 equ delay__counter+0 delay__counter__396select0__byte equ delay__counter+0 delay__counter__396select0__bit equ 0 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=44 false_delay=104 true_size=48 false_size=57 btfss delay__counter__396select0__byte,delay__counter__396select0__bit goto label396__1false label396__1true: ; if { counter @ 0 } body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Set up and wait for acquistion : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 rlf delay__channel,w movwf delay__398byte0 rlf delay__398byte0,f rlf delay__398byte0,w andlw 248 andlw 24 iorlw 65 movwf addcon0 ; Uniform delay remaining = 117 Accumulated Delay = 8 ; Setup for interrupts : ; Uniform delay remaining = 117 Accumulated Delay = 8 ; previous := current movf delay__current,w movwf delay__previous ; Uniform delay remaining = 115 Accumulated Delay = 10 ; Read the I / O port once : ; Uniform delay remaining = 115 Accumulated Delay = 10 ; current := inputs ^ complement movf inputs,w xorwf complement,w movwf delay__current ; Uniform delay remaining = 112 Accumulated Delay = 13 ; not_current := current ^ 0xf movlw 15 xorwf delay__current,w movwf delay__not_current ; Uniform delay remaining = 109 Accumulated Delay = 16 ; changed := current ^ previous movf delay__current,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 106 Accumulated Delay = 19 ; Uniform delay remaining = 106 Accumulated Delay = 19 ; See about triggering the interrupt_pending flag : ; Uniform delay remaining = 106 Accumulated Delay = 19 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start movf low,w andwf delay__not_current,w movwf delay__407byte0 movf high,w andwf delay__current,w iorwf delay__407byte0,f movf delay__changed,w andwf delay__current,w andwf raising,w iorwf delay__407byte0,f movf delay__changed,w andwf delay__not_current,w andwf falling,w iorwf delay__407byte0,w ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start ; Uniform delay remaining = 106 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 105 Accumulated Delay = 1 ; Uniform delay remaining = 105 Accumulated Delay = 1 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end ; Uniform delay remaining = 90 Accumulated Delay = 35 ; Uniform delay remaining = 90 Accumulated Delay = 35 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 90 Accumulated Delay = 35 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label412__2true label412__2false: ; Delay 2 cycles nop nop goto and412__0false label412__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label412__1false label412__1true: and412__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 90 Accumulated Delay = 0 ; Shove serial out to low : ; Uniform delay remaining = 90 Accumulated Delay = 0 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 89 Accumulated Delay = 1 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 88 Accumulated Delay = 2 ; Uniform delay remaining = 88 Accumulated Delay = 2 ; if { interrupt_pending && interrupt_enable } body end goto label412__1end label412__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label412__1end: ; Other expression=`interrupt_enable' delay=6 ; if exp=`interrupt_pending' total delay=9 ; if exp=`interrupt_pending' generic label412__2end: ; Other expression=`interrupt_pending' delay=9 and412__0false: and412__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 81 Accumulated Delay = 44 ; Uniform delay remaining = 81 Accumulated Delay = 44 ; if { counter @ 0 } body end ; Delay 59 cycles movlw 19 movwf delay__396byte3 delay__396delay2: decfsz delay__396byte3,f goto delay__396delay2 nop goto label396__1end label396__1false: ; else body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Start the conversion : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; go_done := 1 bsf go_done__byte,go_done__bit ; Uniform delay remaining = 124 Accumulated Delay = 1 ; mask := 0 clrf delay__mask ; Uniform delay remaining = 123 Accumulated Delay = 2 ; if { channel @ 1 } start ; Alias variable for select channel @ 1 delay__channel__421select0 equ delay__channel+0 delay__channel__421select0__byte equ delay__channel+0 delay__channel__421select0__bit equ 1 ; expression=`{ channel @ 1 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 btfss delay__channel__421select0__byte,delay__channel__421select0__bit goto label421__1false label421__1true: ; if { channel @ 1 } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; if { channel @ 0 } start ; Alias variable for select channel @ 0 delay__channel__422select0 equ delay__channel+0 delay__channel__422select0__byte equ delay__channel+0 delay__channel__422select0__bit equ 0 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 btfsc delay__channel__422select0__byte,delay__channel__422select0__bit ; if { channel @ 0 } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 3 := 1 ; Select mask @ 3 delay__mask__423select0 equ delay__mask+0 delay__mask__423select0__byte equ delay__mask+0 delay__mask__423select0__bit equ 3 bsf delay__mask__423select0__byte,delay__mask__423select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { channel @ 0 } body end btfss delay__channel__422select0__byte,delay__channel__422select0__bit ; else body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 2 := 1 ; Select mask @ 2 delay__mask__425select0 equ delay__mask+0 delay__mask__425select0__byte equ delay__mask+0 delay__mask__425select0__bit equ 2 bsf delay__mask__425select0__byte,delay__mask__425select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; else body end ; if exp=` channel @ 0 ' single true and false skip delay=4 ; Other expression=`{ channel @ 0 }' delay=4 ; if { channel @ 0 } end ; Uniform delay remaining = 119 Accumulated Delay = 4 ; Uniform delay remaining = 119 Accumulated Delay = 4 ; if { channel @ 1 } body end goto label421__1end label421__1false: ; else body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; if { channel @ 0 } start ; Alias variable for select channel @ 0 delay__channel__428select0 equ delay__channel+0 delay__channel__428select0__byte equ delay__channel+0 delay__channel__428select0__bit equ 0 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 btfsc delay__channel__428select0__byte,delay__channel__428select0__bit ; if { channel @ 0 } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 1 := 1 ; Select mask @ 1 delay__mask__429select0 equ delay__mask+0 delay__mask__429select0__byte equ delay__mask+0 delay__mask__429select0__bit equ 1 bsf delay__mask__429select0__byte,delay__mask__429select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { channel @ 0 } body end btfss delay__channel__428select0__byte,delay__channel__428select0__bit ; else body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 0 := 1 ; Select mask @ 0 delay__mask__431select0 equ delay__mask+0 delay__mask__431select0__byte equ delay__mask+0 delay__mask__431select0__bit equ 0 bsf delay__mask__431select0__byte,delay__mask__431select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; else body end ; if exp=` channel @ 0 ' single true and false skip delay=4 ; Other expression=`{ channel @ 0 }' delay=4 ; if { channel @ 0 } end ; Uniform delay remaining = 119 Accumulated Delay = 4 ; Uniform delay remaining = 119 Accumulated Delay = 4 ; else body end ; Delay 1 cycles nop ; if exp=` channel @ 1 ' total delay=8 ; if exp=` channel @ 1 ' generic label421__1end: ; Other expression=`{ channel @ 1 }' delay=8 ; if { channel @ 1 } end ; Uniform delay remaining = 115 Accumulated Delay = 10 ; Delaying 60 uS is way longer than necessary for the conversion ; Uniform delay remaining = 115 Accumulated Delay = 10 ; to complete . ; Uniform delay remaining = 115 Accumulated Delay = 10 ; nop 60 ; Delay 60 cycles movlw 19 movwf delay__436byte1 delay__436delay0: decfsz delay__436byte1,f goto delay__436delay0 nop nop ; Uniform delay remaining = 55 Accumulated Delay = 70 ; result := addres movf addres,w movwf delay__result ; Uniform delay remaining = 53 Accumulated Delay = 72 ; analogs ~~ {{ channel }} := result movf delay__result,w movwf delay__438byte0 movlw LOW analogs addwf delay__channel,w movwf fsr___register movf delay__438byte0,w movwf indf___register ; Uniform delay remaining = 46 Accumulated Delay = 79 ; if { result <= thresholds_low ~~ {{ channel }} } start movlw LOW thresholds_low addwf delay__channel,w movwf fsr___register movf indf___register,w subwf delay__result,w btfsc z___byte,z___bit bcf c___byte,c___bit ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 btfss c___byte,c___bit goto label439__0true label439__0false: ; Delay 2 cycles nop nop goto label439__0end label439__0true: ; if { result <= thresholds_low ~~ {{ channel }} } body start ; Uniform delay remaining = 46 Accumulated Delay = 0 ; inputs := inputs & {{ mask ^ io_mask }} movlw 15 xorwf delay__mask,w andwf inputs,f ; Uniform delay remaining = 43 Accumulated Delay = 3 ; Uniform delay remaining = 43 Accumulated Delay = 3 ; if { result <= thresholds_low ~~ {{ channel }} } body end ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic label439__0end: ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 ; if { result <= thresholds_low ~~ {{ channel }} } end ; Uniform delay remaining = 33 Accumulated Delay = 92 ; if { result >= thresholds_high ~~ {{ channel }} } start movlw LOW thresholds_high addwf delay__channel,w movwf fsr___register movf indf___register,w subwf delay__result,w ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc c___byte,c___bit goto label442__0true label442__0false: ; Delay 1 cycles nop goto label442__0end label442__0true: ; if { result >= thresholds_high ~~ {{ channel }} } body start ; Uniform delay remaining = 33 Accumulated Delay = 0 ; inputs := inputs | mask movf delay__mask,w iorwf inputs,f ; Uniform delay remaining = 31 Accumulated Delay = 2 ; Uniform delay remaining = 31 Accumulated Delay = 2 ; if { result >= thresholds_high ~~ {{ channel }} } body end ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic label442__0end: ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 ; if { result >= thresholds_high ~~ {{ channel }} } end ; Uniform delay remaining = 23 Accumulated Delay = 102 ; inputs := inputs & io_mask movlw 15 andwf inputs,f ; Uniform delay remaining = 21 Accumulated Delay = 104 ; Uniform delay remaining = 21 Accumulated Delay = 104 ; else body end ; if exp=` counter @ 0 ' total delay=107 ; if exp=` counter @ 0 ' generic label396__1end: ; Other expression=`{ counter @ 0 }' delay=107 ; if { counter @ 0 } end ; Uniform delay remaining = 18 Accumulated Delay = 113 ; Uniform delay remaining = 18 Accumulated Delay = 113 ; Soak up remaining 18 cycles ; Delay 18 cycles movlw 5 movwf delay__374byte1 delay__374delay0: decfsz delay__374byte1,f goto delay__374delay0 nop nop ; procedure delay end retlw 0 ; optimize 1 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 get_byte__variables__base equ global__variables__bank0+34 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__465while__continue: ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__465while__break ; call delay {{ }} call delay goto get_byte__465while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__465while__break: ; `while serial_in ...' end ; Clear interrupts and interrupt pending : ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; 1 cycle : ; char := 0 clrf get_byte__char ; 2 cycles to set up loop : ; 1 + 1 + 2 = 4 ; nop extra_instructions_per_bit - 4 ; Delay 5 cycles nop nop nop nop nop ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__484_loop: ; call delay {{ }} call delay ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; 2 cycles : ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__490select0 equ get_byte__char+0 get_byte__char__490select0__byte equ get_byte__char+0 get_byte__char__490select0__bit equ 7 bsf get_byte__char__490select0__byte,get_byte__char__490select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 2 + 2 + 3 = 7 ; nop extra_instructions_per_bit - 7 ; Delay 2 cycles nop nop decfsz get_byte__count,f goto get_byte__484_loop get_byte__484_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 send_byte__variables__base equ global__variables__bank0+37 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label521__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label521__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; 1 cycle : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for loop setup : ; 1 + 2 = 3 ; nop extra_instructions_per_bit - 3 ; Delay 6 cycles nop nop nop nop nop nop ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf send_byte__count send_byte__538_loop: ; 4 cycles : ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__540select0 equ send_byte__char+0 send_byte__char__540select0__byte equ send_byte__char+0 send_byte__char__540select0__bit equ 0 btfss send_byte__char__540select0__byte,send_byte__char__540select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__540select0__byte,send_byte__char__540select0__bit bsf serial_out__byte,serial_out__bit ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 4 + 2 + 3 = 9 = no NOP ' s needed : decfsz send_byte__count,f goto send_byte__538_loop send_byte__538_done: ; `count_down count 8 ...' end ; Send the stop bit : ; 1 cycle to close out previous loop : ; nop 1 ; Delay 1 cycles nop ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for call / return : ; 2 cycles for argument : ; 1 + 2 + 2 = 5 ; nop extra_instructions_per_bit - 5 ; Delay 4 cycles nop nop nop nop ; procedure send_byte end retlw 0 ; procedure reset start reset: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 reset__variables__base equ global__variables__bank0+39 reset__bytes__base equ reset__variables__base+0 reset__bits__base equ reset__variables__base+2 reset__total__bytes equ 2 reset__582byte0 equ reset__bytes__base+1 reset__583byte0 equ reset__bytes__base+1 ; arguments_none ; This procedure will initialize all of the registers : reset__index equ reset__bytes__base+0 ; inputs := 0 clrf inputs ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; falling := 0 clrf falling ; complement := 0 clrf complement ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; index := 0 clrf reset__index ; `while index < 4 ...' start reset__581while__continue: movlw 4 subwf reset__index,w ; expression=` index < 4 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 btfsc c___byte,c___bit goto reset__581while__break ; thresholds_high ~~ {{ index }} := 0xc0 movlw 192 movwf reset__582byte0 movlw LOW thresholds_high addwf reset__index,w movwf fsr___register movf reset__582byte0,w movwf indf___register ; thresholds_low ~~ {{ index }} := 0x40 movlw 64 movwf reset__583byte0 movlw LOW thresholds_low addwf reset__index,w movwf fsr___register movf reset__583byte0,w movwf indf___register ; index := index + 1 incf reset__index,f goto reset__581while__continue ; if exp=` index < 4 ' false goto ; Other expression=` index < 4 ' delay=-1 reset__581while__break: ; `while index < 4 ...' end ; glitch := 0 clrf glitch ; id_index := 0 clrf id_index ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; vref_mode := 0 bcf vref_mode__byte,vref_mode__bit ; addcon1 := 0 ; Switch from register bank 0 to register bank 1 (which contains addcon1) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf addcon1 ; procedure reset end ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 retlw 0 ; Register bank 0 used 41 bytes of 96 available bytes ; Register bank 1 used 0 bytes of 32 available bytes end