1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0049 global__bit__variables__bank0 equ 73 5 00a0 global__bit__variables__bank1 equ 160 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 0003 rp0___byte equ 3 13 0005 rp0___bit equ 5 14 0003 rp1___byte equ 3 15 0006 rp1___bit equ 6 16 0003 irp___byte equ 3 17 0007 irp___bit equ 7 18 0085 trisa___register equ 0x85 19 0086 trisb___register equ 0x86 20 0004 fsr___register equ 4 21 000a pclath___register equ 10 22 org 0 23 start: 24 000 0000 nop 25 001 0000 nop 26 002 0000 nop 27 003 2805 goto skip___interrupt 28 interrupt___vector: 29 004 0009 retfie 30 skip___interrupt: 31 ; Use oscillator calibration stored in high memory 32 005 27ff call 2047 33 ; Switch from register bank 0 to register bank 1 (which contains 143) 34 006 1683 bsf rp0___byte,rp0___bit 35 ; Register bank is now 1 36 007 008f movwf 143 37 ; Initialize A/D system to allow digital I/O 38 008 3007 movlw 7 39 009 009f movwf 159 40 ; Switch from register bank 1 to register bank 0 (which contains 31) 41 00a 1283 bcf rp0___byte,rp0___bit 42 ; Register bank is now 0 43 00b 019f clrf 31 44 ; Initialize TRIS registers 45 00c 30df movlw 223 46 00d 0065 tris 5 47 00e 018a clrf pclath___register 48 00f 2846 goto main 49 ; comment ############################################################################# 50 ; comment {} 51 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 52 ; comment {All rights reserved .} 53 ; comment {} 54 ; comment {Permission to use , copy , modify , distribute , and sell this software} 55 ; comment {for any purpose is hereby granted without fee provided that the above} 56 ; comment {copyright notice and this permission are retained . The author makes} 57 ; comment {no representations about the suitability of this software for any purpose .} 58 ; comment {It is provided { as is } without express or implied warranty .} 59 ; comment {} 60 ; comment {This is the code that implements the AnalogIn4 RoboBrick . Basically} 61 ; comment {it just waits for commands that come in at 2400 baud and responds} 62 ; comment {to them . See} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / robobricks / analogin4 / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment ############################################################################# 69 ; processor pic12ce674 cp = off pwrte = off wdte = on mclre = off fosc = intrc_no_clock 70 ; 16252=0x3f7c 8199=0x2007 71 __config 16252 72 2007 configuration___address equ 8199 73 ; comment {processor pic12f675 cpd = off cp = off boden = off mclre = off pwrte = off wdte = off fosc = intrc_no_clock} 74 ; comment {define processor constants} 75 ; constant clock_rate 4000000 76 3d0900 clock_rate equ 4000000 77 ; constant clocks_per_instruction 4 78 0004 clocks_per_instruction equ 4 79 ; constant instruction_rate clock_rate / clocks_per_instruction 80 f4240 instruction_rate equ 1000000 81 ; comment {define serial communication control constants} 82 ; constant baud_rate 2400 83 0960 baud_rate equ 2400 84 ; constant instructions_per_bit instruction_rate / baud_rate 85 01a0 instructions_per_bit equ 416 86 ; constant delays_per_bit 3 87 0003 delays_per_bit equ 3 88 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 89 008a instructions_per_delay equ 138 90 ; constant extra_instructions_per_bit 9 91 0009 extra_instructions_per_bit equ 9 92 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 93 0003 extra_instructions_per_delay equ 3 94 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 95 0087 delay_instructions equ 135 96 ; comment {Oscillator Mask :} 97 008f osccal equ 143 98 ; constant osccal_unit 0x10 99 0010 osccal_unit equ 16 100 ; comment {Analog to digital conversion result register :} 101 001e addres equ 30 102 ; comment {Analog to digital conversion register 0 :} 103 001f addcon0 equ 31 104 ; bind adon addcon0 @ 0 105 001f adon equ addcon0+0 106 001f adon__byte equ addcon0+0 107 0000 adon__bit equ 0 108 ; bind go_done addcon0 @ 2 109 001f go_done equ addcon0+0 110 001f go_done__byte equ addcon0+0 111 0002 go_done__bit equ 2 112 ; bind chs0 addcon0 @ 3 113 001f chs0 equ addcon0+0 114 001f chs0__byte equ addcon0+0 115 0003 chs0__bit equ 3 116 ; bind chs1 addcon0 @ 4 117 001f chs1 equ addcon0+0 118 001f chs1__byte equ addcon0+0 119 0004 chs1__bit equ 4 120 ; bind adcs0 addcon0 @ 6 121 001f adcs0 equ addcon0+0 122 001f adcs0__byte equ addcon0+0 123 0006 adcs0__bit equ 6 124 ; bind adcs1 addcon0 @ 7 125 001f adcs1 equ addcon0+0 126 001f adcs1__byte equ addcon0+0 127 0007 adcs1__bit equ 7 128 ; comment {Interrupt Control Register :} 129 000b intcon equ 11 130 ; bind gpif intcon @ 0 131 000b gpif equ intcon+0 132 000b gpif__byte equ intcon+0 133 0000 gpif__bit equ 0 134 ; bind intf intcon @ 1 135 000b intf equ intcon+0 136 000b intf__byte equ intcon+0 137 0001 intf__bit equ 1 138 ; bind toif intcon @ 2 139 000b toif equ intcon+0 140 000b toif__byte equ intcon+0 141 0002 toif__bit equ 2 142 ; bind gpie intcon @ 3 143 000b gpie equ intcon+0 144 000b gpie__byte equ intcon+0 145 0003 gpie__bit equ 3 146 ; bind inte intcon @ 4 147 000b inte equ intcon+0 148 000b inte__byte equ intcon+0 149 0004 inte__bit equ 4 150 ; bind toie intcon @ 5 151 000b toie equ intcon+0 152 000b toie__byte equ intcon+0 153 0005 toie__bit equ 5 154 ; bind peie intcon @ 6 155 000b peie equ intcon+0 156 000b peie__byte equ intcon+0 157 0006 peie__bit equ 6 158 ; bind gie intcon @ 7 159 000b gie equ intcon+0 160 000b gie__byte equ intcon+0 161 0007 gie__bit equ 7 162 000c pir1 equ 12 163 ; bind adif pir1 @ 6 164 000c adif equ pir1+0 165 000c adif__byte equ pir1+0 166 0006 adif__bit equ 6 167 008c pie1 equ 140 168 ; bind adie pie1 @ 6 169 008c adie equ pie1+0 170 008c adie__byte equ pie1+0 171 0006 adie__bit equ 6 172 ; comment {Analog to digital conversion register 1 :} 173 009f addcon1 equ 159 174 ; bind pcfg0 addcon1 @ 0 175 009f pcfg0 equ addcon1+0 176 009f pcfg0__byte equ addcon1+0 177 0000 pcfg0__bit equ 0 178 ; bind pcfg1 addcon1 @ 1 179 009f pcfg1 equ addcon1+0 180 009f pcfg1__byte equ addcon1+0 181 0001 pcfg1__bit equ 1 182 ; bind pcfg2 addcon1 @ 2 183 009f pcfg2 equ addcon1+0 184 009f pcfg2__byte equ addcon1+0 185 0002 pcfg2__bit equ 2 186 ; constant ain_bit0 0 187 0000 ain_bit0 equ 0 188 ; constant ain_bit1 1 189 0001 ain_bit1 equ 1 190 ; constant ain_bit2 2 191 0002 ain_bit2 equ 2 192 ; constant serial_in_bit 3 193 0003 serial_in_bit equ 3 194 ; constant ain_bit3 4 195 0004 ain_bit3 equ 4 196 ; constant serial_out_bit 5 197 0005 serial_out_bit equ 5 198 ; constant ain_mask0 {{ 1 << ain_bit0 }} 199 0001 ain_mask0 equ 1 200 ; constant ain_mask1 {{ 1 << ain_bit1 }} 201 0002 ain_mask1 equ 2 202 ; constant ain_mask2 {{ 1 << ain_bit2 }} 203 0004 ain_mask2 equ 4 204 ; constant ain_mask3 {{ 1 << ain_bit3 }} 205 0010 ain_mask3 equ 16 206 ; constant serial_in_mask {{ 1 << serial_in_bit }} 207 0008 serial_in_mask equ 8 208 ; constant serial_out_mask {{ 1 << serial_out_bit }} 209 0020 serial_out_mask equ 32 210 ; constant io_mask 0xf 211 000f io_mask equ 15 212 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} 213 0017 ain_mask equ 23 214 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} 215 0028 serial_mask equ 40 216 ; comment {define port bit assignments} 217 0005 porta equ 5 218 0005 ain0__byte equ 5 219 0000 ain0__bit equ 0 220 0005 ain1__byte equ 5 221 0001 ain1__bit equ 1 222 0005 ain2__byte equ 5 223 0002 ain2__bit equ 2 224 0005 ain3__byte equ 5 225 0004 ain3__bit equ 4 226 0005 serial_in__byte equ 5 227 0003 serial_in__bit equ 3 228 0005 serial_out__byte equ 5 229 0005 serial_out__bit equ 5 230 ; constant analogs_size 4 231 0004 analogs_size equ 4 232 ; string_constants Start 233 string___fetch: 234 010 0082 movwf pcl___register 235 ; id = 1 , 0 , 12 , 4 , 0 , 0 , 0 , 0 , 0r'16' , 10 , 0s'AnalogIn4D' , 15 , 0s'Gramlich&Benson' 236 0000 id___string equ 0 237 id: 238 011 0782 addwf pcl___register,f 239 ; Length = 51 240 012 3433 retlw 51 241 ; 1 242 013 3401 retlw 1 243 ; 0 244 014 3400 retlw 0 245 ; 12 246 015 340c retlw 12 247 ; 4 248 016 3404 retlw 4 249 ; 0 250 017 3400 retlw 0 251 ; 0 252 018 3400 retlw 0 253 ; 0 254 019 3400 retlw 0 255 ; 0 256 01a 3400 retlw 0 257 ; 0r'16' 258 01b 3437 retlw 55 ; random number 259 01c 34d3 retlw 211 ; random number 260 01d 3495 retlw 149 ; random number 261 01e 344f retlw 79 ; random number 262 01f 34bd retlw 189 ; random number 263 020 3420 retlw 32 ; random number 264 021 34bc retlw 188 ; random number 265 022 34da retlw 218 ; random number 266 023 3490 retlw 144 ; random number 267 024 3433 retlw 51 ; random number 268 025 3401 retlw 1 ; random number 269 026 3492 retlw 146 ; random number 270 027 340a retlw 10 ; random number 271 028 348f retlw 143 ; random number 272 029 341c retlw 28 ; random number 273 02a 341c retlw 28 ; random number 274 ; 10 275 02b 340a retlw 10 276 ; `AnalogIn4D' 277 02c 3441 retlw 65 278 02d 346e retlw 110 279 02e 3461 retlw 97 280 02f 346c retlw 108 281 030 346f retlw 111 282 031 3467 retlw 103 283 032 3449 retlw 73 284 033 346e retlw 110 285 034 3434 retlw 52 286 035 3444 retlw 68 287 ; 15 288 036 340f retlw 15 289 ; `Gramlich&Benson' 290 037 3447 retlw 71 291 038 3472 retlw 114 292 039 3461 retlw 97 293 03a 346d retlw 109 294 03b 346c retlw 108 295 03c 3469 retlw 105 296 03d 3463 retlw 99 297 03e 3468 retlw 104 298 03f 3426 retlw 38 299 040 3442 retlw 66 300 041 3465 retlw 101 301 042 346e retlw 110 302 043 3473 retlw 115 303 044 346f retlw 111 304 045 346e retlw 110 305 ; string__constants End 306 ; bank 0 307 ; Default register bank is now 0 308 0020 analogs equ global__variables__bank0+0 309 0024 thresholds_low equ global__variables__bank0+4 310 0028 thresholds_high equ global__variables__bank0+8 311 002c inputs equ global__variables__bank0+12 312 002d complement equ global__variables__bank0+13 313 002e glitch equ global__variables__bank0+14 314 002f id_index equ global__variables__bank0+15 315 0049 vref_mode equ global__bit__variables__bank0+0 316 0049 vref_mode__byte equ global__bit__variables__bank0+0 317 0000 vref_mode__bit equ 0 318 ; comment {Interrupt masks :} 319 0049 interrupt_enable equ global__bit__variables__bank0+0 320 0049 interrupt_enable__byte equ global__bit__variables__bank0+0 321 0001 interrupt_enable__bit equ 1 322 0049 interrupt_pending equ global__bit__variables__bank0+0 323 0049 interrupt_pending__byte equ global__bit__variables__bank0+0 324 0002 interrupt_pending__bit equ 2 325 0049 receiving equ global__bit__variables__bank0+0 326 0049 receiving__byte equ global__bit__variables__bank0+0 327 0003 receiving__bit equ 3 328 0030 falling equ global__variables__bank0+16 329 0031 high equ global__variables__bank0+17 330 0032 low equ global__variables__bank0+18 331 0033 raising equ global__variables__bank0+19 332 333 ; procedure main start 334 main: 335 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 336 0034 main__variables__base equ global__variables__bank0+20 337 0034 main__bytes__base equ main__variables__base+0 338 0038 main__bits__base equ main__variables__base+4 339 0005 main__total__bytes equ 5 340 0037 main__287byte0 equ main__bytes__base+3 341 0037 main__230byte0 equ main__bytes__base+3 342 0037 main__294byte0 equ main__bytes__base+3 343 0037 main__245byte0 equ main__bytes__base+3 344 0037 main__241byte0 equ main__bytes__base+3 345 0037 main__159byte0 equ main__bytes__base+3 346 0037 main__156byte0 equ main__bytes__base+3 347 ; arguments_none 348 0034 main__bit equ main__bytes__base+0 349 0035 main__command equ main__bytes__base+1 350 0036 main__temporary equ main__bytes__base+2 351 ; Initialize the A / D module : 352 ; Select all 4 inputs as A / D : 353 ; addcon1 := 0 354 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 355 046 1683 bsf rp0___byte,rp0___bit 356 ; Register bank is now 1 357 047 019f clrf addcon1 358 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : 359 ; addcon0 := 0x41 360 048 3041 movlw 65 361 ; Switch from register bank 1 to register bank 0 (which contains addcon0) 362 049 1283 bcf rp0___byte,rp0___bit 363 ; Register bank is now 0 364 04a 009f movwf addcon0 365 ; adif := 0 366 04b 130c bcf adif__byte,adif__bit 367 ; adie := 0 368 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) 369 04c 1683 bsf rp0___byte,rp0___bit 370 ; Register bank is now 1 371 04d 130c bcf adie__byte,adie__bit 372 ; gie := 0 373 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) 374 04e 1283 bcf rp0___byte,rp0___bit 375 ; Register bank is now 0 376 04f 138b bcf gie__byte,gie__bit 377 ; call reset {{ }} 378 050 224b call reset 379 ; Set the direction : 380 ; loop_forever ... start 381 main__151loop__forever: 382 ; Wait for a command : 383 ; command := get_byte {{ }} 384 051 2204 call get_byte 385 052 0842 movf get_byte__0return__byte,w 386 053 00b5 movwf main__command 387 ; Dispatch on command : 388 ; switch { command >> 6 } 389 054 3000 movlw HIGH switch__156block_start 390 055 008a movwf pclath___register 391 056 0e35 swapf main__command,w 392 057 00b7 movwf main__156byte0 393 058 0cb7 rrf main__156byte0,f 394 059 0c37 rrf main__156byte0,w 395 05a 3903 andlw 3 396 ; case 0 397 ; case 1 398 ; case 2 399 ; case 3 400 switch__156block_start: 401 05b 0782 addwf pcl___register,f 402 05c 2860 goto switch__156block157 403 05d 28f7 goto switch__156block258 404 05e 2912 goto switch__156block282 405 05f 2913 goto switch__156block285 406 switch__156block_end: 407 ; switch_check 156 switch__156block_start switch__156block_end 408 switch__156block157: 409 ; Command = 00 xx xxxx : 410 ; switch { command >> 3 } 411 060 3000 movlw HIGH switch__159block_start 412 061 008a movwf pclath___register 413 062 0c35 rrf main__command,w 414 063 00b7 movwf main__159byte0 415 064 0cb7 rrf main__159byte0,f 416 065 0c37 rrf main__159byte0,w 417 066 391f andlw 31 418 ; case 0 419 ; case 1 420 ; case 2 3 421 ; case 4 5 422 switch__159block_start: 423 067 0782 addwf pcl___register,f 424 068 2870 goto switch__159block160 425 069 2890 goto switch__159block184 426 06a 28c4 goto switch__159block227 427 06b 28c4 goto switch__159block227 428 06c 28f2 goto switch__159block249 429 06d 28f2 goto switch__159block249 430 06e 28f6 goto switch__159default253 431 06f 28f6 goto switch__159default253 432 switch__159block_end: 433 ; switch_check 159 switch__159block_start switch__159block_end 434 switch__159block160: 435 ; Command = 0000 0 xxx : 436 ; switch { command & 7 } 437 070 3000 movlw HIGH switch__162block_start 438 071 008a movwf pclath___register 439 072 3007 movlw 7 440 073 0535 andwf main__command,w 441 ; case 0 1 2 3 442 ; case 4 443 ; case 5 444 ; case 6 445 switch__162block_start: 446 074 0782 addwf pcl___register,f 447 075 287d goto switch__162block163 448 076 287d goto switch__162block163 449 077 287d goto switch__162block163 450 078 287d goto switch__162block163 451 079 2884 goto switch__162block167 452 07a 2889 goto switch__162block171 453 07b 288d goto switch__162block175 454 07c 288f goto switch__162default179 455 switch__162block_end: 456 ; switch_check 162 switch__162block_start switch__162block_end 457 switch__162block163: 458 ; Read Pin < Command = 0000 00 bb > : 459 ; call send_byte {{ analogs ~~ {{ command }} }} 460 07d 3020 movlw LOW analogs 461 07e 0735 addwf main__command,w 462 07f 0084 movwf fsr___register 463 080 0800 movf indf___register,w 464 081 00c5 movwf send_byte__char 465 082 2225 call send_byte 466 083 288f goto switch__162end 467 switch__162block167: 468 ; Read Binary Values < Command = 0000 0100 > : 469 ; call send_byte {{ inputs ^ complement }} 470 084 082c movf inputs,w 471 085 062d xorwf complement,w 472 086 00c5 movwf send_byte__char 473 087 2225 call send_byte 474 088 288f goto switch__162end 475 switch__162block171: 476 ; Read Raw Binary < Command = 0000 0101 > : 477 ; call send_byte {{ inputs }} 478 089 082c movf inputs,w 479 08a 00c5 movwf send_byte__char 480 08b 2225 call send_byte 481 08c 288f goto switch__162end 482 switch__162block175: 483 ; Reset < Command = 0000 0110 > : 484 ; call reset {{ }} 485 08d 224b call reset 486 08e 288f goto switch__162end 487 switch__162default179: 488 ; Undefined command : 489 switch__162end: 490 08f 28f6 goto switch__159end 491 switch__159block184: 492 ; Command = 0000 1 xxx : 493 ; switch { command & 7 } 494 090 3000 movlw HIGH switch__186block_start 495 091 008a movwf pclath___register 496 092 3007 movlw 7 497 093 0535 andwf main__command,w 498 ; case 0 499 ; case 1 500 ; case 2 501 ; case 3 502 ; case 4 503 ; case 5 504 ; case 6 7 505 switch__186block_start: 506 094 0782 addwf pcl___register,f 507 095 289d goto switch__186block187 508 096 28a1 goto switch__186block191 509 097 28a5 goto switch__186block195 510 098 28a9 goto switch__186block199 511 099 28ad goto switch__186block203 512 09a 28b1 goto switch__186block207 513 09b 28b8 goto switch__186block215 514 09c 28b8 goto switch__186block215 515 switch__186block_end: 516 ; switch_check 186 switch__186block_start switch__186block_end 517 switch__186block187: 518 ; Read Complement Mask < Command = 0000 1000 > : 519 ; call send_byte {{ complement }} 520 09d 082d movf complement,w 521 09e 00c5 movwf send_byte__char 522 09f 2225 call send_byte 523 0a0 28c3 goto switch__186end 524 switch__186block191: 525 ; Read High Mask < Command = 0000 1001 > : 526 ; call send_byte {{ high }} 527 0a1 0831 movf high,w 528 0a2 00c5 movwf send_byte__char 529 0a3 2225 call send_byte 530 0a4 28c3 goto switch__186end 531 switch__186block195: 532 ; Read Low Mask < Command = 0000 1010 > : 533 ; call send_byte {{ low }} 534 0a5 0832 movf low,w 535 0a6 00c5 movwf send_byte__char 536 0a7 2225 call send_byte 537 0a8 28c3 goto switch__186end 538 switch__186block199: 539 ; Read Raising Mask < Command = 0000 1011 > : 540 ; call send_byte {{ raising }} 541 0a9 0833 movf raising,w 542 0aa 00c5 movwf send_byte__char 543 0ab 2225 call send_byte 544 0ac 28c3 goto switch__186end 545 switch__186block203: 546 ; Read Falling Mask < Command = 0000 1100 > : 547 ; call send_byte {{ falling }} 548 0ad 0830 movf falling,w 549 0ae 00c5 movwf send_byte__char 550 0af 2225 call send_byte 551 0b0 28c3 goto switch__186end 552 switch__186block207: 553 ; Read Vref Mode < Command = 0000 1101 > : 554 ; temporary := 0 555 0b1 01b6 clrf main__temporary 556 ; if { vref_mode } start 557 ; expression=`{ vref_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 558 0b2 1849 btfsc vref_mode__byte,vref_mode__bit 559 ; if { vref_mode } body start 560 ; temporary @ 0 := 1 561 ; Select temporary @ 0 562 0036 main__temporary__211select0 equ main__temporary+0 563 0036 main__temporary__211select0__byte equ main__temporary+0 564 0000 main__temporary__211select0__bit equ 0 565 0b3 1436 bsf main__temporary__211select0__byte,main__temporary__211select0__bit 566 ; if { vref_mode } body end 567 ; if exp=`vref_mode' false skip delay=2 568 ; Other expression=`{ vref_mode }' delay=2 569 ; if { vref_mode } end 570 ; call send_byte {{ temporary }} 571 0b4 0836 movf main__temporary,w 572 0b5 00c5 movwf send_byte__char 573 0b6 2225 call send_byte 574 0b7 28c3 goto switch__186end 575 switch__186block215: 576 ; Set Vref Mode < Command = 0000 111 v > : 577 ; temporary := 0 578 0b8 01b6 clrf main__temporary 579 ; vref_mode := 0 580 0b9 1049 bcf vref_mode__byte,vref_mode__bit 581 ; if { command @ 0 } start 582 ; Alias variable for select command @ 0 583 0035 main__command__219select0 equ main__command+0 584 0035 main__command__219select0__byte equ main__command+0 585 0000 main__command__219select0__bit equ 0 586 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=0 true_size=3 false_size=0 587 0ba 1c35 btfss main__command__219select0__byte,main__command__219select0__bit 588 0bb 28bf goto label219__1end 589 ; if { command @ 0 } body start 590 ; vref_mode := 1 591 0bc 1449 bsf vref_mode__byte,vref_mode__bit 592 ; temporary := 1 593 0bd 3001 movlw 1 594 0be 00b6 movwf main__temporary 595 ; if { command @ 0 } body end 596 label219__1end: 597 ; if exp=` command @ 0 ' empty false 598 ; Other expression=`{ command @ 0 }' delay=-1 599 ; if { command @ 0 } end 600 ; addcon1 := temporary 601 0bf 0836 movf main__temporary,w 602 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 603 0c0 1683 bsf rp0___byte,rp0___bit 604 ; Register bank is now 1 605 0c1 009f movwf addcon1 606 ; Switch from register bank 1 to register bank 0 607 0c2 1283 bcf rp0___byte,rp0___bit 608 ; Register bank is now 0 609 switch__186end: 610 0c3 28f6 goto switch__159end 611 switch__159block227: 612 ; Command = 0001 xxxx : 613 ; bit := command & 3 614 0c4 3003 movlw 3 615 0c5 0535 andwf main__command,w 616 0c6 00b4 movwf main__bit 617 ; switch { {{ command >> 2 }} & 3 } 618 0c7 3000 movlw HIGH switch__230block_start 619 0c8 008a movwf pclath___register 620 0c9 0c35 rrf main__command,w 621 0ca 00b7 movwf main__230byte0 622 0cb 0c37 rrf main__230byte0,w 623 0cc 3903 andlw 3 624 ; case 0 625 ; case 1 626 ; case 2 627 ; case 3 628 switch__230block_start: 629 0cd 0782 addwf pcl___register,f 630 0ce 28d2 goto switch__230block231 631 0cf 28d9 goto switch__230block235 632 0d0 28e0 goto switch__230block239 633 0d1 28e9 goto switch__230block243 634 switch__230block_end: 635 ; switch_check 230 switch__230block_start switch__230block_end 636 switch__230block231: 637 ; Read High Threshold < Command = 0001 00 bb > : 638 ; call send_byte {{ thresholds_high ~~ {{ bit }} }} 639 0d2 3028 movlw LOW thresholds_high 640 0d3 0734 addwf main__bit,w 641 0d4 0084 movwf fsr___register 642 0d5 0800 movf indf___register,w 643 0d6 00c5 movwf send_byte__char 644 0d7 2225 call send_byte 645 0d8 28f1 goto switch__230end 646 switch__230block235: 647 ; Read Low Threshold < Command = 0001 01 bb > : 648 ; call send_byte {{ thresholds_low ~~ {{ bit }} }} 649 0d9 3024 movlw LOW thresholds_low 650 0da 0734 addwf main__bit,w 651 0db 0084 movwf fsr___register 652 0dc 0800 movf indf___register,w 653 0dd 00c5 movwf send_byte__char 654 0de 2225 call send_byte 655 0df 28f1 goto switch__230end 656 switch__230block239: 657 ; Set High Threshold < Command = 0001 10 bb > : 658 ; thresholds_high ~~ {{ bit }} := get_byte {{ }} 659 0e0 2204 call get_byte 660 0e1 0842 movf get_byte__0return__byte,w 661 0e2 00b7 movwf main__241byte0 662 0e3 3028 movlw LOW thresholds_high 663 0e4 0734 addwf main__bit,w 664 0e5 0084 movwf fsr___register 665 0e6 0837 movf main__241byte0,w 666 0e7 0080 movwf indf___register 667 0e8 28f1 goto switch__230end 668 switch__230block243: 669 ; Set Low Threshold < Command = 0001 11 bb > : 670 ; thresholds_low ~~ {{ bit }} := get_byte {{ }} 671 0e9 2204 call get_byte 672 0ea 0842 movf get_byte__0return__byte,w 673 0eb 00b7 movwf main__245byte0 674 0ec 3024 movlw LOW thresholds_low 675 0ed 0734 addwf main__bit,w 676 0ee 0084 movwf fsr___register 677 0ef 0837 movf main__245byte0,w 678 0f0 0080 movwf indf___register 679 switch__230end: 680 0f1 28f6 goto switch__159end 681 switch__159block249: 682 ; Set Complement Mask < Command = 0010 cccc > : 683 ; complement := command & io_mask 684 0f2 300f movlw 15 685 0f3 0535 andwf main__command,w 686 0f4 00ad movwf complement 687 0f5 28f6 goto switch__159end 688 switch__159default253: 689 ; Do nothing : 690 switch__159end: 691 0f6 2985 goto switch__156end 692 switch__156block258: 693 ; Command = 01 xx xxxx : 694 ; temporary := command & io_mask 695 0f7 300f movlw 15 696 0f8 0535 andwf main__command,w 697 0f9 00b6 movwf main__temporary 698 ; Kludge : to get switch so it does not span 256 byte boundary : 699 ; nop 3 700 ; Delay 3 cycles 701 0fa 0000 nop 702 0fb 0000 nop 703 0fc 0000 nop 704 ; switch { {{ command >> 4 }} & 3 } 705 0fd 3001 movlw HIGH switch__263block_start 706 0fe 008a movwf pclath___register 707 0ff 0e35 swapf main__command,w 708 100 3903 andlw 3 709 ; case 0 710 ; case 1 711 ; case 2 712 ; case 3 713 switch__263block_start: 714 101 0782 addwf pcl___register,f 715 102 2906 goto switch__263block264 716 103 2909 goto switch__263block268 717 104 290c goto switch__263block272 718 105 290f goto switch__263block276 719 switch__263block_end: 720 ; switch_check 263 switch__263block_start switch__263block_end 721 switch__263block264: 722 ; Set High Mask < Command = 0100 hhhh > : 723 ; high := temporary 724 106 0836 movf main__temporary,w 725 107 00b1 movwf high 726 108 2911 goto switch__263end 727 switch__263block268: 728 ; Set Low Mask < Command = 0101 llll > : 729 ; low := temporary 730 109 0836 movf main__temporary,w 731 10a 00b2 movwf low 732 10b 2911 goto switch__263end 733 switch__263block272: 734 ; Set Raising Mask < Command = 0110 rrrr > : 735 ; raising := temporary 736 10c 0836 movf main__temporary,w 737 10d 00b3 movwf raising 738 10e 2911 goto switch__263end 739 switch__263block276: 740 ; Set Falling Mask < Command = 0111 ffff > : 741 ; falling := temporary 742 10f 0836 movf main__temporary,w 743 110 00b0 movwf falling 744 switch__263end: 745 111 2985 goto switch__156end 746 switch__156block282: 747 ; Do nothing < Command = 10 xx xxxx > : 748 112 2985 goto switch__156end 749 switch__156block285: 750 ; Command = 11 xx xxxx : 751 ; switch { {{ command >> 3 }} & 7 } 752 113 3001 movlw HIGH switch__287block_start 753 114 008a movwf pclath___register 754 115 0c35 rrf main__command,w 755 116 00b7 movwf main__287byte0 756 117 0cb7 rrf main__287byte0,f 757 118 0c37 rrf main__287byte0,w 758 119 3907 andlw 7 759 ; case 0 1 2 3 4 760 ; case 5 761 ; case 6 762 ; case 7 763 switch__287block_start: 764 11a 0782 addwf pcl___register,f 765 11b 2923 goto switch__287block288 766 11c 2923 goto switch__287block288 767 11d 2923 goto switch__287block288 768 11e 2923 goto switch__287block288 769 11f 2923 goto switch__287block288 770 120 2924 goto switch__287block292 771 121 2934 goto switch__287block306 772 122 2950 goto switch__287block324 773 switch__287block_end: 774 ; switch_check 287 switch__287block_start switch__287block_end 775 switch__287block288: 776 ; Command = 1100 xxxx or 1110 0 xxx : 777 ; Do nothing : 778 123 2985 goto switch__287end 779 switch__287block292: 780 ; Read Interrupt Bits < Command = 1110 1111 > : 781 ; if { {{ command & 7 }} = 7 } start 782 124 3007 movlw 7 783 125 0535 andwf main__command,w 784 126 00b7 movwf main__294byte0 785 127 3007 movlw 7 786 128 0237 subwf main__294byte0,w 787 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 788 129 1d03 btfss z___byte,z___bit 789 12a 2933 goto label294__1end 790 ; if { {{ command & 7 }} = 7 } body start 791 ; Return Interrupt Bits : 792 ; temporary := 0 793 12b 01b6 clrf main__temporary 794 ; if { interrupt_enable } start 795 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 796 12c 18c9 btfsc interrupt_enable__byte,interrupt_enable__bit 797 ; if { interrupt_enable } body start 798 ; temporary @ 1 := 1 799 ; Select temporary @ 1 800 0036 main__temporary__298select0 equ main__temporary+0 801 0036 main__temporary__298select0__byte equ main__temporary+0 802 0001 main__temporary__298select0__bit equ 1 803 12d 14b6 bsf main__temporary__298select0__byte,main__temporary__298select0__bit 804 ; if { interrupt_enable } body end 805 ; if exp=`interrupt_enable' false skip delay=2 806 ; Other expression=`{ interrupt_enable }' delay=2 807 ; if { interrupt_enable } end 808 ; if { interrupt_pending } start 809 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 810 12e 1949 btfsc interrupt_pending__byte,interrupt_pending__bit 811 ; if { interrupt_pending } body start 812 ; temporary @ 0 := 1 813 ; Select temporary @ 0 814 0036 main__temporary__301select0 equ main__temporary+0 815 0036 main__temporary__301select0__byte equ main__temporary+0 816 0000 main__temporary__301select0__bit equ 0 817 12f 1436 bsf main__temporary__301select0__byte,main__temporary__301select0__bit 818 ; if { interrupt_pending } body end 819 ; if exp=`interrupt_pending' false skip delay=2 820 ; Other expression=`{ interrupt_pending }' delay=2 821 ; if { interrupt_pending } end 822 ; call send_byte {{ temporary }} 823 130 0836 movf main__temporary,w 824 131 00c5 movwf send_byte__char 825 132 2225 call send_byte 826 ; if { {{ command & 7 }} = 7 } body end 827 label294__1end: 828 ; if exp=` {{ command & 7 }} = 7 ' empty false 829 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 830 ; if { {{ command & 7 }} = 7 } end 831 133 2985 goto switch__287end 832 switch__287block306: 833 ; Shared Interrupt commands < Command = 1111 0 xxx > : 834 ; switch { command & 7 } 835 134 3001 movlw HIGH switch__308block_start 836 135 008a movwf pclath___register 837 136 3007 movlw 7 838 137 0535 andwf main__command,w 839 ; case 0 1 2 3 840 ; case 4 5 841 ; case 6 7 842 switch__308block_start: 843 138 0782 addwf pcl___register,f 844 139 2941 goto switch__308block309 845 13a 2941 goto switch__308block309 846 13b 2941 goto switch__308block309 847 13c 2941 goto switch__308block309 848 13d 2948 goto switch__308block314 849 13e 2948 goto switch__308block314 850 13f 294c goto switch__308block318 851 140 294c goto switch__308block318 852 switch__308block_end: 853 ; switch_check 308 switch__308block_start switch__308block_end 854 switch__308block309: 855 ; Set interrupt bits < Command = 1111 10 ep > : 856 ; interrupt_enable := command @ 1 857 ; Alias variable for select command @ 1 858 0035 main__command__311select0 equ main__command+0 859 0035 main__command__311select0__byte equ main__command+0 860 0001 main__command__311select0__bit equ 1 861 141 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 862 142 18b5 btfsc main__command__311select0__byte,main__command__311select0__bit 863 143 14c9 bsf interrupt_enable__byte,interrupt_enable__bit 864 ; interrupt_pending := command @ 0 865 ; Alias variable for select command @ 0 866 0035 main__command__312select0 equ main__command+0 867 0035 main__command__312select0__byte equ main__command+0 868 0000 main__command__312select0__bit equ 0 869 144 1149 bcf interrupt_pending__byte,interrupt_pending__bit 870 145 1835 btfsc main__command__312select0__byte,main__command__312select0__bit 871 146 1549 bsf interrupt_pending__byte,interrupt_pending__bit 872 147 294f goto switch__308end 873 switch__308block314: 874 ; Set Interrupt Pending < Command = 1111 110 p > : 875 ; interrupt_pending := command @ 0 876 ; Alias variable for select command @ 0 877 0035 main__command__316select0 equ main__command+0 878 0035 main__command__316select0__byte equ main__command+0 879 0000 main__command__316select0__bit equ 0 880 148 1149 bcf interrupt_pending__byte,interrupt_pending__bit 881 149 1835 btfsc main__command__316select0__byte,main__command__316select0__bit 882 14a 1549 bsf interrupt_pending__byte,interrupt_pending__bit 883 14b 294f goto switch__308end 884 switch__308block318: 885 ; Set Interrupt Enable < Command = 1110 111 e > : 886 ; interrupt_enable := command @ 0 887 ; Alias variable for select command @ 0 888 0035 main__command__320select0 equ main__command+0 889 0035 main__command__320select0__byte equ main__command+0 890 0000 main__command__320select0__bit equ 0 891 14c 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 892 14d 1835 btfsc main__command__320select0__byte,main__command__320select0__bit 893 14e 14c9 bsf interrupt_enable__byte,interrupt_enable__bit 894 switch__308end: 895 14f 2985 goto switch__287end 896 switch__287block324: 897 ; Shared commands < Command = 1111 1 xxx > : 898 ; switch { command & 7 } 899 150 3001 movlw HIGH switch__326block_start 900 151 008a movwf pclath___register 901 152 3007 movlw 7 902 153 0535 andwf main__command,w 903 ; case 0 904 ; case 1 905 ; case 2 906 ; case 3 907 ; case 4 908 ; case 5 909 ; case 6 910 ; case 7 911 switch__326block_start: 912 154 0782 addwf pcl___register,f 913 155 295d goto switch__326block327 914 156 2962 goto switch__326block331 915 157 2967 goto switch__326block335 916 158 296d goto switch__326block339 917 159 2970 goto switch__326block343 918 15a 297b goto switch__326block351 919 15b 297d goto switch__326block355 920 15c 2982 goto switch__326block360 921 switch__326block_end: 922 ; switch_check 326 switch__326block_start switch__326block_end 923 switch__326block327: 924 ; Clock Decrement < Command = 1111 1000 > : 925 ; osccal := osccal - osccal_unit 926 15d 30f0 movlw 240 927 ; Switch from register bank 0 to register bank 1 (which contains osccal) 928 15e 1683 bsf rp0___byte,rp0___bit 929 ; Register bank is now 1 930 15f 078f addwf osccal,f 931 ; Switch from register bank 1 to register bank 0 932 160 1283 bcf rp0___byte,rp0___bit 933 ; Register bank is now 0 934 161 2985 goto switch__326end 935 switch__326block331: 936 ; Clock Increment < Command = 1111 1001 > : 937 ; osccal := osccal + osccal_unit 938 162 3010 movlw 16 939 ; Switch from register bank 0 to register bank 1 (which contains osccal) 940 163 1683 bsf rp0___byte,rp0___bit 941 ; Register bank is now 1 942 164 078f addwf osccal,f 943 ; Switch from register bank 1 to register bank 0 944 165 1283 bcf rp0___byte,rp0___bit 945 ; Register bank is now 0 946 166 2985 goto switch__326end 947 switch__326block335: 948 ; Clock Read < Command = 1111 1010 > : 949 ; call send_byte {{ osccal }} 950 ; Switch from register bank 0 to register bank 1 (which contains osccal) 951 167 1683 bsf rp0___byte,rp0___bit 952 ; Register bank is now 1 953 168 080f movf osccal,w 954 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 955 169 1283 bcf rp0___byte,rp0___bit 956 ; Register bank is now 0 957 16a 00c5 movwf send_byte__char 958 16b 2225 call send_byte 959 16c 2985 goto switch__326end 960 switch__326block339: 961 ; Clock Pulse < Command = 1111 1011 > : 962 ; call send_byte {{ 0 }} 963 16d 01c5 clrf send_byte__char 964 16e 2225 call send_byte 965 16f 2985 goto switch__326end 966 switch__326block343: 967 ; ID Next < Command = 1111 1100 > : 968 ; call send_byte {{ id ~~ {{ id_index }} }} 969 170 0a2f incf id_index,w 970 171 018a clrf pclath___register 971 172 2011 call id 972 173 00c5 movwf send_byte__char 973 174 2225 call send_byte 974 ; id_index := id_index + 1 975 175 0aaf incf id_index,f 976 ; if { id_index >= id . size } start 977 176 3033 movlw 51 978 177 022f subwf id_index,w 979 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 980 178 1803 btfsc c___byte,c___bit 981 ; if { id_index >= id . size } body start 982 ; id_index := 0 983 179 01af clrf id_index 984 ; if { id_index >= id . size } body end 985 ; if exp=` id_index >= id . size ' false skip delay=4 986 ; Other expression=`{ id_index >= id . size }' delay=4 987 ; if { id_index >= id . size } end 988 17a 2985 goto switch__326end 989 switch__326block351: 990 ; ID Reset < Command = 1111 1101 > : 991 ; id_index := 0 992 17b 01af clrf id_index 993 17c 2985 goto switch__326end 994 switch__326block355: 995 ; Glitch Read < Command = 1111 1110 > : 996 ; call send_byte {{ glitch }} 997 17d 082e movf glitch,w 998 17e 00c5 movwf send_byte__char 999 17f 2225 call send_byte 1000 ; glitch := 0 1001 180 01ae clrf glitch 1002 181 2985 goto switch__326end 1003 switch__326block360: 1004 ; Glitch < Command = 1111 1111 > : 1005 ; if { glitch != 0xff } start 1006 182 0a2e incf glitch,w 1007 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1008 183 1d03 btfss z___byte,z___bit 1009 ; if { glitch != 0xff } body start 1010 ; glitch := glitch + 1 1011 184 0aae incf glitch,f 1012 ; if { glitch != 0xff } body end 1013 ; if exp=` glitch != 0xff ' false skip delay=3 1014 ; Other expression=`{ glitch != 0xff }' delay=3 1015 ; if { glitch != 0xff } end 1016 switch__326end: 1017 switch__287end: 1018 switch__156end: 1019 185 2851 goto main__151loop__forever 1020 ; loop_forever ... end 1021 ; procedure main end 1022 1023 ; procedure delay start 1024 ; optimize 0 1025 delay: 1026 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1027 0039 delay__variables__base equ global__variables__bank0+25 1028 0039 delay__bytes__base equ delay__variables__base+0 1029 0042 delay__bits__base equ delay__variables__base+9 1030 0009 delay__total__bytes equ 9 1031 0041 delay__374byte1 equ delay__bytes__base+8 1032 0041 delay__438byte0 equ delay__bytes__base+8 1033 0041 delay__407byte0 equ delay__bytes__base+8 1034 0041 delay__398byte0 equ delay__bytes__base+8 1035 0041 delay__396byte3 equ delay__bytes__base+8 1036 0041 delay__436byte1 equ delay__bytes__base+8 1037 ; arguments_none 1038 ; uniform_delay delay_instructions 1039 ; Uniform delay remaining = 131 Accumulated Delay = 0 1040 ; Uniform delay remaining = 131 Accumulated Delay = 0 1041 ; This procedure will delay for one third of a bit time . 1042 ; Uniform delay remaining = 131 Accumulated Delay = 0 1043 ; Uniform delay remaining = 131 Accumulated Delay = 0 1044 ; Uniform delay remaining = 131 Accumulated Delay = 0 1045 0039 delay__channel equ delay__bytes__base+0 1046 ; Uniform delay remaining = 131 Accumulated Delay = 0 1047 003a delay__current equ delay__bytes__base+1 1048 ; Uniform delay remaining = 131 Accumulated Delay = 0 1049 003b delay__changed equ delay__bytes__base+2 1050 ; Uniform delay remaining = 131 Accumulated Delay = 0 1051 003c delay__previous equ delay__bytes__base+3 1052 ; Uniform delay remaining = 131 Accumulated Delay = 0 1053 003d delay__not_current equ delay__bytes__base+4 1054 ; Uniform delay remaining = 131 Accumulated Delay = 0 1055 003e delay__counter equ delay__bytes__base+5 1056 ; Uniform delay remaining = 131 Accumulated Delay = 0 1057 003f delay__mask equ delay__bytes__base+6 1058 ; Uniform delay remaining = 131 Accumulated Delay = 0 1059 0040 delay__result equ delay__bytes__base+7 1060 ; Uniform delay remaining = 131 Accumulated Delay = 0 1061 ; Uniform delay remaining = 131 Accumulated Delay = 0 1062 ; Kick the dog : 1063 ; Uniform delay remaining = 131 Accumulated Delay = 0 1064 ; watch_dog_reset 1065 186 0064 clrwdt 1066 ; Uniform delay remaining = 130 Accumulated Delay = 1 1067 ; Uniform delay remaining = 130 Accumulated Delay = 1 1068 ; channel := {{ counter >> 1 }} & 3 1069 187 1003 bcf c___byte,c___bit 1070 188 0c3e rrf delay__counter,w 1071 189 3903 andlw 3 1072 18a 00b9 movwf delay__channel 1073 ; Uniform delay remaining = 126 Accumulated Delay = 5 1074 ; counter := counter + 1 1075 18b 0abe incf delay__counter,f 1076 ; Uniform delay remaining = 125 Accumulated Delay = 6 1077 ; if { counter @ 0 } start 1078 ; Alias variable for select counter @ 0 1079 003e delay__counter__396select0 equ delay__counter+0 1080 003e delay__counter__396select0__byte equ delay__counter+0 1081 0000 delay__counter__396select0__bit equ 0 1082 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=44 false_delay=104 true_size=48 false_size=57 1083 18c 1c3e btfss delay__counter__396select0__byte,delay__counter__396select0__bit 1084 18d 29c4 goto label396__1false 1085 label396__1true: 1086 ; if { counter @ 0 } body start 1087 ; Uniform delay remaining = 125 Accumulated Delay = 0 1088 ; Set up and wait for acquistion : 1089 ; Uniform delay remaining = 125 Accumulated Delay = 0 1090 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 1091 18e 0d39 rlf delay__channel,w 1092 18f 00c1 movwf delay__398byte0 1093 190 0dc1 rlf delay__398byte0,f 1094 191 0d41 rlf delay__398byte0,w 1095 192 39f8 andlw 248 1096 193 3918 andlw 24 1097 194 3841 iorlw 65 1098 195 009f movwf addcon0 1099 ; Uniform delay remaining = 117 Accumulated Delay = 8 1100 ; Setup for interrupts : 1101 ; Uniform delay remaining = 117 Accumulated Delay = 8 1102 ; previous := current 1103 196 083a movf delay__current,w 1104 197 00bc movwf delay__previous 1105 ; Uniform delay remaining = 115 Accumulated Delay = 10 1106 ; Read the I / O port once : 1107 ; Uniform delay remaining = 115 Accumulated Delay = 10 1108 ; current := inputs ^ complement 1109 198 082c movf inputs,w 1110 199 062d xorwf complement,w 1111 19a 00ba movwf delay__current 1112 ; Uniform delay remaining = 112 Accumulated Delay = 13 1113 ; not_current := current ^ 0xf 1114 19b 300f movlw 15 1115 19c 063a xorwf delay__current,w 1116 19d 00bd movwf delay__not_current 1117 ; Uniform delay remaining = 109 Accumulated Delay = 16 1118 ; changed := current ^ previous 1119 19e 083a movf delay__current,w 1120 19f 063c xorwf delay__previous,w 1121 1a0 00bb movwf delay__changed 1122 ; Uniform delay remaining = 106 Accumulated Delay = 19 1123 ; Uniform delay remaining = 106 Accumulated Delay = 19 1124 ; See about triggering the interrupt_pending flag : 1125 ; Uniform delay remaining = 106 Accumulated Delay = 19 1126 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start 1127 1a1 0832 movf low,w 1128 1a2 053d andwf delay__not_current,w 1129 1a3 00c1 movwf delay__407byte0 1130 1a4 0831 movf high,w 1131 1a5 053a andwf delay__current,w 1132 1a6 04c1 iorwf delay__407byte0,f 1133 1a7 083b movf delay__changed,w 1134 1a8 053a andwf delay__current,w 1135 1a9 0533 andwf raising,w 1136 1aa 04c1 iorwf delay__407byte0,f 1137 1ab 083b movf delay__changed,w 1138 1ac 053d andwf delay__not_current,w 1139 1ad 0530 andwf falling,w 1140 1ae 0441 iorwf delay__407byte0,w 1141 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 1142 1af 1d03 btfss z___byte,z___bit 1143 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start 1144 ; Uniform delay remaining = 106 Accumulated Delay = 0 1145 ; interrupt_pending := 1 1146 1b0 1549 bsf interrupt_pending__byte,interrupt_pending__bit 1147 ; Uniform delay remaining = 105 Accumulated Delay = 1 1148 ; Uniform delay remaining = 105 Accumulated Delay = 1 1149 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end 1150 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 1151 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 1152 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end 1153 ; Uniform delay remaining = 90 Accumulated Delay = 35 1154 ; Uniform delay remaining = 90 Accumulated Delay = 35 1155 ; Send an interrupt if interrupts are enabled : 1156 ; Uniform delay remaining = 90 Accumulated Delay = 35 1157 ; if { interrupt_pending && interrupt_enable } start 1158 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1159 1b1 1949 btfsc interrupt_pending__byte,interrupt_pending__bit 1160 1b2 29b6 goto label412__2true 1161 label412__2false: 1162 ; Delay 2 cycles 1163 1b3 0000 nop 1164 1b4 0000 nop 1165 1b5 29be goto and412__0false 1166 label412__2true: 1167 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1168 1b6 1cc9 btfss interrupt_enable__byte,interrupt_enable__bit 1169 1b7 29bb goto label412__1false 1170 label412__1true: 1171 and412__0true: 1172 ; if { interrupt_pending && interrupt_enable } body start 1173 ; Uniform delay remaining = 90 Accumulated Delay = 0 1174 ; Shove serial out to low : 1175 ; Uniform delay remaining = 90 Accumulated Delay = 0 1176 ; interrupt_enable := 0 1177 1b8 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 1178 ; Uniform delay remaining = 89 Accumulated Delay = 1 1179 ; serial_out := 0 1180 1b9 1285 bcf serial_out__byte,serial_out__bit 1181 ; Uniform delay remaining = 88 Accumulated Delay = 2 1182 ; Uniform delay remaining = 88 Accumulated Delay = 2 1183 ; if { interrupt_pending && interrupt_enable } body end 1184 1ba 29be goto label412__1end 1185 label412__1false: 1186 ; Delay 3 cycles 1187 1bb 0000 nop 1188 1bc 0000 nop 1189 1bd 0000 nop 1190 ; if exp=`interrupt_enable' total delay=6 1191 ; if exp=`interrupt_enable' generic 1192 label412__1end: 1193 ; Other expression=`interrupt_enable' delay=6 1194 ; if exp=`interrupt_pending' total delay=9 1195 ; if exp=`interrupt_pending' generic 1196 label412__2end: 1197 ; Other expression=`interrupt_pending' delay=9 1198 and412__0false: 1199 and412__0end: 1200 ; if { interrupt_pending && interrupt_enable } end 1201 ; Uniform delay remaining = 81 Accumulated Delay = 44 1202 ; Uniform delay remaining = 81 Accumulated Delay = 44 1203 ; if { counter @ 0 } body end 1204 ; Delay 59 cycles 1205 1be 3013 movlw 19 1206 1bf 00c1 movwf delay__396byte3 1207 delay__396delay2: 1208 1c0 0bc1 decfsz delay__396byte3,f 1209 1c1 29c0 goto delay__396delay2 1210 1c2 0000 nop 1211 1c3 29fd goto label396__1end 1212 label396__1false: 1213 ; else body start 1214 ; Uniform delay remaining = 125 Accumulated Delay = 0 1215 ; Start the conversion : 1216 ; Uniform delay remaining = 125 Accumulated Delay = 0 1217 ; go_done := 1 1218 1c4 151f bsf go_done__byte,go_done__bit 1219 ; Uniform delay remaining = 124 Accumulated Delay = 1 1220 ; mask := 0 1221 1c5 01bf clrf delay__mask 1222 ; Uniform delay remaining = 123 Accumulated Delay = 2 1223 ; if { channel @ 1 } start 1224 ; Alias variable for select channel @ 1 1225 0039 delay__channel__421select0 equ delay__channel+0 1226 0039 delay__channel__421select0__byte equ delay__channel+0 1227 0001 delay__channel__421select0__bit equ 1 1228 ; expression=`{ channel @ 1 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 1229 1c6 1cb9 btfss delay__channel__421select0__byte,delay__channel__421select0__bit 1230 1c7 29cd goto label421__1false 1231 label421__1true: 1232 ; if { channel @ 1 } body start 1233 ; Uniform delay remaining = 123 Accumulated Delay = 0 1234 ; if { channel @ 0 } start 1235 ; Alias variable for select channel @ 0 1236 0039 delay__channel__422select0 equ delay__channel+0 1237 0039 delay__channel__422select0__byte equ delay__channel+0 1238 0000 delay__channel__422select0__bit equ 0 1239 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1240 1c8 1839 btfsc delay__channel__422select0__byte,delay__channel__422select0__bit 1241 ; if { channel @ 0 } body start 1242 ; Uniform delay remaining = 123 Accumulated Delay = 0 1243 ; mask @ 3 := 1 1244 ; Select mask @ 3 1245 003f delay__mask__423select0 equ delay__mask+0 1246 003f delay__mask__423select0__byte equ delay__mask+0 1247 0003 delay__mask__423select0__bit equ 3 1248 1c9 15bf bsf delay__mask__423select0__byte,delay__mask__423select0__bit 1249 ; Uniform delay remaining = 122 Accumulated Delay = 1 1250 ; Uniform delay remaining = 122 Accumulated Delay = 1 1251 ; if { channel @ 0 } body end 1252 1ca 1c39 btfss delay__channel__422select0__byte,delay__channel__422select0__bit 1253 ; else body start 1254 ; Uniform delay remaining = 123 Accumulated Delay = 0 1255 ; mask @ 2 := 1 1256 ; Select mask @ 2 1257 003f delay__mask__425select0 equ delay__mask+0 1258 003f delay__mask__425select0__byte equ delay__mask+0 1259 0002 delay__mask__425select0__bit equ 2 1260 1cb 153f bsf delay__mask__425select0__byte,delay__mask__425select0__bit 1261 ; Uniform delay remaining = 122 Accumulated Delay = 1 1262 ; Uniform delay remaining = 122 Accumulated Delay = 1 1263 ; else body end 1264 ; if exp=` channel @ 0 ' single true and false skip delay=4 1265 ; Other expression=`{ channel @ 0 }' delay=4 1266 ; if { channel @ 0 } end 1267 ; Uniform delay remaining = 119 Accumulated Delay = 4 1268 ; Uniform delay remaining = 119 Accumulated Delay = 4 1269 ; if { channel @ 1 } body end 1270 1cc 29d2 goto label421__1end 1271 label421__1false: 1272 ; else body start 1273 ; Uniform delay remaining = 123 Accumulated Delay = 0 1274 ; if { channel @ 0 } start 1275 ; Alias variable for select channel @ 0 1276 0039 delay__channel__428select0 equ delay__channel+0 1277 0039 delay__channel__428select0__byte equ delay__channel+0 1278 0000 delay__channel__428select0__bit equ 0 1279 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1280 1cd 1839 btfsc delay__channel__428select0__byte,delay__channel__428select0__bit 1281 ; if { channel @ 0 } body start 1282 ; Uniform delay remaining = 123 Accumulated Delay = 0 1283 ; mask @ 1 := 1 1284 ; Select mask @ 1 1285 003f delay__mask__429select0 equ delay__mask+0 1286 003f delay__mask__429select0__byte equ delay__mask+0 1287 0001 delay__mask__429select0__bit equ 1 1288 1ce 14bf bsf delay__mask__429select0__byte,delay__mask__429select0__bit 1289 ; Uniform delay remaining = 122 Accumulated Delay = 1 1290 ; Uniform delay remaining = 122 Accumulated Delay = 1 1291 ; if { channel @ 0 } body end 1292 1cf 1c39 btfss delay__channel__428select0__byte,delay__channel__428select0__bit 1293 ; else body start 1294 ; Uniform delay remaining = 123 Accumulated Delay = 0 1295 ; mask @ 0 := 1 1296 ; Select mask @ 0 1297 003f delay__mask__431select0 equ delay__mask+0 1298 003f delay__mask__431select0__byte equ delay__mask+0 1299 0000 delay__mask__431select0__bit equ 0 1300 1d0 143f bsf delay__mask__431select0__byte,delay__mask__431select0__bit 1301 ; Uniform delay remaining = 122 Accumulated Delay = 1 1302 ; Uniform delay remaining = 122 Accumulated Delay = 1 1303 ; else body end 1304 ; if exp=` channel @ 0 ' single true and false skip delay=4 1305 ; Other expression=`{ channel @ 0 }' delay=4 1306 ; if { channel @ 0 } end 1307 ; Uniform delay remaining = 119 Accumulated Delay = 4 1308 ; Uniform delay remaining = 119 Accumulated Delay = 4 1309 ; else body end 1310 ; Delay 1 cycles 1311 1d1 0000 nop 1312 ; if exp=` channel @ 1 ' total delay=8 1313 ; if exp=` channel @ 1 ' generic 1314 label421__1end: 1315 ; Other expression=`{ channel @ 1 }' delay=8 1316 ; if { channel @ 1 } end 1317 ; Uniform delay remaining = 115 Accumulated Delay = 10 1318 ; Delaying 60 uS is way longer than necessary for the conversion 1319 ; Uniform delay remaining = 115 Accumulated Delay = 10 1320 ; to complete . 1321 ; Uniform delay remaining = 115 Accumulated Delay = 10 1322 ; nop 60 1323 ; Delay 60 cycles 1324 1d2 3013 movlw 19 1325 1d3 00c1 movwf delay__436byte1 1326 delay__436delay0: 1327 1d4 0bc1 decfsz delay__436byte1,f 1328 1d5 29d4 goto delay__436delay0 1329 1d6 0000 nop 1330 1d7 0000 nop 1331 ; Uniform delay remaining = 55 Accumulated Delay = 70 1332 ; result := addres 1333 1d8 081e movf addres,w 1334 1d9 00c0 movwf delay__result 1335 ; Uniform delay remaining = 53 Accumulated Delay = 72 1336 ; analogs ~~ {{ channel }} := result 1337 1da 0840 movf delay__result,w 1338 1db 00c1 movwf delay__438byte0 1339 1dc 3020 movlw LOW analogs 1340 1dd 0739 addwf delay__channel,w 1341 1de 0084 movwf fsr___register 1342 1df 0841 movf delay__438byte0,w 1343 1e0 0080 movwf indf___register 1344 ; Uniform delay remaining = 46 Accumulated Delay = 79 1345 ; if { result <= thresholds_low ~~ {{ channel }} } start 1346 1e1 3024 movlw LOW thresholds_low 1347 1e2 0739 addwf delay__channel,w 1348 1e3 0084 movwf fsr___register 1349 1e4 0800 movf indf___register,w 1350 1e5 0240 subwf delay__result,w 1351 1e6 1903 btfsc z___byte,z___bit 1352 1e7 1003 bcf c___byte,c___bit 1353 ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 1354 1e8 1c03 btfss c___byte,c___bit 1355 1e9 29ed goto label439__0true 1356 label439__0false: 1357 ; Delay 2 cycles 1358 1ea 0000 nop 1359 1eb 0000 nop 1360 1ec 29f0 goto label439__0end 1361 label439__0true: 1362 ; if { result <= thresholds_low ~~ {{ channel }} } body start 1363 ; Uniform delay remaining = 46 Accumulated Delay = 0 1364 ; inputs := inputs & {{ mask ^ io_mask }} 1365 1ed 300f movlw 15 1366 1ee 063f xorwf delay__mask,w 1367 1ef 05ac andwf inputs,f 1368 ; Uniform delay remaining = 43 Accumulated Delay = 3 1369 ; Uniform delay remaining = 43 Accumulated Delay = 3 1370 ; if { result <= thresholds_low ~~ {{ channel }} } body end 1371 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 1372 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic 1373 label439__0end: 1374 ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 1375 ; if { result <= thresholds_low ~~ {{ channel }} } end 1376 ; Uniform delay remaining = 33 Accumulated Delay = 92 1377 ; if { result >= thresholds_high ~~ {{ channel }} } start 1378 1f0 3028 movlw LOW thresholds_high 1379 1f1 0739 addwf delay__channel,w 1380 1f2 0084 movwf fsr___register 1381 1f3 0800 movf indf___register,w 1382 1f4 0240 subwf delay__result,w 1383 ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 1384 1f5 1803 btfsc c___byte,c___bit 1385 1f6 29f9 goto label442__0true 1386 label442__0false: 1387 ; Delay 1 cycles 1388 1f7 0000 nop 1389 1f8 29fb goto label442__0end 1390 label442__0true: 1391 ; if { result >= thresholds_high ~~ {{ channel }} } body start 1392 ; Uniform delay remaining = 33 Accumulated Delay = 0 1393 ; inputs := inputs | mask 1394 1f9 083f movf delay__mask,w 1395 1fa 04ac iorwf inputs,f 1396 ; Uniform delay remaining = 31 Accumulated Delay = 2 1397 ; Uniform delay remaining = 31 Accumulated Delay = 2 1398 ; if { result >= thresholds_high ~~ {{ channel }} } body end 1399 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 1400 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic 1401 label442__0end: 1402 ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 1403 ; if { result >= thresholds_high ~~ {{ channel }} } end 1404 ; Uniform delay remaining = 23 Accumulated Delay = 102 1405 ; inputs := inputs & io_mask 1406 1fb 300f movlw 15 1407 1fc 05ac andwf inputs,f 1408 ; Uniform delay remaining = 21 Accumulated Delay = 104 1409 ; Uniform delay remaining = 21 Accumulated Delay = 104 1410 ; else body end 1411 ; if exp=` counter @ 0 ' total delay=107 1412 ; if exp=` counter @ 0 ' generic 1413 label396__1end: 1414 ; Other expression=`{ counter @ 0 }' delay=107 1415 ; if { counter @ 0 } end 1416 ; Uniform delay remaining = 18 Accumulated Delay = 113 1417 ; Uniform delay remaining = 18 Accumulated Delay = 113 1418 ; Soak up remaining 18 cycles 1419 ; Delay 18 cycles 1420 1fd 3005 movlw 5 1421 1fe 00c1 movwf delay__374byte1 1422 delay__374delay0: 1423 1ff 0bc1 decfsz delay__374byte1,f 1424 200 29ff goto delay__374delay0 1425 201 0000 nop 1426 202 0000 nop 1427 ; procedure delay end 1428 203 3400 retlw 0 1429 ; optimize 1 1430 1431 ; procedure get_byte start 1432 get_byte: 1433 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1434 0042 get_byte__variables__base equ global__variables__bank0+34 1435 0042 get_byte__bytes__base equ get_byte__variables__base+0 1436 0045 get_byte__bits__base equ get_byte__variables__base+3 1437 0003 get_byte__total__bytes equ 3 1438 ; arguments_none 1439 0042 get_byte__0return__byte equ get_byte__bytes__base+0 1440 ; Wait for a character and return it . 1441 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 1442 ; way the next call to get_byte < > will sychronize on the start 1443 ; bit instead of possibly starting a little later . 1444 0043 get_byte__count equ get_byte__bytes__base+1 1445 0044 get_byte__char equ get_byte__bytes__base+2 1446 ; Wait for start bit : 1447 ; receiving := 1 1448 204 15c9 bsf receiving__byte,receiving__bit 1449 ; `while serial_in ...' start 1450 get_byte__465while__continue: 1451 ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 1452 205 1d85 btfss serial_in__byte,serial_in__bit 1453 206 2a09 goto get_byte__465while__break 1454 ; call delay {{ }} 1455 207 2186 call delay 1456 208 2a05 goto get_byte__465while__continue 1457 ; if exp=`serial_in' false goto 1458 ; Other expression=`serial_in' delay=-1 1459 get_byte__465while__break: 1460 ; `while serial_in ...' end 1461 ; Clear interrupts and interrupt pending : 1462 ; 1 cycle : 1463 ; serial_out := 1 1464 209 1685 bsf serial_out__byte,serial_out__bit 1465 ; Skip over start bit : 1466 ; call delay {{ }} 1467 20a 2186 call delay 1468 ; call delay {{ }} 1469 20b 2186 call delay 1470 ; call delay {{ }} 1471 20c 2186 call delay 1472 ; Sample in the middle third of each data bit : 1473 ; 1 cycle : 1474 ; char := 0 1475 20d 01c4 clrf get_byte__char 1476 ; 2 cycles to set up loop : 1477 ; 1 + 1 + 2 = 4 1478 ; nop extra_instructions_per_bit - 4 1479 ; Delay 5 cycles 1480 20e 0000 nop 1481 20f 0000 nop 1482 210 0000 nop 1483 211 0000 nop 1484 212 0000 nop 1485 ; `count_down count 8 ...' start 1486 213 3008 movlw 8 1487 214 00c3 movwf get_byte__count 1488 get_byte__484_loop: 1489 ; call delay {{ }} 1490 215 2186 call delay 1491 ; 2 cycles : 1492 ; char := char >> 1 1493 216 1003 bcf c___byte,c___bit 1494 217 0cc4 rrf get_byte__char,f 1495 ; 2 cycles : 1496 ; if { serial_in } start 1497 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1498 218 1985 btfsc serial_in__byte,serial_in__bit 1499 ; if { serial_in } body start 1500 ; char @ 7 := 1 1501 ; Select char @ 7 1502 0044 get_byte__char__490select0 equ get_byte__char+0 1503 0044 get_byte__char__490select0__byte equ get_byte__char+0 1504 0007 get_byte__char__490select0__bit equ 7 1505 219 17c4 bsf get_byte__char__490select0__byte,get_byte__char__490select0__bit 1506 ; if { serial_in } body end 1507 ; if exp=`serial_in' false skip delay=2 1508 ; Other expression=`{ serial_in }' delay=2 1509 ; if { serial_in } end 1510 ; call delay {{ }} 1511 21a 2186 call delay 1512 ; call delay {{ }} 1513 21b 2186 call delay 1514 ; 3 cycles at end of loop : 1515 ; 2 + 2 + 3 = 7 1516 ; nop extra_instructions_per_bit - 7 1517 ; Delay 2 cycles 1518 21c 0000 nop 1519 21d 0000 nop 1520 21e 0bc3 decfsz get_byte__count,f 1521 21f 2a15 goto get_byte__484_loop 1522 get_byte__484_done: 1523 ; `count_down count 8 ...' end 1524 ; Skip over 2 / 3 ' s of stop bit : 1525 ; call delay {{ }} 1526 220 2186 call delay 1527 ; call delay {{ }} 1528 221 2186 call delay 1529 ; return char 1530 222 0844 movf get_byte__char,w 1531 223 00c2 movwf get_byte__0return__byte 1532 224 3400 retlw 0 1533 ; procedure get_byte end 1534 1535 ; procedure send_byte start 1536 send_byte: 1537 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1538 0045 send_byte__variables__base equ global__variables__bank0+37 1539 0045 send_byte__bytes__base equ send_byte__variables__base+0 1540 0047 send_byte__bits__base equ send_byte__variables__base+2 1541 0002 send_byte__total__bytes equ 2 1542 0045 send_byte__char equ send_byte__bytes__base+0 1543 ; Send < char > to < tx > : 1544 0046 send_byte__count equ send_byte__bytes__base+1 1545 ; < receiving > will be 1 if the last get / put routine was a get . 1546 ; Before we start transmitting a response back , we want to ensure 1547 ; that there has been enough time to turn the line line around . 1548 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 1549 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 1550 ; for good measure . Technically , the second call to delay < > 1551 ; is not really needed . 1552 ; if { receiving } start 1553 ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 1554 225 1dc9 btfss receiving__byte,receiving__bit 1555 226 2a2a goto label521__0end 1556 ; if { receiving } body start 1557 ; receiving := 0 1558 227 11c9 bcf receiving__byte,receiving__bit 1559 ; call delay {{ }} 1560 228 2186 call delay 1561 ; call delay {{ }} 1562 229 2186 call delay 1563 ; if { receiving } body end 1564 label521__0end: 1565 ; if exp=`receiving' empty false 1566 ; Other expression=`{ receiving }' delay=-1 1567 ; if { receiving } end 1568 ; Send the start bit : 1569 ; 1 cycle : 1570 ; serial_out := 0 1571 22a 1285 bcf serial_out__byte,serial_out__bit 1572 ; call delay {{ }} 1573 22b 2186 call delay 1574 ; call delay {{ }} 1575 22c 2186 call delay 1576 ; call delay {{ }} 1577 22d 2186 call delay 1578 ; 2 cycles for loop setup : 1579 ; 1 + 2 = 3 1580 ; nop extra_instructions_per_bit - 3 1581 ; Delay 6 cycles 1582 22e 0000 nop 1583 22f 0000 nop 1584 230 0000 nop 1585 231 0000 nop 1586 232 0000 nop 1587 233 0000 nop 1588 ; Send the data : 1589 ; `count_down count 8 ...' start 1590 234 3008 movlw 8 1591 235 00c6 movwf send_byte__count 1592 send_byte__538_loop: 1593 ; 4 cycles : 1594 ; serial_out := char @ 0 1595 ; Alias variable for select char @ 0 1596 0045 send_byte__char__540select0 equ send_byte__char+0 1597 0045 send_byte__char__540select0__byte equ send_byte__char+0 1598 0000 send_byte__char__540select0__bit equ 0 1599 236 1c45 btfss send_byte__char__540select0__byte,send_byte__char__540select0__bit 1600 237 1285 bcf serial_out__byte,serial_out__bit 1601 238 1845 btfsc send_byte__char__540select0__byte,send_byte__char__540select0__bit 1602 239 1685 bsf serial_out__byte,serial_out__bit 1603 ; 2 cycles : 1604 ; char := char >> 1 1605 23a 1003 bcf c___byte,c___bit 1606 23b 0cc5 rrf send_byte__char,f 1607 ; call delay {{ }} 1608 23c 2186 call delay 1609 ; call delay {{ }} 1610 23d 2186 call delay 1611 ; call delay {{ }} 1612 23e 2186 call delay 1613 ; 3 cycles at end of loop : 1614 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 1615 23f 0bc6 decfsz send_byte__count,f 1616 240 2a36 goto send_byte__538_loop 1617 send_byte__538_done: 1618 ; `count_down count 8 ...' end 1619 ; Send the stop bit : 1620 ; 1 cycle to close out previous loop : 1621 ; nop 1 1622 ; Delay 1 cycles 1623 241 0000 nop 1624 ; 1 cycle : 1625 ; serial_out := 1 1626 242 1685 bsf serial_out__byte,serial_out__bit 1627 ; call delay {{ }} 1628 243 2186 call delay 1629 ; call delay {{ }} 1630 244 2186 call delay 1631 ; call delay {{ }} 1632 245 2186 call delay 1633 ; 2 cycles for call / return : 1634 ; 2 cycles for argument : 1635 ; 1 + 2 + 2 = 5 1636 ; nop extra_instructions_per_bit - 5 1637 ; Delay 4 cycles 1638 246 0000 nop 1639 247 0000 nop 1640 248 0000 nop 1641 249 0000 nop 1642 ; procedure send_byte end 1643 24a 3400 retlw 0 1644 1645 ; procedure reset start 1646 reset: 1647 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1648 0047 reset__variables__base equ global__variables__bank0+39 1649 0047 reset__bytes__base equ reset__variables__base+0 1650 0049 reset__bits__base equ reset__variables__base+2 1651 0002 reset__total__bytes equ 2 1652 0048 reset__582byte0 equ reset__bytes__base+1 1653 0048 reset__583byte0 equ reset__bytes__base+1 1654 ; arguments_none 1655 ; This procedure will initialize all of the registers : 1656 0047 reset__index equ reset__bytes__base+0 1657 ; inputs := 0 1658 24b 01ac clrf inputs 1659 ; high := 0 1660 24c 01b1 clrf high 1661 ; low := 0 1662 24d 01b2 clrf low 1663 ; raising := 0 1664 24e 01b3 clrf raising 1665 ; falling := 0 1666 24f 01b0 clrf falling 1667 ; complement := 0 1668 250 01ad clrf complement 1669 ; interrupt_enable := 0 1670 251 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 1671 ; interrupt_pending := 0 1672 252 1149 bcf interrupt_pending__byte,interrupt_pending__bit 1673 ; index := 0 1674 253 01c7 clrf reset__index 1675 ; `while index < 4 ...' start 1676 reset__581while__continue: 1677 254 3004 movlw 4 1678 255 0247 subwf reset__index,w 1679 ; expression=` index < 4 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 1680 256 1803 btfsc c___byte,c___bit 1681 257 2a68 goto reset__581while__break 1682 ; thresholds_high ~~ {{ index }} := 0xc0 1683 258 30c0 movlw 192 1684 259 00c8 movwf reset__582byte0 1685 25a 3028 movlw LOW thresholds_high 1686 25b 0747 addwf reset__index,w 1687 25c 0084 movwf fsr___register 1688 25d 0848 movf reset__582byte0,w 1689 25e 0080 movwf indf___register 1690 ; thresholds_low ~~ {{ index }} := 0x40 1691 25f 3040 movlw 64 1692 260 00c8 movwf reset__583byte0 1693 261 3024 movlw LOW thresholds_low 1694 262 0747 addwf reset__index,w 1695 263 0084 movwf fsr___register 1696 264 0848 movf reset__583byte0,w 1697 265 0080 movwf indf___register 1698 ; index := index + 1 1699 266 0ac7 incf reset__index,f 1700 267 2a54 goto reset__581while__continue 1701 ; if exp=` index < 4 ' false goto 1702 ; Other expression=` index < 4 ' delay=-1 1703 reset__581while__break: 1704 ; `while index < 4 ...' end 1705 ; glitch := 0 1706 268 01ae clrf glitch 1707 ; id_index := 0 1708 269 01af clrf id_index 1709 ; serial_out := 1 1710 26a 1685 bsf serial_out__byte,serial_out__bit 1711 ; vref_mode := 0 1712 26b 1049 bcf vref_mode__byte,vref_mode__bit 1713 ; addcon1 := 0 1714 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 1715 26c 1683 bsf rp0___byte,rp0___bit 1716 ; Register bank is now 1 1717 26d 019f clrf addcon1 1718 ; procedure reset end 1719 ; Switch from register bank 1 to register bank 0 1720 26e 1283 bcf rp0___byte,rp0___bit 1721 ; Register bank is now 0 1722 26f 3400 retlw 0 1723 1724 ; Register bank 0 used 41 bytes of 96 available bytes 1725 ; Register bank 1 used 0 bytes of 32 available bytes 1726 1727 end