1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0049 global__bit__variables__bank0 equ 73 5 00a0 global__bit__variables__bank1 equ 160 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 0003 rp0___byte equ 3 13 0005 rp0___bit equ 5 14 0003 rp1___byte equ 3 15 0006 rp1___bit equ 6 16 0003 irp___byte equ 3 17 0007 irp___bit equ 7 18 0085 trisa___register equ 0x85 19 0086 trisb___register equ 0x86 20 0004 fsr___register equ 4 21 000a pclath___register equ 10 22 org 0 23 start: 24 000 0000 nop 25 001 0000 nop 26 002 0000 nop 27 003 2805 goto skip___interrupt 28 interrupt___vector: 29 004 0009 retfie 30 skip___interrupt: 31 ; Use oscillator calibration stored in high memory 32 005 27ff call 2047 33 ; Switch from register bank 0 to register bank 1 (which contains 143) 34 006 1683 bsf rp0___byte,rp0___bit 35 ; Register bank is now 1 36 007 008f movwf 143 37 ; Initialize A/D system to allow digital I/O 38 008 3007 movlw 7 39 009 009f movwf 159 40 ; Switch from register bank 1 to register bank 0 (which contains 31) 41 00a 1283 bcf rp0___byte,rp0___bit 42 ; Register bank is now 0 43 00b 019f clrf 31 44 ; Initialize TRIS registers 45 00c 30df movlw 223 46 00d 0065 tris 5 47 00e 018a clrf pclath___register 48 00f 2846 goto main 49 ; comment ############################################################################# 50 ; comment {} 51 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 52 ; comment {All rights reserved .} 53 ; comment {} 54 ; comment {Permission to use , copy , modify , distribute , and sell this software} 55 ; comment {for any purpose is hereby granted without fee provided that the above} 56 ; comment {copyright notice and this permission are retained . The author makes} 57 ; comment {no representations about the suitability of this software for any purpose .} 58 ; comment {It is provided { as is } without express or implied warranty .} 59 ; comment {} 60 ; comment {This is the code that implements the AnalogIn4 RoboBrick . Basically} 61 ; comment {it just waits for commands that come in at 2400 baud and responds} 62 ; comment {to them . See} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / robobricks / analogin4 / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment ############################################################################# 69 ; processor pic12ce674 cp = off pwrte = off wdte = on mclre = off fosc = intrc_no_clock 70 ; 16252=0x3f7c 8199=0x2007 71 __config 16252 72 2007 configuration___address equ 8199 73 ; comment {define processor constants} 74 ; constant clock_rate 4000000 75 3d0900 clock_rate equ 4000000 76 ; constant clocks_per_instruction 4 77 0004 clocks_per_instruction equ 4 78 ; constant instruction_rate clock_rate / clocks_per_instruction 79 f4240 instruction_rate equ 1000000 80 ; comment {define serial communication control constants} 81 ; constant baud_rate 2400 82 0960 baud_rate equ 2400 83 ; constant instructions_per_bit instruction_rate / baud_rate 84 01a0 instructions_per_bit equ 416 85 ; constant delays_per_bit 3 86 0003 delays_per_bit equ 3 87 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 88 008a instructions_per_delay equ 138 89 ; constant extra_instructions_per_bit 9 90 0009 extra_instructions_per_bit equ 9 91 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 92 0003 extra_instructions_per_delay equ 3 93 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 94 0087 delay_instructions equ 135 95 ; comment {Oscillator Mask :} 96 008f osccal equ 143 97 ; constant osccal_unit 0x10 98 0010 osccal_unit equ 16 99 ; comment {Analog to digital conversion result register :} 100 001e addres equ 30 101 ; comment {Analog to digital conversion register 0 :} 102 001f addcon0 equ 31 103 ; bind adon addcon0 @ 0 104 001f adon equ addcon0+0 105 001f adon__byte equ addcon0+0 106 0000 adon__bit equ 0 107 ; bind go_done addcon0 @ 2 108 001f go_done equ addcon0+0 109 001f go_done__byte equ addcon0+0 110 0002 go_done__bit equ 2 111 ; bind chs0 addcon0 @ 3 112 001f chs0 equ addcon0+0 113 001f chs0__byte equ addcon0+0 114 0003 chs0__bit equ 3 115 ; bind chs1 addcon0 @ 4 116 001f chs1 equ addcon0+0 117 001f chs1__byte equ addcon0+0 118 0004 chs1__bit equ 4 119 ; bind adcs0 addcon0 @ 6 120 001f adcs0 equ addcon0+0 121 001f adcs0__byte equ addcon0+0 122 0006 adcs0__bit equ 6 123 ; bind adcs1 addcon0 @ 7 124 001f adcs1 equ addcon0+0 125 001f adcs1__byte equ addcon0+0 126 0007 adcs1__bit equ 7 127 ; comment {Interrupt Control Register :} 128 000b intcon equ 11 129 ; bind gpif intcon @ 0 130 000b gpif equ intcon+0 131 000b gpif__byte equ intcon+0 132 0000 gpif__bit equ 0 133 ; bind intf intcon @ 1 134 000b intf equ intcon+0 135 000b intf__byte equ intcon+0 136 0001 intf__bit equ 1 137 ; bind toif intcon @ 2 138 000b toif equ intcon+0 139 000b toif__byte equ intcon+0 140 0002 toif__bit equ 2 141 ; bind gpie intcon @ 3 142 000b gpie equ intcon+0 143 000b gpie__byte equ intcon+0 144 0003 gpie__bit equ 3 145 ; bind inte intcon @ 4 146 000b inte equ intcon+0 147 000b inte__byte equ intcon+0 148 0004 inte__bit equ 4 149 ; bind toie intcon @ 5 150 000b toie equ intcon+0 151 000b toie__byte equ intcon+0 152 0005 toie__bit equ 5 153 ; bind peie intcon @ 6 154 000b peie equ intcon+0 155 000b peie__byte equ intcon+0 156 0006 peie__bit equ 6 157 ; bind gie intcon @ 7 158 000b gie equ intcon+0 159 000b gie__byte equ intcon+0 160 0007 gie__bit equ 7 161 000c pir1 equ 12 162 ; bind adif pir1 @ 6 163 000c adif equ pir1+0 164 000c adif__byte equ pir1+0 165 0006 adif__bit equ 6 166 008c pie1 equ 140 167 ; bind adie pie1 @ 6 168 008c adie equ pie1+0 169 008c adie__byte equ pie1+0 170 0006 adie__bit equ 6 171 ; comment {Analog to digital conversion register 1 :} 172 009f addcon1 equ 159 173 ; bind pcfg0 addcon1 @ 0 174 009f pcfg0 equ addcon1+0 175 009f pcfg0__byte equ addcon1+0 176 0000 pcfg0__bit equ 0 177 ; bind pcfg1 addcon1 @ 1 178 009f pcfg1 equ addcon1+0 179 009f pcfg1__byte equ addcon1+0 180 0001 pcfg1__bit equ 1 181 ; bind pcfg2 addcon1 @ 2 182 009f pcfg2 equ addcon1+0 183 009f pcfg2__byte equ addcon1+0 184 0002 pcfg2__bit equ 2 185 ; constant ain_bit0 0 186 0000 ain_bit0 equ 0 187 ; constant ain_bit1 1 188 0001 ain_bit1 equ 1 189 ; constant ain_bit2 2 190 0002 ain_bit2 equ 2 191 ; constant serial_in_bit 3 192 0003 serial_in_bit equ 3 193 ; constant ain_bit3 4 194 0004 ain_bit3 equ 4 195 ; constant serial_out_bit 5 196 0005 serial_out_bit equ 5 197 ; constant ain_mask0 {{ 1 << ain_bit0 }} 198 0001 ain_mask0 equ 1 199 ; constant ain_mask1 {{ 1 << ain_bit1 }} 200 0002 ain_mask1 equ 2 201 ; constant ain_mask2 {{ 1 << ain_bit2 }} 202 0004 ain_mask2 equ 4 203 ; constant ain_mask3 {{ 1 << ain_bit3 }} 204 0010 ain_mask3 equ 16 205 ; constant serial_in_mask {{ 1 << serial_in_bit }} 206 0008 serial_in_mask equ 8 207 ; constant serial_out_mask {{ 1 << serial_out_bit }} 208 0020 serial_out_mask equ 32 209 ; constant io_mask 0xf 210 000f io_mask equ 15 211 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} 212 0017 ain_mask equ 23 213 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} 214 0028 serial_mask equ 40 215 ; comment {define port bit assignments} 216 0005 porta equ 5 217 0005 ain0__byte equ 5 218 0000 ain0__bit equ 0 219 0005 ain1__byte equ 5 220 0001 ain1__bit equ 1 221 0005 ain2__byte equ 5 222 0002 ain2__bit equ 2 223 0005 ain3__byte equ 5 224 0004 ain3__bit equ 4 225 0005 serial_in__byte equ 5 226 0003 serial_in__bit equ 3 227 0005 serial_out__byte equ 5 228 0005 serial_out__bit equ 5 229 ; constant analogs_size 4 230 0004 analogs_size equ 4 231 ; string_constants Start 232 string___fetch: 233 010 0082 movwf pcl___register 234 ; id = 1 , 0 , 12 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 10 , 0s'AnalogIn4B' , 15 , 0s'Gramlich&Benson' 235 0000 id___string equ 0 236 id: 237 011 0782 addwf pcl___register,f 238 ; Length = 51 239 012 3433 retlw 51 240 ; 1 241 013 3401 retlw 1 242 ; 0 243 014 3400 retlw 0 244 ; 12 245 015 340c retlw 12 246 ; 1 247 016 3401 retlw 1 248 ; 0 249 017 3400 retlw 0 250 ; 0 251 018 3400 retlw 0 252 ; 0 253 019 3400 retlw 0 254 ; 0 255 01a 3400 retlw 0 256 ; 0r'16' 257 01b 34ca retlw 202 ; random number 258 01c 3478 retlw 120 ; random number 259 01d 3459 retlw 89 ; random number 260 01e 3445 retlw 69 ; random number 261 01f 3479 retlw 121 ; random number 262 020 34b0 retlw 176 ; random number 263 021 34e8 retlw 232 ; random number 264 022 3491 retlw 145 ; random number 265 023 34eb retlw 235 ; random number 266 024 34c9 retlw 201 ; random number 267 025 347c retlw 124 ; random number 268 026 344b retlw 75 ; random number 269 027 34ce retlw 206 ; random number 270 028 349e retlw 158 ; random number 271 029 34ba retlw 186 ; random number 272 02a 349d retlw 157 ; random number 273 ; 10 274 02b 340a retlw 10 275 ; `AnalogIn4B' 276 02c 3441 retlw 65 277 02d 346e retlw 110 278 02e 3461 retlw 97 279 02f 346c retlw 108 280 030 346f retlw 111 281 031 3467 retlw 103 282 032 3449 retlw 73 283 033 346e retlw 110 284 034 3434 retlw 52 285 035 3442 retlw 66 286 ; 15 287 036 340f retlw 15 288 ; `Gramlich&Benson' 289 037 3447 retlw 71 290 038 3472 retlw 114 291 039 3461 retlw 97 292 03a 346d retlw 109 293 03b 346c retlw 108 294 03c 3469 retlw 105 295 03d 3463 retlw 99 296 03e 3468 retlw 104 297 03f 3426 retlw 38 298 040 3442 retlw 66 299 041 3465 retlw 101 300 042 346e retlw 110 301 043 3473 retlw 115 302 044 346f retlw 111 303 045 346e retlw 110 304 ; string__constants End 305 ; bank 0 306 ; Default register bank is now 0 307 0020 analogs equ global__variables__bank0+0 308 0024 thresholds_low equ global__variables__bank0+4 309 0028 thresholds_high equ global__variables__bank0+8 310 002c inputs equ global__variables__bank0+12 311 002d complement equ global__variables__bank0+13 312 002e glitch equ global__variables__bank0+14 313 002f id_index equ global__variables__bank0+15 314 0049 vref_mode equ global__bit__variables__bank0+0 315 0049 vref_mode__byte equ global__bit__variables__bank0+0 316 0000 vref_mode__bit equ 0 317 ; comment {Interrupt masks :} 318 0049 interrupt_enable equ global__bit__variables__bank0+0 319 0049 interrupt_enable__byte equ global__bit__variables__bank0+0 320 0001 interrupt_enable__bit equ 1 321 0049 interrupt_pending equ global__bit__variables__bank0+0 322 0049 interrupt_pending__byte equ global__bit__variables__bank0+0 323 0002 interrupt_pending__bit equ 2 324 0049 receiving equ global__bit__variables__bank0+0 325 0049 receiving__byte equ global__bit__variables__bank0+0 326 0003 receiving__bit equ 3 327 0030 falling equ global__variables__bank0+16 328 0031 high equ global__variables__bank0+17 329 0032 low equ global__variables__bank0+18 330 0033 raising equ global__variables__bank0+19 331 332 ; procedure main start 333 main: 334 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 335 0034 main__variables__base equ global__variables__bank0+20 336 0034 main__bytes__base equ main__variables__base+0 337 0038 main__bits__base equ main__variables__base+4 338 0005 main__total__bytes equ 5 339 0037 main__229byte0 equ main__bytes__base+3 340 0037 main__293byte0 equ main__bytes__base+3 341 0037 main__244byte0 equ main__bytes__base+3 342 0037 main__240byte0 equ main__bytes__base+3 343 0037 main__158byte0 equ main__bytes__base+3 344 0037 main__155byte0 equ main__bytes__base+3 345 0037 main__286byte0 equ main__bytes__base+3 346 ; arguments_none 347 0034 main__bit equ main__bytes__base+0 348 0035 main__command equ main__bytes__base+1 349 0036 main__temporary equ main__bytes__base+2 350 ; Initialize the A / D module : 351 ; Select all 4 inputs as A / D : 352 ; addcon1 := 0 353 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 354 046 1683 bsf rp0___byte,rp0___bit 355 ; Register bank is now 1 356 047 019f clrf addcon1 357 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : 358 ; addcon0 := 0x41 359 048 3041 movlw 65 360 ; Switch from register bank 1 to register bank 0 (which contains addcon0) 361 049 1283 bcf rp0___byte,rp0___bit 362 ; Register bank is now 0 363 04a 009f movwf addcon0 364 ; adif := 0 365 04b 130c bcf adif__byte,adif__bit 366 ; adie := 0 367 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) 368 04c 1683 bsf rp0___byte,rp0___bit 369 ; Register bank is now 1 370 04d 130c bcf adie__byte,adie__bit 371 ; gie := 0 372 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) 373 04e 1283 bcf rp0___byte,rp0___bit 374 ; Register bank is now 0 375 04f 138b bcf gie__byte,gie__bit 376 ; call reset {{ }} 377 050 224b call reset 378 ; Set the direction : 379 ; loop_forever ... start 380 main__150loop__forever: 381 ; Wait for a command : 382 ; command := get_byte {{ }} 383 051 2204 call get_byte 384 052 0842 movf get_byte__0return__byte,w 385 053 00b5 movwf main__command 386 ; Dispatch on command : 387 ; switch { command >> 6 } 388 054 3000 movlw HIGH switch__155block_start 389 055 008a movwf pclath___register 390 056 0e35 swapf main__command,w 391 057 00b7 movwf main__155byte0 392 058 0cb7 rrf main__155byte0,f 393 059 0c37 rrf main__155byte0,w 394 05a 3903 andlw 3 395 ; case 0 396 ; case 1 397 ; case 2 398 ; case 3 399 switch__155block_start: 400 05b 0782 addwf pcl___register,f 401 05c 2860 goto switch__155block156 402 05d 28f7 goto switch__155block257 403 05e 2912 goto switch__155block281 404 05f 2913 goto switch__155block284 405 switch__155block_end: 406 ; switch_check 155 switch__155block_start switch__155block_end 407 switch__155block156: 408 ; Command = 00 xx xxxx : 409 ; switch { command >> 3 } 410 060 3000 movlw HIGH switch__158block_start 411 061 008a movwf pclath___register 412 062 0c35 rrf main__command,w 413 063 00b7 movwf main__158byte0 414 064 0cb7 rrf main__158byte0,f 415 065 0c37 rrf main__158byte0,w 416 066 391f andlw 31 417 ; case 0 418 ; case 1 419 ; case 2 3 420 ; case 4 5 421 switch__158block_start: 422 067 0782 addwf pcl___register,f 423 068 2870 goto switch__158block159 424 069 2890 goto switch__158block183 425 06a 28c4 goto switch__158block226 426 06b 28c4 goto switch__158block226 427 06c 28f2 goto switch__158block248 428 06d 28f2 goto switch__158block248 429 06e 28f6 goto switch__158default252 430 06f 28f6 goto switch__158default252 431 switch__158block_end: 432 ; switch_check 158 switch__158block_start switch__158block_end 433 switch__158block159: 434 ; Command = 0000 0 xxx : 435 ; switch { command & 7 } 436 070 3000 movlw HIGH switch__161block_start 437 071 008a movwf pclath___register 438 072 3007 movlw 7 439 073 0535 andwf main__command,w 440 ; case 0 1 2 3 441 ; case 4 442 ; case 5 443 ; case 6 444 switch__161block_start: 445 074 0782 addwf pcl___register,f 446 075 287d goto switch__161block162 447 076 287d goto switch__161block162 448 077 287d goto switch__161block162 449 078 287d goto switch__161block162 450 079 2884 goto switch__161block166 451 07a 2889 goto switch__161block170 452 07b 288d goto switch__161block174 453 07c 288f goto switch__161default178 454 switch__161block_end: 455 ; switch_check 161 switch__161block_start switch__161block_end 456 switch__161block162: 457 ; Read Pin < Command = 0000 00 bb > : 458 ; call send_byte {{ analogs ~~ {{ command }} }} 459 07d 3020 movlw LOW analogs 460 07e 0735 addwf main__command,w 461 07f 0084 movwf fsr___register 462 080 0800 movf indf___register,w 463 081 00c5 movwf send_byte__char 464 082 2225 call send_byte 465 083 288f goto switch__161end 466 switch__161block166: 467 ; Read Binary Values < Command = 0000 0100 > : 468 ; call send_byte {{ inputs ^ complement }} 469 084 082c movf inputs,w 470 085 062d xorwf complement,w 471 086 00c5 movwf send_byte__char 472 087 2225 call send_byte 473 088 288f goto switch__161end 474 switch__161block170: 475 ; Read Raw Binary < Command = 0000 0101 > : 476 ; call send_byte {{ inputs }} 477 089 082c movf inputs,w 478 08a 00c5 movwf send_byte__char 479 08b 2225 call send_byte 480 08c 288f goto switch__161end 481 switch__161block174: 482 ; Reset < Command = 0000 0110 > : 483 ; call reset {{ }} 484 08d 224b call reset 485 08e 288f goto switch__161end 486 switch__161default178: 487 ; Undefined command : 488 switch__161end: 489 08f 28f6 goto switch__158end 490 switch__158block183: 491 ; Command = 0000 1 xxx : 492 ; switch { command & 7 } 493 090 3000 movlw HIGH switch__185block_start 494 091 008a movwf pclath___register 495 092 3007 movlw 7 496 093 0535 andwf main__command,w 497 ; case 0 498 ; case 1 499 ; case 2 500 ; case 3 501 ; case 4 502 ; case 5 503 ; case 6 7 504 switch__185block_start: 505 094 0782 addwf pcl___register,f 506 095 289d goto switch__185block186 507 096 28a1 goto switch__185block190 508 097 28a5 goto switch__185block194 509 098 28a9 goto switch__185block198 510 099 28ad goto switch__185block202 511 09a 28b1 goto switch__185block206 512 09b 28b8 goto switch__185block214 513 09c 28b8 goto switch__185block214 514 switch__185block_end: 515 ; switch_check 185 switch__185block_start switch__185block_end 516 switch__185block186: 517 ; Read Complement Mask < Command = 0000 1000 > : 518 ; call send_byte {{ complement }} 519 09d 082d movf complement,w 520 09e 00c5 movwf send_byte__char 521 09f 2225 call send_byte 522 0a0 28c3 goto switch__185end 523 switch__185block190: 524 ; Read High Mask < Command = 0000 1001 > : 525 ; call send_byte {{ high }} 526 0a1 0831 movf high,w 527 0a2 00c5 movwf send_byte__char 528 0a3 2225 call send_byte 529 0a4 28c3 goto switch__185end 530 switch__185block194: 531 ; Read Low Mask < Command = 0000 1010 > : 532 ; call send_byte {{ low }} 533 0a5 0832 movf low,w 534 0a6 00c5 movwf send_byte__char 535 0a7 2225 call send_byte 536 0a8 28c3 goto switch__185end 537 switch__185block198: 538 ; Read Raising Mask < Command = 0000 1011 > : 539 ; call send_byte {{ raising }} 540 0a9 0833 movf raising,w 541 0aa 00c5 movwf send_byte__char 542 0ab 2225 call send_byte 543 0ac 28c3 goto switch__185end 544 switch__185block202: 545 ; Read Falling Mask < Command = 0000 1100 > : 546 ; call send_byte {{ falling }} 547 0ad 0830 movf falling,w 548 0ae 00c5 movwf send_byte__char 549 0af 2225 call send_byte 550 0b0 28c3 goto switch__185end 551 switch__185block206: 552 ; Read Vref Mode < Command = 0000 1101 > : 553 ; temporary := 0 554 0b1 01b6 clrf main__temporary 555 ; if { vref_mode } start 556 ; expression=`{ vref_mode }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 557 0b2 1849 btfsc vref_mode__byte,vref_mode__bit 558 ; if { vref_mode } body start 559 ; temporary @ 0 := 1 560 ; Select temporary @ 0 561 0036 main__temporary__210select0 equ main__temporary+0 562 0036 main__temporary__210select0__byte equ main__temporary+0 563 0000 main__temporary__210select0__bit equ 0 564 0b3 1436 bsf main__temporary__210select0__byte,main__temporary__210select0__bit 565 ; if { vref_mode } body end 566 ; if exp=`vref_mode' false skip delay=2 567 ; Other expression=`{ vref_mode }' delay=2 568 ; if { vref_mode } end 569 ; call send_byte {{ temporary }} 570 0b4 0836 movf main__temporary,w 571 0b5 00c5 movwf send_byte__char 572 0b6 2225 call send_byte 573 0b7 28c3 goto switch__185end 574 switch__185block214: 575 ; Set Vref Mode < Command = 0000 111 v > : 576 ; temporary := 0 577 0b8 01b6 clrf main__temporary 578 ; vref_mode := 0 579 0b9 1049 bcf vref_mode__byte,vref_mode__bit 580 ; if { command @ 0 } start 581 ; Alias variable for select command @ 0 582 0035 main__command__218select0 equ main__command+0 583 0035 main__command__218select0__byte equ main__command+0 584 0000 main__command__218select0__bit equ 0 585 ; expression=`{ command @ 0 }' exp_delay=0 true_delay=3 false_delay=0 true_size=3 false_size=0 586 0ba 1c35 btfss main__command__218select0__byte,main__command__218select0__bit 587 0bb 28bf goto label218__1end 588 ; if { command @ 0 } body start 589 ; vref_mode := 1 590 0bc 1449 bsf vref_mode__byte,vref_mode__bit 591 ; temporary := 1 592 0bd 3001 movlw 1 593 0be 00b6 movwf main__temporary 594 ; if { command @ 0 } body end 595 label218__1end: 596 ; if exp=` command @ 0 ' empty false 597 ; Other expression=`{ command @ 0 }' delay=-1 598 ; if { command @ 0 } end 599 ; addcon1 := temporary 600 0bf 0836 movf main__temporary,w 601 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 602 0c0 1683 bsf rp0___byte,rp0___bit 603 ; Register bank is now 1 604 0c1 009f movwf addcon1 605 ; Switch from register bank 1 to register bank 0 606 0c2 1283 bcf rp0___byte,rp0___bit 607 ; Register bank is now 0 608 switch__185end: 609 0c3 28f6 goto switch__158end 610 switch__158block226: 611 ; Command = 0001 xxxx : 612 ; bit := command & 3 613 0c4 3003 movlw 3 614 0c5 0535 andwf main__command,w 615 0c6 00b4 movwf main__bit 616 ; switch { {{ command >> 2 }} & 3 } 617 0c7 3000 movlw HIGH switch__229block_start 618 0c8 008a movwf pclath___register 619 0c9 0c35 rrf main__command,w 620 0ca 00b7 movwf main__229byte0 621 0cb 0c37 rrf main__229byte0,w 622 0cc 3903 andlw 3 623 ; case 0 624 ; case 1 625 ; case 2 626 ; case 3 627 switch__229block_start: 628 0cd 0782 addwf pcl___register,f 629 0ce 28d2 goto switch__229block230 630 0cf 28d9 goto switch__229block234 631 0d0 28e0 goto switch__229block238 632 0d1 28e9 goto switch__229block242 633 switch__229block_end: 634 ; switch_check 229 switch__229block_start switch__229block_end 635 switch__229block230: 636 ; Read High Threshold < Command = 0001 00 bb > : 637 ; call send_byte {{ thresholds_high ~~ {{ bit }} }} 638 0d2 3028 movlw LOW thresholds_high 639 0d3 0734 addwf main__bit,w 640 0d4 0084 movwf fsr___register 641 0d5 0800 movf indf___register,w 642 0d6 00c5 movwf send_byte__char 643 0d7 2225 call send_byte 644 0d8 28f1 goto switch__229end 645 switch__229block234: 646 ; Read Low Threshold < Command = 0001 01 bb > : 647 ; call send_byte {{ thresholds_low ~~ {{ bit }} }} 648 0d9 3024 movlw LOW thresholds_low 649 0da 0734 addwf main__bit,w 650 0db 0084 movwf fsr___register 651 0dc 0800 movf indf___register,w 652 0dd 00c5 movwf send_byte__char 653 0de 2225 call send_byte 654 0df 28f1 goto switch__229end 655 switch__229block238: 656 ; Set High Threshold < Command = 0001 10 bb > : 657 ; thresholds_high ~~ {{ bit }} := get_byte {{ }} 658 0e0 2204 call get_byte 659 0e1 0842 movf get_byte__0return__byte,w 660 0e2 00b7 movwf main__240byte0 661 0e3 3028 movlw LOW thresholds_high 662 0e4 0734 addwf main__bit,w 663 0e5 0084 movwf fsr___register 664 0e6 0837 movf main__240byte0,w 665 0e7 0080 movwf indf___register 666 0e8 28f1 goto switch__229end 667 switch__229block242: 668 ; Set Low Threshold < Command = 0001 11 bb > : 669 ; thresholds_low ~~ {{ bit }} := get_byte {{ }} 670 0e9 2204 call get_byte 671 0ea 0842 movf get_byte__0return__byte,w 672 0eb 00b7 movwf main__244byte0 673 0ec 3024 movlw LOW thresholds_low 674 0ed 0734 addwf main__bit,w 675 0ee 0084 movwf fsr___register 676 0ef 0837 movf main__244byte0,w 677 0f0 0080 movwf indf___register 678 switch__229end: 679 0f1 28f6 goto switch__158end 680 switch__158block248: 681 ; Set Complement Mask < Command = 0010 cccc > : 682 ; complement := command & io_mask 683 0f2 300f movlw 15 684 0f3 0535 andwf main__command,w 685 0f4 00ad movwf complement 686 0f5 28f6 goto switch__158end 687 switch__158default252: 688 ; Do nothing : 689 switch__158end: 690 0f6 2985 goto switch__155end 691 switch__155block257: 692 ; Command = 01 xx xxxx : 693 ; temporary := command & io_mask 694 0f7 300f movlw 15 695 0f8 0535 andwf main__command,w 696 0f9 00b6 movwf main__temporary 697 ; Kludge : to get switch so it does not span 256 byte boundary : 698 ; nop 3 699 ; Delay 3 cycles 700 0fa 0000 nop 701 0fb 0000 nop 702 0fc 0000 nop 703 ; switch { {{ command >> 4 }} & 3 } 704 0fd 3001 movlw HIGH switch__262block_start 705 0fe 008a movwf pclath___register 706 0ff 0e35 swapf main__command,w 707 100 3903 andlw 3 708 ; case 0 709 ; case 1 710 ; case 2 711 ; case 3 712 switch__262block_start: 713 101 0782 addwf pcl___register,f 714 102 2906 goto switch__262block263 715 103 2909 goto switch__262block267 716 104 290c goto switch__262block271 717 105 290f goto switch__262block275 718 switch__262block_end: 719 ; switch_check 262 switch__262block_start switch__262block_end 720 switch__262block263: 721 ; Set High Mask < Command = 0100 hhhh > : 722 ; high := temporary 723 106 0836 movf main__temporary,w 724 107 00b1 movwf high 725 108 2911 goto switch__262end 726 switch__262block267: 727 ; Set Low Mask < Command = 0101 llll > : 728 ; low := temporary 729 109 0836 movf main__temporary,w 730 10a 00b2 movwf low 731 10b 2911 goto switch__262end 732 switch__262block271: 733 ; Set Raising Mask < Command = 0110 rrrr > : 734 ; raising := temporary 735 10c 0836 movf main__temporary,w 736 10d 00b3 movwf raising 737 10e 2911 goto switch__262end 738 switch__262block275: 739 ; Set Falling Mask < Command = 0111 ffff > : 740 ; falling := temporary 741 10f 0836 movf main__temporary,w 742 110 00b0 movwf falling 743 switch__262end: 744 111 2985 goto switch__155end 745 switch__155block281: 746 ; Do nothing < Command = 10 xx xxxx > : 747 112 2985 goto switch__155end 748 switch__155block284: 749 ; Command = 11 xx xxxx : 750 ; switch { {{ command >> 3 }} & 7 } 751 113 3001 movlw HIGH switch__286block_start 752 114 008a movwf pclath___register 753 115 0c35 rrf main__command,w 754 116 00b7 movwf main__286byte0 755 117 0cb7 rrf main__286byte0,f 756 118 0c37 rrf main__286byte0,w 757 119 3907 andlw 7 758 ; case 0 1 2 3 4 759 ; case 5 760 ; case 6 761 ; case 7 762 switch__286block_start: 763 11a 0782 addwf pcl___register,f 764 11b 2923 goto switch__286block287 765 11c 2923 goto switch__286block287 766 11d 2923 goto switch__286block287 767 11e 2923 goto switch__286block287 768 11f 2923 goto switch__286block287 769 120 2924 goto switch__286block291 770 121 2934 goto switch__286block305 771 122 2950 goto switch__286block323 772 switch__286block_end: 773 ; switch_check 286 switch__286block_start switch__286block_end 774 switch__286block287: 775 ; Command = 1100 xxxx or 1110 0 xxx : 776 ; Do nothing : 777 123 2985 goto switch__286end 778 switch__286block291: 779 ; Read Interrupt Bits < Command = 1110 1111 > : 780 ; if { {{ command & 7 }} = 7 } start 781 124 3007 movlw 7 782 125 0535 andwf main__command,w 783 126 00b7 movwf main__293byte0 784 127 3007 movlw 7 785 128 0237 subwf main__293byte0,w 786 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 787 129 1d03 btfss z___byte,z___bit 788 12a 2933 goto label293__1end 789 ; if { {{ command & 7 }} = 7 } body start 790 ; Return Interrupt Bits : 791 ; temporary := 0 792 12b 01b6 clrf main__temporary 793 ; if { interrupt_enable } start 794 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 795 12c 18c9 btfsc interrupt_enable__byte,interrupt_enable__bit 796 ; if { interrupt_enable } body start 797 ; temporary @ 1 := 1 798 ; Select temporary @ 1 799 0036 main__temporary__297select0 equ main__temporary+0 800 0036 main__temporary__297select0__byte equ main__temporary+0 801 0001 main__temporary__297select0__bit equ 1 802 12d 14b6 bsf main__temporary__297select0__byte,main__temporary__297select0__bit 803 ; if { interrupt_enable } body end 804 ; if exp=`interrupt_enable' false skip delay=2 805 ; Other expression=`{ interrupt_enable }' delay=2 806 ; if { interrupt_enable } end 807 ; if { interrupt_pending } start 808 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 809 12e 1949 btfsc interrupt_pending__byte,interrupt_pending__bit 810 ; if { interrupt_pending } body start 811 ; temporary @ 0 := 1 812 ; Select temporary @ 0 813 0036 main__temporary__300select0 equ main__temporary+0 814 0036 main__temporary__300select0__byte equ main__temporary+0 815 0000 main__temporary__300select0__bit equ 0 816 12f 1436 bsf main__temporary__300select0__byte,main__temporary__300select0__bit 817 ; if { interrupt_pending } body end 818 ; if exp=`interrupt_pending' false skip delay=2 819 ; Other expression=`{ interrupt_pending }' delay=2 820 ; if { interrupt_pending } end 821 ; call send_byte {{ temporary }} 822 130 0836 movf main__temporary,w 823 131 00c5 movwf send_byte__char 824 132 2225 call send_byte 825 ; if { {{ command & 7 }} = 7 } body end 826 label293__1end: 827 ; if exp=` {{ command & 7 }} = 7 ' empty false 828 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 829 ; if { {{ command & 7 }} = 7 } end 830 133 2985 goto switch__286end 831 switch__286block305: 832 ; Shared Interrupt commands < Command = 1111 0 xxx > : 833 ; switch { command & 7 } 834 134 3001 movlw HIGH switch__307block_start 835 135 008a movwf pclath___register 836 136 3007 movlw 7 837 137 0535 andwf main__command,w 838 ; case 0 1 2 3 839 ; case 4 5 840 ; case 6 7 841 switch__307block_start: 842 138 0782 addwf pcl___register,f 843 139 2941 goto switch__307block308 844 13a 2941 goto switch__307block308 845 13b 2941 goto switch__307block308 846 13c 2941 goto switch__307block308 847 13d 2948 goto switch__307block313 848 13e 2948 goto switch__307block313 849 13f 294c goto switch__307block317 850 140 294c goto switch__307block317 851 switch__307block_end: 852 ; switch_check 307 switch__307block_start switch__307block_end 853 switch__307block308: 854 ; Set interrupt bits < Command = 1111 10 ep > : 855 ; interrupt_enable := command @ 1 856 ; Alias variable for select command @ 1 857 0035 main__command__310select0 equ main__command+0 858 0035 main__command__310select0__byte equ main__command+0 859 0001 main__command__310select0__bit equ 1 860 141 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 861 142 18b5 btfsc main__command__310select0__byte,main__command__310select0__bit 862 143 14c9 bsf interrupt_enable__byte,interrupt_enable__bit 863 ; interrupt_pending := command @ 0 864 ; Alias variable for select command @ 0 865 0035 main__command__311select0 equ main__command+0 866 0035 main__command__311select0__byte equ main__command+0 867 0000 main__command__311select0__bit equ 0 868 144 1149 bcf interrupt_pending__byte,interrupt_pending__bit 869 145 1835 btfsc main__command__311select0__byte,main__command__311select0__bit 870 146 1549 bsf interrupt_pending__byte,interrupt_pending__bit 871 147 294f goto switch__307end 872 switch__307block313: 873 ; Set Interrupt Pending < Command = 1111 110 p > : 874 ; interrupt_pending := command @ 0 875 ; Alias variable for select command @ 0 876 0035 main__command__315select0 equ main__command+0 877 0035 main__command__315select0__byte equ main__command+0 878 0000 main__command__315select0__bit equ 0 879 148 1149 bcf interrupt_pending__byte,interrupt_pending__bit 880 149 1835 btfsc main__command__315select0__byte,main__command__315select0__bit 881 14a 1549 bsf interrupt_pending__byte,interrupt_pending__bit 882 14b 294f goto switch__307end 883 switch__307block317: 884 ; Set Interrupt Enable < Command = 1110 111 e > : 885 ; interrupt_enable := command @ 0 886 ; Alias variable for select command @ 0 887 0035 main__command__319select0 equ main__command+0 888 0035 main__command__319select0__byte equ main__command+0 889 0000 main__command__319select0__bit equ 0 890 14c 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 891 14d 1835 btfsc main__command__319select0__byte,main__command__319select0__bit 892 14e 14c9 bsf interrupt_enable__byte,interrupt_enable__bit 893 switch__307end: 894 14f 2985 goto switch__286end 895 switch__286block323: 896 ; Shared commands < Command = 1111 1 xxx > : 897 ; switch { command & 7 } 898 150 3001 movlw HIGH switch__325block_start 899 151 008a movwf pclath___register 900 152 3007 movlw 7 901 153 0535 andwf main__command,w 902 ; case 0 903 ; case 1 904 ; case 2 905 ; case 3 906 ; case 4 907 ; case 5 908 ; case 6 909 ; case 7 910 switch__325block_start: 911 154 0782 addwf pcl___register,f 912 155 295d goto switch__325block326 913 156 2962 goto switch__325block330 914 157 2967 goto switch__325block334 915 158 296d goto switch__325block338 916 159 2970 goto switch__325block342 917 15a 297b goto switch__325block350 918 15b 297d goto switch__325block354 919 15c 2982 goto switch__325block359 920 switch__325block_end: 921 ; switch_check 325 switch__325block_start switch__325block_end 922 switch__325block326: 923 ; Clock Decrement < Command = 1111 1000 > : 924 ; osccal := osccal - osccal_unit 925 15d 30f0 movlw 240 926 ; Switch from register bank 0 to register bank 1 (which contains osccal) 927 15e 1683 bsf rp0___byte,rp0___bit 928 ; Register bank is now 1 929 15f 078f addwf osccal,f 930 ; Switch from register bank 1 to register bank 0 931 160 1283 bcf rp0___byte,rp0___bit 932 ; Register bank is now 0 933 161 2985 goto switch__325end 934 switch__325block330: 935 ; Clock Increment < Command = 1111 1001 > : 936 ; osccal := osccal + osccal_unit 937 162 3010 movlw 16 938 ; Switch from register bank 0 to register bank 1 (which contains osccal) 939 163 1683 bsf rp0___byte,rp0___bit 940 ; Register bank is now 1 941 164 078f addwf osccal,f 942 ; Switch from register bank 1 to register bank 0 943 165 1283 bcf rp0___byte,rp0___bit 944 ; Register bank is now 0 945 166 2985 goto switch__325end 946 switch__325block334: 947 ; Clock Read < Command = 1111 1010 > : 948 ; call send_byte {{ osccal }} 949 ; Switch from register bank 0 to register bank 1 (which contains osccal) 950 167 1683 bsf rp0___byte,rp0___bit 951 ; Register bank is now 1 952 168 080f movf osccal,w 953 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 954 169 1283 bcf rp0___byte,rp0___bit 955 ; Register bank is now 0 956 16a 00c5 movwf send_byte__char 957 16b 2225 call send_byte 958 16c 2985 goto switch__325end 959 switch__325block338: 960 ; Clock Pulse < Command = 1111 1011 > : 961 ; call send_byte {{ 0 }} 962 16d 01c5 clrf send_byte__char 963 16e 2225 call send_byte 964 16f 2985 goto switch__325end 965 switch__325block342: 966 ; ID Next < Command = 1111 1100 > : 967 ; call send_byte {{ id ~~ {{ id_index }} }} 968 170 0a2f incf id_index,w 969 171 018a clrf pclath___register 970 172 2011 call id 971 173 00c5 movwf send_byte__char 972 174 2225 call send_byte 973 ; id_index := id_index + 1 974 175 0aaf incf id_index,f 975 ; if { id_index >= id . size } start 976 176 3033 movlw 51 977 177 022f subwf id_index,w 978 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 979 178 1803 btfsc c___byte,c___bit 980 ; if { id_index >= id . size } body start 981 ; id_index := 0 982 179 01af clrf id_index 983 ; if { id_index >= id . size } body end 984 ; if exp=` id_index >= id . size ' false skip delay=4 985 ; Other expression=`{ id_index >= id . size }' delay=4 986 ; if { id_index >= id . size } end 987 17a 2985 goto switch__325end 988 switch__325block350: 989 ; ID Reset < Command = 1111 1101 > : 990 ; id_index := 0 991 17b 01af clrf id_index 992 17c 2985 goto switch__325end 993 switch__325block354: 994 ; Glitch Read < Command = 1111 1110 > : 995 ; call send_byte {{ glitch }} 996 17d 082e movf glitch,w 997 17e 00c5 movwf send_byte__char 998 17f 2225 call send_byte 999 ; glitch := 0 1000 180 01ae clrf glitch 1001 181 2985 goto switch__325end 1002 switch__325block359: 1003 ; Glitch < Command = 1111 1111 > : 1004 ; if { glitch != 0xff } start 1005 182 0a2e incf glitch,w 1006 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1007 183 1d03 btfss z___byte,z___bit 1008 ; if { glitch != 0xff } body start 1009 ; glitch := glitch + 1 1010 184 0aae incf glitch,f 1011 ; if { glitch != 0xff } body end 1012 ; if exp=` glitch != 0xff ' false skip delay=3 1013 ; Other expression=`{ glitch != 0xff }' delay=3 1014 ; if { glitch != 0xff } end 1015 switch__325end: 1016 switch__286end: 1017 switch__155end: 1018 185 2851 goto main__150loop__forever 1019 ; loop_forever ... end 1020 ; procedure main end 1021 1022 ; procedure delay start 1023 ; optimize 0 1024 delay: 1025 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1026 0039 delay__variables__base equ global__variables__bank0+25 1027 0039 delay__bytes__base equ delay__variables__base+0 1028 0042 delay__bits__base equ delay__variables__base+9 1029 0009 delay__total__bytes equ 9 1030 0041 delay__397byte0 equ delay__bytes__base+8 1031 0041 delay__395byte3 equ delay__bytes__base+8 1032 0041 delay__435byte1 equ delay__bytes__base+8 1033 0041 delay__373byte1 equ delay__bytes__base+8 1034 0041 delay__437byte0 equ delay__bytes__base+8 1035 0041 delay__406byte0 equ delay__bytes__base+8 1036 ; arguments_none 1037 ; uniform_delay delay_instructions 1038 ; Uniform delay remaining = 131 Accumulated Delay = 0 1039 ; Uniform delay remaining = 131 Accumulated Delay = 0 1040 ; This procedure will delay for one third of a bit time . 1041 ; Uniform delay remaining = 131 Accumulated Delay = 0 1042 ; Uniform delay remaining = 131 Accumulated Delay = 0 1043 ; Uniform delay remaining = 131 Accumulated Delay = 0 1044 0039 delay__channel equ delay__bytes__base+0 1045 ; Uniform delay remaining = 131 Accumulated Delay = 0 1046 003a delay__current equ delay__bytes__base+1 1047 ; Uniform delay remaining = 131 Accumulated Delay = 0 1048 003b delay__changed equ delay__bytes__base+2 1049 ; Uniform delay remaining = 131 Accumulated Delay = 0 1050 003c delay__previous equ delay__bytes__base+3 1051 ; Uniform delay remaining = 131 Accumulated Delay = 0 1052 003d delay__not_current equ delay__bytes__base+4 1053 ; Uniform delay remaining = 131 Accumulated Delay = 0 1054 003e delay__counter equ delay__bytes__base+5 1055 ; Uniform delay remaining = 131 Accumulated Delay = 0 1056 003f delay__mask equ delay__bytes__base+6 1057 ; Uniform delay remaining = 131 Accumulated Delay = 0 1058 0040 delay__result equ delay__bytes__base+7 1059 ; Uniform delay remaining = 131 Accumulated Delay = 0 1060 ; Uniform delay remaining = 131 Accumulated Delay = 0 1061 ; Kick the dog : 1062 ; Uniform delay remaining = 131 Accumulated Delay = 0 1063 ; watch_dog_reset 1064 186 0064 clrwdt 1065 ; Uniform delay remaining = 130 Accumulated Delay = 1 1066 ; Uniform delay remaining = 130 Accumulated Delay = 1 1067 ; channel := {{ counter >> 1 }} & 3 1068 187 1003 bcf c___byte,c___bit 1069 188 0c3e rrf delay__counter,w 1070 189 3903 andlw 3 1071 18a 00b9 movwf delay__channel 1072 ; Uniform delay remaining = 126 Accumulated Delay = 5 1073 ; counter := counter + 1 1074 18b 0abe incf delay__counter,f 1075 ; Uniform delay remaining = 125 Accumulated Delay = 6 1076 ; if { counter @ 0 } start 1077 ; Alias variable for select counter @ 0 1078 003e delay__counter__395select0 equ delay__counter+0 1079 003e delay__counter__395select0__byte equ delay__counter+0 1080 0000 delay__counter__395select0__bit equ 0 1081 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=44 false_delay=104 true_size=48 false_size=57 1082 18c 1c3e btfss delay__counter__395select0__byte,delay__counter__395select0__bit 1083 18d 29c4 goto label395__1false 1084 label395__1true: 1085 ; if { counter @ 0 } body start 1086 ; Uniform delay remaining = 125 Accumulated Delay = 0 1087 ; Set up and wait for acquistion : 1088 ; Uniform delay remaining = 125 Accumulated Delay = 0 1089 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 1090 18e 0d39 rlf delay__channel,w 1091 18f 00c1 movwf delay__397byte0 1092 190 0dc1 rlf delay__397byte0,f 1093 191 0d41 rlf delay__397byte0,w 1094 192 39f8 andlw 248 1095 193 3918 andlw 24 1096 194 3841 iorlw 65 1097 195 009f movwf addcon0 1098 ; Uniform delay remaining = 117 Accumulated Delay = 8 1099 ; Setup for interrupts : 1100 ; Uniform delay remaining = 117 Accumulated Delay = 8 1101 ; previous := current 1102 196 083a movf delay__current,w 1103 197 00bc movwf delay__previous 1104 ; Uniform delay remaining = 115 Accumulated Delay = 10 1105 ; Read the I / O port once : 1106 ; Uniform delay remaining = 115 Accumulated Delay = 10 1107 ; current := inputs ^ complement 1108 198 082c movf inputs,w 1109 199 062d xorwf complement,w 1110 19a 00ba movwf delay__current 1111 ; Uniform delay remaining = 112 Accumulated Delay = 13 1112 ; not_current := current ^ 0xf 1113 19b 300f movlw 15 1114 19c 063a xorwf delay__current,w 1115 19d 00bd movwf delay__not_current 1116 ; Uniform delay remaining = 109 Accumulated Delay = 16 1117 ; changed := current ^ previous 1118 19e 083a movf delay__current,w 1119 19f 063c xorwf delay__previous,w 1120 1a0 00bb movwf delay__changed 1121 ; Uniform delay remaining = 106 Accumulated Delay = 19 1122 ; Uniform delay remaining = 106 Accumulated Delay = 19 1123 ; See about triggering the interrupt_pending flag : 1124 ; Uniform delay remaining = 106 Accumulated Delay = 19 1125 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start 1126 1a1 0832 movf low,w 1127 1a2 053d andwf delay__not_current,w 1128 1a3 00c1 movwf delay__406byte0 1129 1a4 0831 movf high,w 1130 1a5 053a andwf delay__current,w 1131 1a6 04c1 iorwf delay__406byte0,f 1132 1a7 083b movf delay__changed,w 1133 1a8 053a andwf delay__current,w 1134 1a9 0533 andwf raising,w 1135 1aa 04c1 iorwf delay__406byte0,f 1136 1ab 083b movf delay__changed,w 1137 1ac 053d andwf delay__not_current,w 1138 1ad 0530 andwf falling,w 1139 1ae 0441 iorwf delay__406byte0,w 1140 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 1141 1af 1d03 btfss z___byte,z___bit 1142 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start 1143 ; Uniform delay remaining = 106 Accumulated Delay = 0 1144 ; interrupt_pending := 1 1145 1b0 1549 bsf interrupt_pending__byte,interrupt_pending__bit 1146 ; Uniform delay remaining = 105 Accumulated Delay = 1 1147 ; Uniform delay remaining = 105 Accumulated Delay = 1 1148 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end 1149 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 1150 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 1151 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end 1152 ; Uniform delay remaining = 90 Accumulated Delay = 35 1153 ; Uniform delay remaining = 90 Accumulated Delay = 35 1154 ; Send an interrupt if interrupts are enabled : 1155 ; Uniform delay remaining = 90 Accumulated Delay = 35 1156 ; if { interrupt_pending && interrupt_enable } start 1157 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1158 1b1 1949 btfsc interrupt_pending__byte,interrupt_pending__bit 1159 1b2 29b6 goto label411__2true 1160 label411__2false: 1161 ; Delay 2 cycles 1162 1b3 0000 nop 1163 1b4 0000 nop 1164 1b5 29be goto and411__0false 1165 label411__2true: 1166 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1167 1b6 1cc9 btfss interrupt_enable__byte,interrupt_enable__bit 1168 1b7 29bb goto label411__1false 1169 label411__1true: 1170 and411__0true: 1171 ; if { interrupt_pending && interrupt_enable } body start 1172 ; Uniform delay remaining = 90 Accumulated Delay = 0 1173 ; Shove serial out to low : 1174 ; Uniform delay remaining = 90 Accumulated Delay = 0 1175 ; interrupt_enable := 0 1176 1b8 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 1177 ; Uniform delay remaining = 89 Accumulated Delay = 1 1178 ; serial_out := 0 1179 1b9 1285 bcf serial_out__byte,serial_out__bit 1180 ; Uniform delay remaining = 88 Accumulated Delay = 2 1181 ; Uniform delay remaining = 88 Accumulated Delay = 2 1182 ; if { interrupt_pending && interrupt_enable } body end 1183 1ba 29be goto label411__1end 1184 label411__1false: 1185 ; Delay 3 cycles 1186 1bb 0000 nop 1187 1bc 0000 nop 1188 1bd 0000 nop 1189 ; if exp=`interrupt_enable' total delay=6 1190 ; if exp=`interrupt_enable' generic 1191 label411__1end: 1192 ; Other expression=`interrupt_enable' delay=6 1193 ; if exp=`interrupt_pending' total delay=9 1194 ; if exp=`interrupt_pending' generic 1195 label411__2end: 1196 ; Other expression=`interrupt_pending' delay=9 1197 and411__0false: 1198 and411__0end: 1199 ; if { interrupt_pending && interrupt_enable } end 1200 ; Uniform delay remaining = 81 Accumulated Delay = 44 1201 ; Uniform delay remaining = 81 Accumulated Delay = 44 1202 ; if { counter @ 0 } body end 1203 ; Delay 59 cycles 1204 1be 3013 movlw 19 1205 1bf 00c1 movwf delay__395byte3 1206 delay__395delay2: 1207 1c0 0bc1 decfsz delay__395byte3,f 1208 1c1 29c0 goto delay__395delay2 1209 1c2 0000 nop 1210 1c3 29fd goto label395__1end 1211 label395__1false: 1212 ; else body start 1213 ; Uniform delay remaining = 125 Accumulated Delay = 0 1214 ; Start the conversion : 1215 ; Uniform delay remaining = 125 Accumulated Delay = 0 1216 ; go_done := 1 1217 1c4 151f bsf go_done__byte,go_done__bit 1218 ; Uniform delay remaining = 124 Accumulated Delay = 1 1219 ; mask := 0 1220 1c5 01bf clrf delay__mask 1221 ; Uniform delay remaining = 123 Accumulated Delay = 2 1222 ; if { channel @ 1 } start 1223 ; Alias variable for select channel @ 1 1224 0039 delay__channel__420select0 equ delay__channel+0 1225 0039 delay__channel__420select0__byte equ delay__channel+0 1226 0001 delay__channel__420select0__bit equ 1 1227 ; expression=`{ channel @ 1 }' exp_delay=0 true_delay=4 false_delay=4 true_size=4 false_size=4 1228 1c6 1cb9 btfss delay__channel__420select0__byte,delay__channel__420select0__bit 1229 1c7 29cd goto label420__1false 1230 label420__1true: 1231 ; if { channel @ 1 } body start 1232 ; Uniform delay remaining = 123 Accumulated Delay = 0 1233 ; if { channel @ 0 } start 1234 ; Alias variable for select channel @ 0 1235 0039 delay__channel__421select0 equ delay__channel+0 1236 0039 delay__channel__421select0__byte equ delay__channel+0 1237 0000 delay__channel__421select0__bit equ 0 1238 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1239 1c8 1839 btfsc delay__channel__421select0__byte,delay__channel__421select0__bit 1240 ; if { channel @ 0 } body start 1241 ; Uniform delay remaining = 123 Accumulated Delay = 0 1242 ; mask @ 3 := 1 1243 ; Select mask @ 3 1244 003f delay__mask__422select0 equ delay__mask+0 1245 003f delay__mask__422select0__byte equ delay__mask+0 1246 0003 delay__mask__422select0__bit equ 3 1247 1c9 15bf bsf delay__mask__422select0__byte,delay__mask__422select0__bit 1248 ; Uniform delay remaining = 122 Accumulated Delay = 1 1249 ; Uniform delay remaining = 122 Accumulated Delay = 1 1250 ; if { channel @ 0 } body end 1251 1ca 1c39 btfss delay__channel__421select0__byte,delay__channel__421select0__bit 1252 ; else body start 1253 ; Uniform delay remaining = 123 Accumulated Delay = 0 1254 ; mask @ 2 := 1 1255 ; Select mask @ 2 1256 003f delay__mask__424select0 equ delay__mask+0 1257 003f delay__mask__424select0__byte equ delay__mask+0 1258 0002 delay__mask__424select0__bit equ 2 1259 1cb 153f bsf delay__mask__424select0__byte,delay__mask__424select0__bit 1260 ; Uniform delay remaining = 122 Accumulated Delay = 1 1261 ; Uniform delay remaining = 122 Accumulated Delay = 1 1262 ; else body end 1263 ; if exp=` channel @ 0 ' single true and false skip delay=4 1264 ; Other expression=`{ channel @ 0 }' delay=4 1265 ; if { channel @ 0 } end 1266 ; Uniform delay remaining = 119 Accumulated Delay = 4 1267 ; Uniform delay remaining = 119 Accumulated Delay = 4 1268 ; if { channel @ 1 } body end 1269 1cc 29d2 goto label420__1end 1270 label420__1false: 1271 ; else body start 1272 ; Uniform delay remaining = 123 Accumulated Delay = 0 1273 ; if { channel @ 0 } start 1274 ; Alias variable for select channel @ 0 1275 0039 delay__channel__427select0 equ delay__channel+0 1276 0039 delay__channel__427select0__byte equ delay__channel+0 1277 0000 delay__channel__427select0__bit equ 0 1278 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 1279 1cd 1839 btfsc delay__channel__427select0__byte,delay__channel__427select0__bit 1280 ; if { channel @ 0 } body start 1281 ; Uniform delay remaining = 123 Accumulated Delay = 0 1282 ; mask @ 1 := 1 1283 ; Select mask @ 1 1284 003f delay__mask__428select0 equ delay__mask+0 1285 003f delay__mask__428select0__byte equ delay__mask+0 1286 0001 delay__mask__428select0__bit equ 1 1287 1ce 14bf bsf delay__mask__428select0__byte,delay__mask__428select0__bit 1288 ; Uniform delay remaining = 122 Accumulated Delay = 1 1289 ; Uniform delay remaining = 122 Accumulated Delay = 1 1290 ; if { channel @ 0 } body end 1291 1cf 1c39 btfss delay__channel__427select0__byte,delay__channel__427select0__bit 1292 ; else body start 1293 ; Uniform delay remaining = 123 Accumulated Delay = 0 1294 ; mask @ 0 := 1 1295 ; Select mask @ 0 1296 003f delay__mask__430select0 equ delay__mask+0 1297 003f delay__mask__430select0__byte equ delay__mask+0 1298 0000 delay__mask__430select0__bit equ 0 1299 1d0 143f bsf delay__mask__430select0__byte,delay__mask__430select0__bit 1300 ; Uniform delay remaining = 122 Accumulated Delay = 1 1301 ; Uniform delay remaining = 122 Accumulated Delay = 1 1302 ; else body end 1303 ; if exp=` channel @ 0 ' single true and false skip delay=4 1304 ; Other expression=`{ channel @ 0 }' delay=4 1305 ; if { channel @ 0 } end 1306 ; Uniform delay remaining = 119 Accumulated Delay = 4 1307 ; Uniform delay remaining = 119 Accumulated Delay = 4 1308 ; else body end 1309 ; Delay 1 cycles 1310 1d1 0000 nop 1311 ; if exp=` channel @ 1 ' total delay=8 1312 ; if exp=` channel @ 1 ' generic 1313 label420__1end: 1314 ; Other expression=`{ channel @ 1 }' delay=8 1315 ; if { channel @ 1 } end 1316 ; Uniform delay remaining = 115 Accumulated Delay = 10 1317 ; Delaying 60 uS is way longer than necessary for the conversion 1318 ; Uniform delay remaining = 115 Accumulated Delay = 10 1319 ; to complete . 1320 ; Uniform delay remaining = 115 Accumulated Delay = 10 1321 ; nop 60 1322 ; Delay 60 cycles 1323 1d2 3013 movlw 19 1324 1d3 00c1 movwf delay__435byte1 1325 delay__435delay0: 1326 1d4 0bc1 decfsz delay__435byte1,f 1327 1d5 29d4 goto delay__435delay0 1328 1d6 0000 nop 1329 1d7 0000 nop 1330 ; Uniform delay remaining = 55 Accumulated Delay = 70 1331 ; result := addres 1332 1d8 081e movf addres,w 1333 1d9 00c0 movwf delay__result 1334 ; Uniform delay remaining = 53 Accumulated Delay = 72 1335 ; analogs ~~ {{ channel }} := result 1336 1da 0840 movf delay__result,w 1337 1db 00c1 movwf delay__437byte0 1338 1dc 3020 movlw LOW analogs 1339 1dd 0739 addwf delay__channel,w 1340 1de 0084 movwf fsr___register 1341 1df 0841 movf delay__437byte0,w 1342 1e0 0080 movwf indf___register 1343 ; Uniform delay remaining = 46 Accumulated Delay = 79 1344 ; if { result <= thresholds_low ~~ {{ channel }} } start 1345 1e1 3024 movlw LOW thresholds_low 1346 1e2 0739 addwf delay__channel,w 1347 1e3 0084 movwf fsr___register 1348 1e4 0800 movf indf___register,w 1349 1e5 0240 subwf delay__result,w 1350 1e6 1903 btfsc z___byte,z___bit 1351 1e7 1003 bcf c___byte,c___bit 1352 ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 1353 1e8 1c03 btfss c___byte,c___bit 1354 1e9 29ed goto label438__0true 1355 label438__0false: 1356 ; Delay 2 cycles 1357 1ea 0000 nop 1358 1eb 0000 nop 1359 1ec 29f0 goto label438__0end 1360 label438__0true: 1361 ; if { result <= thresholds_low ~~ {{ channel }} } body start 1362 ; Uniform delay remaining = 46 Accumulated Delay = 0 1363 ; inputs := inputs & {{ mask ^ io_mask }} 1364 1ed 300f movlw 15 1365 1ee 063f xorwf delay__mask,w 1366 1ef 05ac andwf inputs,f 1367 ; Uniform delay remaining = 43 Accumulated Delay = 3 1368 ; Uniform delay remaining = 43 Accumulated Delay = 3 1369 ; if { result <= thresholds_low ~~ {{ channel }} } body end 1370 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 1371 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic 1372 label438__0end: 1373 ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 1374 ; if { result <= thresholds_low ~~ {{ channel }} } end 1375 ; Uniform delay remaining = 33 Accumulated Delay = 92 1376 ; if { result >= thresholds_high ~~ {{ channel }} } start 1377 1f0 3028 movlw LOW thresholds_high 1378 1f1 0739 addwf delay__channel,w 1379 1f2 0084 movwf fsr___register 1380 1f3 0800 movf indf___register,w 1381 1f4 0240 subwf delay__result,w 1382 ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 1383 1f5 1803 btfsc c___byte,c___bit 1384 1f6 29f9 goto label441__0true 1385 label441__0false: 1386 ; Delay 1 cycles 1387 1f7 0000 nop 1388 1f8 29fb goto label441__0end 1389 label441__0true: 1390 ; if { result >= thresholds_high ~~ {{ channel }} } body start 1391 ; Uniform delay remaining = 33 Accumulated Delay = 0 1392 ; inputs := inputs | mask 1393 1f9 083f movf delay__mask,w 1394 1fa 04ac iorwf inputs,f 1395 ; Uniform delay remaining = 31 Accumulated Delay = 2 1396 ; Uniform delay remaining = 31 Accumulated Delay = 2 1397 ; if { result >= thresholds_high ~~ {{ channel }} } body end 1398 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 1399 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic 1400 label441__0end: 1401 ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 1402 ; if { result >= thresholds_high ~~ {{ channel }} } end 1403 ; Uniform delay remaining = 23 Accumulated Delay = 102 1404 ; inputs := inputs & io_mask 1405 1fb 300f movlw 15 1406 1fc 05ac andwf inputs,f 1407 ; Uniform delay remaining = 21 Accumulated Delay = 104 1408 ; Uniform delay remaining = 21 Accumulated Delay = 104 1409 ; else body end 1410 ; if exp=` counter @ 0 ' total delay=107 1411 ; if exp=` counter @ 0 ' generic 1412 label395__1end: 1413 ; Other expression=`{ counter @ 0 }' delay=107 1414 ; if { counter @ 0 } end 1415 ; Uniform delay remaining = 18 Accumulated Delay = 113 1416 ; Uniform delay remaining = 18 Accumulated Delay = 113 1417 ; Soak up remaining 18 cycles 1418 ; Delay 18 cycles 1419 1fd 3005 movlw 5 1420 1fe 00c1 movwf delay__373byte1 1421 delay__373delay0: 1422 1ff 0bc1 decfsz delay__373byte1,f 1423 200 29ff goto delay__373delay0 1424 201 0000 nop 1425 202 0000 nop 1426 ; procedure delay end 1427 203 3400 retlw 0 1428 ; optimize 1 1429 1430 ; procedure get_byte start 1431 get_byte: 1432 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1433 0042 get_byte__variables__base equ global__variables__bank0+34 1434 0042 get_byte__bytes__base equ get_byte__variables__base+0 1435 0045 get_byte__bits__base equ get_byte__variables__base+3 1436 0003 get_byte__total__bytes equ 3 1437 ; arguments_none 1438 0042 get_byte__0return__byte equ get_byte__bytes__base+0 1439 ; Wait for a character and return it . 1440 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 1441 ; way the next call to get_byte < > will sychronize on the start 1442 ; bit instead of possibly starting a little later . 1443 0043 get_byte__count equ get_byte__bytes__base+1 1444 0044 get_byte__char equ get_byte__bytes__base+2 1445 ; Wait for start bit : 1446 ; receiving := 1 1447 204 15c9 bsf receiving__byte,receiving__bit 1448 ; `while serial_in ...' start 1449 get_byte__464while__continue: 1450 ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 1451 205 1d85 btfss serial_in__byte,serial_in__bit 1452 206 2a09 goto get_byte__464while__break 1453 ; call delay {{ }} 1454 207 2186 call delay 1455 208 2a05 goto get_byte__464while__continue 1456 ; if exp=`serial_in' false goto 1457 ; Other expression=`serial_in' delay=-1 1458 get_byte__464while__break: 1459 ; `while serial_in ...' end 1460 ; Clear interrupts and interrupt pending : 1461 ; 1 cycle : 1462 ; serial_out := 1 1463 209 1685 bsf serial_out__byte,serial_out__bit 1464 ; Skip over start bit : 1465 ; call delay {{ }} 1466 20a 2186 call delay 1467 ; call delay {{ }} 1468 20b 2186 call delay 1469 ; call delay {{ }} 1470 20c 2186 call delay 1471 ; Sample in the middle third of each data bit : 1472 ; 1 cycle : 1473 ; char := 0 1474 20d 01c4 clrf get_byte__char 1475 ; 2 cycles to set up loop : 1476 ; 1 + 1 + 2 = 4 1477 ; nop extra_instructions_per_bit - 4 1478 ; Delay 5 cycles 1479 20e 0000 nop 1480 20f 0000 nop 1481 210 0000 nop 1482 211 0000 nop 1483 212 0000 nop 1484 ; `count_down count 8 ...' start 1485 213 3008 movlw 8 1486 214 00c3 movwf get_byte__count 1487 get_byte__483_loop: 1488 ; call delay {{ }} 1489 215 2186 call delay 1490 ; 2 cycles : 1491 ; char := char >> 1 1492 216 1003 bcf c___byte,c___bit 1493 217 0cc4 rrf get_byte__char,f 1494 ; 2 cycles : 1495 ; if { serial_in } start 1496 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1497 218 1985 btfsc serial_in__byte,serial_in__bit 1498 ; if { serial_in } body start 1499 ; char @ 7 := 1 1500 ; Select char @ 7 1501 0044 get_byte__char__489select0 equ get_byte__char+0 1502 0044 get_byte__char__489select0__byte equ get_byte__char+0 1503 0007 get_byte__char__489select0__bit equ 7 1504 219 17c4 bsf get_byte__char__489select0__byte,get_byte__char__489select0__bit 1505 ; if { serial_in } body end 1506 ; if exp=`serial_in' false skip delay=2 1507 ; Other expression=`{ serial_in }' delay=2 1508 ; if { serial_in } end 1509 ; call delay {{ }} 1510 21a 2186 call delay 1511 ; call delay {{ }} 1512 21b 2186 call delay 1513 ; 3 cycles at end of loop : 1514 ; 2 + 2 + 3 = 7 1515 ; nop extra_instructions_per_bit - 7 1516 ; Delay 2 cycles 1517 21c 0000 nop 1518 21d 0000 nop 1519 21e 0bc3 decfsz get_byte__count,f 1520 21f 2a15 goto get_byte__483_loop 1521 get_byte__483_done: 1522 ; `count_down count 8 ...' end 1523 ; Skip over 2 / 3 ' s of stop bit : 1524 ; call delay {{ }} 1525 220 2186 call delay 1526 ; call delay {{ }} 1527 221 2186 call delay 1528 ; return char 1529 222 0844 movf get_byte__char,w 1530 223 00c2 movwf get_byte__0return__byte 1531 224 3400 retlw 0 1532 ; procedure get_byte end 1533 1534 ; procedure send_byte start 1535 send_byte: 1536 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1537 0045 send_byte__variables__base equ global__variables__bank0+37 1538 0045 send_byte__bytes__base equ send_byte__variables__base+0 1539 0047 send_byte__bits__base equ send_byte__variables__base+2 1540 0002 send_byte__total__bytes equ 2 1541 0045 send_byte__char equ send_byte__bytes__base+0 1542 ; Send < char > to < tx > : 1543 0046 send_byte__count equ send_byte__bytes__base+1 1544 ; < receiving > will be 1 if the last get / put routine was a get . 1545 ; Before we start transmitting a response back , we want to ensure 1546 ; that there has been enough time to turn the line line around . 1547 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 1548 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 1549 ; for good measure . Technically , the second call to delay < > 1550 ; is not really needed . 1551 ; if { receiving } start 1552 ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 1553 225 1dc9 btfss receiving__byte,receiving__bit 1554 226 2a2a goto label520__0end 1555 ; if { receiving } body start 1556 ; receiving := 0 1557 227 11c9 bcf receiving__byte,receiving__bit 1558 ; call delay {{ }} 1559 228 2186 call delay 1560 ; call delay {{ }} 1561 229 2186 call delay 1562 ; if { receiving } body end 1563 label520__0end: 1564 ; if exp=`receiving' empty false 1565 ; Other expression=`{ receiving }' delay=-1 1566 ; if { receiving } end 1567 ; Send the start bit : 1568 ; 1 cycle : 1569 ; serial_out := 0 1570 22a 1285 bcf serial_out__byte,serial_out__bit 1571 ; call delay {{ }} 1572 22b 2186 call delay 1573 ; call delay {{ }} 1574 22c 2186 call delay 1575 ; call delay {{ }} 1576 22d 2186 call delay 1577 ; 2 cycles for loop setup : 1578 ; 1 + 2 = 3 1579 ; nop extra_instructions_per_bit - 3 1580 ; Delay 6 cycles 1581 22e 0000 nop 1582 22f 0000 nop 1583 230 0000 nop 1584 231 0000 nop 1585 232 0000 nop 1586 233 0000 nop 1587 ; Send the data : 1588 ; `count_down count 8 ...' start 1589 234 3008 movlw 8 1590 235 00c6 movwf send_byte__count 1591 send_byte__537_loop: 1592 ; 4 cycles : 1593 ; serial_out := char @ 0 1594 ; Alias variable for select char @ 0 1595 0045 send_byte__char__539select0 equ send_byte__char+0 1596 0045 send_byte__char__539select0__byte equ send_byte__char+0 1597 0000 send_byte__char__539select0__bit equ 0 1598 236 1c45 btfss send_byte__char__539select0__byte,send_byte__char__539select0__bit 1599 237 1285 bcf serial_out__byte,serial_out__bit 1600 238 1845 btfsc send_byte__char__539select0__byte,send_byte__char__539select0__bit 1601 239 1685 bsf serial_out__byte,serial_out__bit 1602 ; 2 cycles : 1603 ; char := char >> 1 1604 23a 1003 bcf c___byte,c___bit 1605 23b 0cc5 rrf send_byte__char,f 1606 ; call delay {{ }} 1607 23c 2186 call delay 1608 ; call delay {{ }} 1609 23d 2186 call delay 1610 ; call delay {{ }} 1611 23e 2186 call delay 1612 ; 3 cycles at end of loop : 1613 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 1614 23f 0bc6 decfsz send_byte__count,f 1615 240 2a36 goto send_byte__537_loop 1616 send_byte__537_done: 1617 ; `count_down count 8 ...' end 1618 ; Send the stop bit : 1619 ; 1 cycle to close out previous loop : 1620 ; nop 1 1621 ; Delay 1 cycles 1622 241 0000 nop 1623 ; 1 cycle : 1624 ; serial_out := 1 1625 242 1685 bsf serial_out__byte,serial_out__bit 1626 ; call delay {{ }} 1627 243 2186 call delay 1628 ; call delay {{ }} 1629 244 2186 call delay 1630 ; call delay {{ }} 1631 245 2186 call delay 1632 ; 2 cycles for call / return : 1633 ; 2 cycles for argument : 1634 ; 1 + 2 + 2 = 5 1635 ; nop extra_instructions_per_bit - 5 1636 ; Delay 4 cycles 1637 246 0000 nop 1638 247 0000 nop 1639 248 0000 nop 1640 249 0000 nop 1641 ; procedure send_byte end 1642 24a 3400 retlw 0 1643 1644 ; procedure reset start 1645 reset: 1646 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 1647 0047 reset__variables__base equ global__variables__bank0+39 1648 0047 reset__bytes__base equ reset__variables__base+0 1649 0049 reset__bits__base equ reset__variables__base+2 1650 0002 reset__total__bytes equ 2 1651 0048 reset__582byte0 equ reset__bytes__base+1 1652 0048 reset__581byte0 equ reset__bytes__base+1 1653 ; arguments_none 1654 ; This procedure will initialize all of the registers : 1655 0047 reset__index equ reset__bytes__base+0 1656 ; inputs := 0 1657 24b 01ac clrf inputs 1658 ; high := 0 1659 24c 01b1 clrf high 1660 ; low := 0 1661 24d 01b2 clrf low 1662 ; raising := 0 1663 24e 01b3 clrf raising 1664 ; falling := 0 1665 24f 01b0 clrf falling 1666 ; complement := 0 1667 250 01ad clrf complement 1668 ; interrupt_enable := 0 1669 251 10c9 bcf interrupt_enable__byte,interrupt_enable__bit 1670 ; interrupt_pending := 0 1671 252 1149 bcf interrupt_pending__byte,interrupt_pending__bit 1672 ; index := 0 1673 253 01c7 clrf reset__index 1674 ; `while index < 4 ...' start 1675 reset__580while__continue: 1676 254 3004 movlw 4 1677 255 0247 subwf reset__index,w 1678 ; expression=` index < 4 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 1679 256 1803 btfsc c___byte,c___bit 1680 257 2a68 goto reset__580while__break 1681 ; thresholds_high ~~ {{ index }} := 0xc0 1682 258 30c0 movlw 192 1683 259 00c8 movwf reset__581byte0 1684 25a 3028 movlw LOW thresholds_high 1685 25b 0747 addwf reset__index,w 1686 25c 0084 movwf fsr___register 1687 25d 0848 movf reset__581byte0,w 1688 25e 0080 movwf indf___register 1689 ; thresholds_low ~~ {{ index }} := 0x40 1690 25f 3040 movlw 64 1691 260 00c8 movwf reset__582byte0 1692 261 3024 movlw LOW thresholds_low 1693 262 0747 addwf reset__index,w 1694 263 0084 movwf fsr___register 1695 264 0848 movf reset__582byte0,w 1696 265 0080 movwf indf___register 1697 ; index := index + 1 1698 266 0ac7 incf reset__index,f 1699 267 2a54 goto reset__580while__continue 1700 ; if exp=` index < 4 ' false goto 1701 ; Other expression=` index < 4 ' delay=-1 1702 reset__580while__break: 1703 ; `while index < 4 ...' end 1704 ; glitch := 0 1705 268 01ae clrf glitch 1706 ; id_index := 0 1707 269 01af clrf id_index 1708 ; serial_out := 1 1709 26a 1685 bsf serial_out__byte,serial_out__bit 1710 ; vref_mode := 0 1711 26b 1049 bcf vref_mode__byte,vref_mode__bit 1712 ; addcon1 := 0 1713 ; Switch from register bank 0 to register bank 1 (which contains addcon1) 1714 26c 1683 bsf rp0___byte,rp0___bit 1715 ; Register bank is now 1 1716 26d 019f clrf addcon1 1717 ; procedure reset end 1718 ; Switch from register bank 1 to register bank 0 1719 26e 1283 bcf rp0___byte,rp0___bit 1720 ; Register bank is now 0 1721 26f 3400 retlw 0 1722 1723 ; Register bank 0 used 41 bytes of 96 available bytes 1724 ; Register bank 1 used 0 bytes of 32 available bytes 1725 1726 end