1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0040 global__bit__variables__bank0 equ 64 5 00a6 global__bit__variables__bank1 equ 166 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 0003 rp0___byte equ 3 13 0005 rp0___bit equ 5 14 0003 rp1___byte equ 3 15 0006 rp1___bit equ 6 16 0003 irp___byte equ 3 17 0007 irp___bit equ 7 18 0085 trisa___register equ 0x85 19 0086 trisb___register equ 0x86 20 0004 fsr___register equ 4 21 000a pclath___register equ 10 22 org 0 23 start: 24 000 0000 nop 25 001 0000 nop 26 002 0000 nop 27 003 2805 goto skip___interrupt 28 interrupt___vector: 29 004 0009 retfie 30 skip___interrupt: 31 ; Use oscillator calibration stored in high memory 32 005 27ff call 2047 33 ; Switch from register bank 0 to register bank 1 (which contains 143) 34 006 1683 bsf rp0___byte,rp0___bit 35 ; Register bank is now 1 36 007 008f movwf 143 37 ; Initialize A/D system to allow digital I/O 38 008 3007 movlw 7 39 009 009f movwf 159 40 ; Switch from register bank 1 to register bank 0 (which contains 31) 41 00a 1283 bcf rp0___byte,rp0___bit 42 ; Register bank is now 0 43 00b 019f clrf 31 44 ; Initialize TRIS registers 45 00c 30df movlw 223 46 00d 0065 tris 5 47 00e 018a clrf pclath___register 48 ; Switch from register bank 0 to register bank 1 49 00f 1683 bsf rp0___byte,rp0___bit 50 ; Register bank is now 1 51 010 2a00 goto main 52 ; comment ############################################################################# 53 ; comment {} 54 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 55 ; comment {All rights reserved .} 56 ; comment {} 57 ; comment {Permission to use , copy , modify , distribute , and sell this software} 58 ; comment {for any purpose is hereby granted without fee provided that the above} 59 ; comment {copyright notice and this permission are retained . The author makes} 60 ; comment {no representations about the suitability of this software for any purpose .} 61 ; comment {It is provided { as is } without express or implied warranty .} 62 ; comment {} 63 ; comment {This is the code that implements the InOut4 RoboBrick . Basically} 64 ; comment {it just waits for commands that come in at 2400 baud and responds} 65 ; comment {to them . See} 66 ; comment {} 67 ; comment {http : / / web . gramlich . net / projects / robobricks / inout4 / index . html} 68 ; comment {} 69 ; comment {for more details .} 70 ; comment {} 71 ; comment ############################################################################# 72 ; processor pic12ce674 cp = off pwrte = off wdte = off mclre = off fosc = intrc_no_clock 73 ; 16244=0x3f74 8199=0x2007 74 __config 16244 75 2007 configuration___address equ 8199 76 ; comment {define processor constants} 77 ; constant clock_rate 4000000 78 3d0900 clock_rate equ 4000000 79 ; constant clocks_per_instruction 4 80 0004 clocks_per_instruction equ 4 81 ; constant instruction_rate clock_rate / clocks_per_instruction 82 f4240 instruction_rate equ 1000000 83 ; comment {define serial communication control constants} 84 ; constant baud_rate 2400 85 0960 baud_rate equ 2400 86 ; constant instructions_per_bit instruction_rate / baud_rate 87 01a0 instructions_per_bit equ 416 88 ; constant delays_per_bit 3 89 0003 delays_per_bit equ 3 90 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 91 008a instructions_per_delay equ 138 92 0005 osccal equ 5 93 ; constant osccal_unit 0x10 94 0010 osccal_unit equ 16 95 ; comment {Analog to digital conversion result register :} 96 001e addres equ 30 97 ; comment {Analog to digital conversion register 0 :} 98 001f addcon0 equ 31 99 ; bind adon addcon0 @ 0 100 001f adon equ addcon0+0 101 001f adon__byte equ addcon0+0 102 0000 adon__bit equ 0 103 ; bind go_done addcon0 @ 2 104 001f go_done equ addcon0+0 105 001f go_done__byte equ addcon0+0 106 0002 go_done__bit equ 2 107 ; bind chs0 addcon0 @ 3 108 001f chs0 equ addcon0+0 109 001f chs0__byte equ addcon0+0 110 0003 chs0__bit equ 3 111 ; bind chs1 addcon0 @ 4 112 001f chs1 equ addcon0+0 113 001f chs1__byte equ addcon0+0 114 0004 chs1__bit equ 4 115 ; bind adcs0 addcon0 @ 6 116 001f adcs0 equ addcon0+0 117 001f adcs0__byte equ addcon0+0 118 0006 adcs0__bit equ 6 119 ; bind adcs1 addcon0 @ 7 120 001f adcs1 equ addcon0+0 121 001f adcs1__byte equ addcon0+0 122 0007 adcs1__bit equ 7 123 ; comment {Interrupt Control Register :} 124 000b intcon equ 11 125 ; bind gpif intcon @ 0 126 000b gpif equ intcon+0 127 000b gpif__byte equ intcon+0 128 0000 gpif__bit equ 0 129 ; bind intf intcon @ 1 130 000b intf equ intcon+0 131 000b intf__byte equ intcon+0 132 0001 intf__bit equ 1 133 ; bind toif intcon @ 2 134 000b toif equ intcon+0 135 000b toif__byte equ intcon+0 136 0002 toif__bit equ 2 137 ; bind gpie intcon @ 3 138 000b gpie equ intcon+0 139 000b gpie__byte equ intcon+0 140 0003 gpie__bit equ 3 141 ; bind inte intcon @ 4 142 000b inte equ intcon+0 143 000b inte__byte equ intcon+0 144 0004 inte__bit equ 4 145 ; bind toie intcon @ 5 146 000b toie equ intcon+0 147 000b toie__byte equ intcon+0 148 0005 toie__bit equ 5 149 ; bind peie intcon @ 6 150 000b peie equ intcon+0 151 000b peie__byte equ intcon+0 152 0006 peie__bit equ 6 153 ; bind gie intcon @ 7 154 000b gie equ intcon+0 155 000b gie__byte equ intcon+0 156 0007 gie__bit equ 7 157 000c pir1 equ 12 158 ; bind adif pir1 @ 6 159 000c adif equ pir1+0 160 000c adif__byte equ pir1+0 161 0006 adif__bit equ 6 162 008c pie1 equ 140 163 ; bind adie pie1 @ 6 164 008c adie equ pie1+0 165 008c adie__byte equ pie1+0 166 0006 adie__bit equ 6 167 ; comment {Analog to digital conversion register 1 :} 168 009f addcon1 equ 159 169 ; bind pcfg0 addcon1 @ 0 170 009f pcfg0 equ addcon1+0 171 009f pcfg0__byte equ addcon1+0 172 0000 pcfg0__bit equ 0 173 ; bind pcfg1 addcon1 @ 1 174 009f pcfg1 equ addcon1+0 175 009f pcfg1__byte equ addcon1+0 176 0001 pcfg1__bit equ 1 177 ; bind pcfg2 addcon1 @ 2 178 009f pcfg2 equ addcon1+0 179 009f pcfg2__byte equ addcon1+0 180 0002 pcfg2__bit equ 2 181 ; constant ain_bit0 0 182 0000 ain_bit0 equ 0 183 ; constant ain_bit1 1 184 0001 ain_bit1 equ 1 185 ; constant ain_bit2 2 186 0002 ain_bit2 equ 2 187 ; constant serial_in_bit 3 188 0003 serial_in_bit equ 3 189 ; constant ain_bit3 4 190 0004 ain_bit3 equ 4 191 ; constant serial_out_bit 5 192 0005 serial_out_bit equ 5 193 ; constant ain_mask0 {{ 1 << ain_bit0 }} 194 0001 ain_mask0 equ 1 195 ; constant ain_mask1 {{ 1 << ain_bit1 }} 196 0002 ain_mask1 equ 2 197 ; constant ain_mask2 {{ 1 << ain_bit2 }} 198 0004 ain_mask2 equ 4 199 ; constant ain_mask3 {{ 1 << ain_bit3 }} 200 0010 ain_mask3 equ 16 201 ; constant serial_in_mask {{ 1 << serial_in_bit }} 202 0008 serial_in_mask equ 8 203 ; constant serial_out_mask {{ 1 << serial_out_bit }} 204 0020 serial_out_mask equ 32 205 ; constant io_mask 0xf 206 000f io_mask equ 15 207 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} 208 0017 ain_mask equ 23 209 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} 210 0028 serial_mask equ 40 211 ; comment {define port bit assignments} 212 0005 porta equ 5 213 0005 ain0__byte equ 5 214 0000 ain0__bit equ 0 215 0005 ain1__byte equ 5 216 0001 ain1__bit equ 1 217 0005 ain2__byte equ 5 218 0002 ain2__bit equ 2 219 0005 ain3__byte equ 5 220 0004 ain3__bit equ 4 221 0005 serial_in__byte equ 5 222 0003 serial_in__bit equ 3 223 0005 serial_out__byte equ 5 224 0005 serial_out__bit equ 5 225 ; constant analogs_size 4 226 0004 analogs_size equ 4 227 ; string_constants Start 228 ; Switch from register bank 1 to register bank 0 229 011 1283 bcf rp0___byte,rp0___bit 230 ; Register bank is now 0 231 string___fetch: 232 012 0082 movwf pcl___register 233 ; id = 1 , 0 , 19 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 10 , 0s'AnalogIn4A' , 15 , 0s'Gramlich&Benson' 234 0000 id___string equ 0 235 id: 236 013 0782 addwf pcl___register,f 237 ; Length = 51 238 014 3433 retlw 51 239 ; 1 240 015 3401 retlw 1 241 ; 0 242 016 3400 retlw 0 243 ; 19 244 017 3413 retlw 19 245 ; 0 246 018 3400 retlw 0 247 ; 0 248 019 3400 retlw 0 249 ; 0 250 01a 3400 retlw 0 251 ; 0 252 01b 3400 retlw 0 253 ; 0 254 01c 3400 retlw 0 255 ; 0r'16' 256 01d 3491 retlw 145 ; random number 257 01e 3438 retlw 56 ; random number 258 01f 34fd retlw 253 ; random number 259 020 34dc retlw 220 ; random number 260 021 344e retlw 78 ; random number 261 022 3435 retlw 53 ; random number 262 023 34d6 retlw 214 ; random number 263 024 3404 retlw 4 ; random number 264 025 34db retlw 219 ; random number 265 026 34ff retlw 255 ; random number 266 027 34a7 retlw 167 ; random number 267 028 34a6 retlw 166 ; random number 268 029 3485 retlw 133 ; random number 269 02a 34a5 retlw 165 ; random number 270 02b 3424 retlw 36 ; random number 271 02c 347c retlw 124 ; random number 272 ; 10 273 02d 340a retlw 10 274 ; `AnalogIn4A' 275 02e 3441 retlw 65 276 02f 346e retlw 110 277 030 3461 retlw 97 278 031 346c retlw 108 279 032 346f retlw 111 280 033 3467 retlw 103 281 034 3449 retlw 73 282 035 346e retlw 110 283 036 3434 retlw 52 284 037 3441 retlw 65 285 ; 15 286 038 340f retlw 15 287 ; `Gramlich&Benson' 288 039 3447 retlw 71 289 03a 3472 retlw 114 290 03b 3461 retlw 97 291 03c 346d retlw 109 292 03d 346c retlw 108 293 03e 3469 retlw 105 294 03f 3463 retlw 99 295 040 3468 retlw 104 296 041 3426 retlw 38 297 042 3442 retlw 66 298 043 3465 retlw 101 299 044 346e retlw 110 300 045 3473 retlw 115 301 046 346f retlw 111 302 047 346e retlw 110 303 ; string__constants End 304 ; constant id_size 8 + 16 + 1 + 10 + 1 + 15 305 0033 id_size equ 51 306 ; bank 0 307 ; Default register bank is now 0 308 0020 analogs equ global__variables__bank0+0 309 0024 thresholds_low equ global__variables__bank0+4 310 0028 thresholds_high equ global__variables__bank0+8 311 002c inputs equ global__variables__bank0+12 312 002d complement equ global__variables__bank0+13 313 ; comment {Interrupt masks :} 314 0040 interrupt_enable equ global__bit__variables__bank0+0 315 0040 interrupt_enable__byte equ global__bit__variables__bank0+0 316 0000 interrupt_enable__bit equ 0 317 0040 interrupt_pending equ global__bit__variables__bank0+0 318 0040 interrupt_pending__byte equ global__bit__variables__bank0+0 319 0001 interrupt_pending__bit equ 1 320 0040 receiving equ global__bit__variables__bank0+0 321 0040 receiving__byte equ global__bit__variables__bank0+0 322 0002 receiving__bit equ 2 323 002e falling equ global__variables__bank0+14 324 002f high equ global__variables__bank0+15 325 0030 low equ global__variables__bank0+16 326 0031 raising equ global__variables__bank0+17 327 ; comment {For now put all the smaller routines first so that they can live} 328 ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} 329 ; comment {can only call routines that are within the first 256 bytes < i . e .} 330 ; comment {the first half > of the code page .} 331 ; bank 0 332 ; Default register bank is now 0 333 334 ; procedure delay start 335 ; optimize 0 336 delay: 337 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 338 ; Procedure must be called with PCLATH set to code bank 0 339 0032 delay__variables__base equ global__variables__bank0+18 340 0032 delay__bytes__base equ delay__variables__base+0 341 003a delay__bits__base equ delay__variables__base+8 342 0009 delay__total__bytes equ 9 343 0039 delay__175byte2 equ delay__bytes__base+7 344 0039 delay__152byte3 equ delay__bytes__base+7 345 0039 delay__187byte0 equ delay__bytes__base+7 346 0039 delay__186byte1 equ delay__bytes__base+7 347 0039 delay__131byte1 equ delay__bytes__base+7 348 0039 delay__163byte0 equ delay__bytes__base+7 349 0039 delay__154byte0 equ delay__bytes__base+7 350 ; arguments_none 351 ; uniform_delay instructions_per_delay 352 ; Uniform delay remaining = 134 Accumulated Delay = 0 353 ; Uniform delay remaining = 134 Accumulated Delay = 0 354 ; This procedure will delay for one third of a bit time . 355 ; Uniform delay remaining = 134 Accumulated Delay = 0 356 ; Uniform delay remaining = 134 Accumulated Delay = 0 357 ; Uniform delay remaining = 134 Accumulated Delay = 0 358 0032 delay__channel equ delay__bytes__base+0 359 ; Uniform delay remaining = 134 Accumulated Delay = 0 360 0033 delay__current equ delay__bytes__base+1 361 ; Uniform delay remaining = 134 Accumulated Delay = 0 362 0034 delay__changed equ delay__bytes__base+2 363 ; Uniform delay remaining = 134 Accumulated Delay = 0 364 0035 delay__previous equ delay__bytes__base+3 365 ; Uniform delay remaining = 134 Accumulated Delay = 0 366 0036 delay__not_current equ delay__bytes__base+4 367 ; Uniform delay remaining = 134 Accumulated Delay = 0 368 0037 delay__counter equ delay__bytes__base+5 369 ; Uniform delay remaining = 134 Accumulated Delay = 0 370 0038 delay__mask equ delay__bytes__base+6 371 ; Uniform delay remaining = 134 Accumulated Delay = 0 372 ; Uniform delay remaining = 134 Accumulated Delay = 0 373 ; Kick the dog : 374 ; Uniform delay remaining = 134 Accumulated Delay = 0 375 ; watch_dog_reset 376 048 0064 clrwdt 377 ; Uniform delay remaining = 133 Accumulated Delay = 1 378 ; Uniform delay remaining = 133 Accumulated Delay = 1 379 ; channel := {{ counter >> 1 }} & 3 380 049 1003 bcf c___byte,c___bit 381 04a 0c37 rrf delay__counter,w 382 04b 3903 andlw 3 383 04c 00b2 movwf delay__channel 384 ; Uniform delay remaining = 129 Accumulated Delay = 5 385 ; counter := counter + 1 386 04d 0ab7 incf delay__counter,f 387 ; Uniform delay remaining = 128 Accumulated Delay = 6 388 ; if { counter @ 0 } start 389 ; Alias variable for select counter @ 0 390 0037 delay__counter__152select0 equ delay__counter+0 391 0037 delay__counter__152select0__byte equ delay__counter+0 392 0000 delay__counter__152select0__bit equ 0 393 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=40 false_delay=108 true_size=41 false_size=68 394 04e 1c37 btfss delay__counter__152select0__byte,delay__counter__152select0__bit 395 04f 287e goto label152__1false 396 label152__1true: 397 ; if { counter @ 0 } body start 398 ; Uniform delay remaining = 128 Accumulated Delay = 0 399 ; Set up and wait for acquistion : 400 ; Uniform delay remaining = 128 Accumulated Delay = 0 401 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 402 050 0d32 rlf delay__channel,w 403 051 00b9 movwf delay__154byte0 404 052 0db9 rlf delay__154byte0,f 405 053 0d39 rlf delay__154byte0,w 406 054 39f8 andlw 248 407 055 3918 andlw 24 408 056 3841 iorlw 65 409 057 009f movwf addcon0 410 ; Uniform delay remaining = 120 Accumulated Delay = 8 411 ; Setup for interrupts : 412 ; Uniform delay remaining = 120 Accumulated Delay = 8 413 ; previous := current 414 058 0833 movf delay__current,w 415 059 00b5 movwf delay__previous 416 ; Uniform delay remaining = 118 Accumulated Delay = 10 417 ; Read the I / O port once : 418 ; Uniform delay remaining = 118 Accumulated Delay = 10 419 ; current := inputs ^ complement 420 05a 082c movf inputs,w 421 05b 062d xorwf complement,w 422 05c 00b3 movwf delay__current 423 ; Uniform delay remaining = 115 Accumulated Delay = 13 424 ; not_current := current ^ 0xf 425 05d 300f movlw 15 426 05e 0633 xorwf delay__current,w 427 05f 00b6 movwf delay__not_current 428 ; Uniform delay remaining = 112 Accumulated Delay = 16 429 ; changed := current ^ previous 430 060 0833 movf delay__current,w 431 061 0635 xorwf delay__previous,w 432 062 00b4 movwf delay__changed 433 ; Uniform delay remaining = 109 Accumulated Delay = 19 434 ; Uniform delay remaining = 109 Accumulated Delay = 19 435 ; See about triggering the interrupt_pending flag : 436 ; Uniform delay remaining = 109 Accumulated Delay = 19 437 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start 438 063 0830 movf low,w 439 064 0536 andwf delay__not_current,w 440 065 00b9 movwf delay__163byte0 441 066 082f movf high,w 442 067 0533 andwf delay__current,w 443 068 04b9 iorwf delay__163byte0,f 444 069 0834 movf delay__changed,w 445 06a 0533 andwf delay__current,w 446 06b 0531 andwf raising,w 447 06c 04b9 iorwf delay__163byte0,f 448 06d 0834 movf delay__changed,w 449 06e 0536 andwf delay__not_current,w 450 06f 052e andwf falling,w 451 070 0439 iorwf delay__163byte0,w 452 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 453 071 1d03 btfss z___byte,z___bit 454 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start 455 ; Uniform delay remaining = 109 Accumulated Delay = 0 456 ; interrupt_pending := 1 457 072 14c0 bsf interrupt_pending__byte,interrupt_pending__bit 458 ; Uniform delay remaining = 108 Accumulated Delay = 1 459 ; Uniform delay remaining = 108 Accumulated Delay = 1 460 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end 461 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 462 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 463 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end 464 ; Uniform delay remaining = 93 Accumulated Delay = 35 465 ; Uniform delay remaining = 93 Accumulated Delay = 35 466 ; Send an interrupt if interrupts are enabled : 467 ; Uniform delay remaining = 93 Accumulated Delay = 35 468 ; if { interrupt_pending && interrupt_enable } start 469 ; expression=`interrupt_pending' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 470 073 18c0 btfsc interrupt_pending__byte,interrupt_pending__bit 471 074 2877 goto label168__2true 472 label168__2false: 473 ; Delay 1 cycles 474 075 0000 nop 475 076 2879 goto and168__0false 476 label168__2true: 477 ; expression=`interrupt_enable' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 478 077 1840 btfsc interrupt_enable__byte,interrupt_enable__bit 479 and168__0true: 480 ; if { interrupt_pending && interrupt_enable } body start 481 ; Uniform delay remaining = 93 Accumulated Delay = 0 482 ; Shove serial out to low : 483 ; Uniform delay remaining = 93 Accumulated Delay = 0 484 ; serial_out := 0 485 078 1285 bcf serial_out__byte,serial_out__bit 486 ; Uniform delay remaining = 92 Accumulated Delay = 1 487 ; Uniform delay remaining = 92 Accumulated Delay = 1 488 ; if { interrupt_pending && interrupt_enable } body end 489 ; if exp=`interrupt_enable' false skip delay=2 490 ; Other expression=`interrupt_enable' delay=2 491 ; if exp=`interrupt_pending' total delay=5 492 ; if exp=`interrupt_pending' generic 493 label168__2end: 494 ; Other expression=`interrupt_pending' delay=5 495 and168__0false: 496 and168__0end: 497 ; if { interrupt_pending && interrupt_enable } end 498 ; Uniform delay remaining = 88 Accumulated Delay = 40 499 ; Uniform delay remaining = 88 Accumulated Delay = 40 500 ; if { counter @ 0 } body end 501 ; Delay 67 cycles 502 079 3016 movlw 22 503 07a 00b9 movwf delay__152byte3 504 delay__152delay2: 505 07b 0bb9 decfsz delay__152byte3,f 506 07c 287b goto delay__152delay2 507 07d 28c2 goto label152__1end 508 label152__1false: 509 ; else body start 510 ; Uniform delay remaining = 128 Accumulated Delay = 0 511 ; Start the conversion : 512 ; Uniform delay remaining = 128 Accumulated Delay = 0 513 ; go_done := 1 514 07e 151f bsf go_done__byte,go_done__bit 515 ; Uniform delay remaining = 127 Accumulated Delay = 1 516 ; if { channel = 0 } start 517 07f 0832 movf delay__channel,w 518 ; expression=`{ channel = 0 }' exp_delay=1 true_delay=1 false_delay=10 true_size=1 false_size=15 519 080 1d03 btfss z___byte,z___bit 520 081 2889 goto label175__0false 521 label175__0true: 522 ; if { channel = 0 } body start 523 ; Uniform delay remaining = 127 Accumulated Delay = 0 524 ; mask := 1 525 082 3001 movlw 1 526 ; 1 instructions found for sharing 527 ; Uniform delay remaining = 125 Accumulated Delay = 2 528 ; if { channel = 0 } body end 529 ; Delay 8 cycles 530 083 3002 movlw 2 531 084 00b9 movwf delay__175byte2 532 delay__175delay1: 533 085 0bb9 decfsz delay__175byte2,f 534 086 2885 goto delay__175delay1 535 087 0000 nop 536 088 2898 goto label175__0end 537 label175__0false: 538 089 0332 decf delay__channel,w 539 ; expression=`{ channel = 1 }' exp_delay=1 true_delay=1 false_delay=6 true_size=1 false_size=6 540 08a 1d03 btfss z___byte,z___bit 541 08b 2892 goto label177__0false 542 label177__0true: 543 ; else_if { channel = 1 } body start 544 ; Uniform delay remaining = 127 Accumulated Delay = 0 545 ; mask := 2 546 08c 3002 movlw 2 547 ; 1 instructions found for sharing 548 ; Uniform delay remaining = 125 Accumulated Delay = 2 549 ; else_if { channel = 1 } body end 550 ; Delay 4 cycles 551 08d 0000 nop 552 08e 0000 nop 553 08f 0000 nop 554 090 0000 nop 555 091 2898 goto label177__0end 556 label177__0false: 557 092 3002 movlw 2 558 093 0232 subwf delay__channel,w 559 ; expression=`{ channel = 2 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 560 094 1903 btfsc z___byte,z___bit 561 ; else_if { channel = 2 } body start 562 ; Uniform delay remaining = 127 Accumulated Delay = 0 563 ; mask := 4 564 095 3004 movlw 4 565 ; 1 instructions found for sharing 566 ; Uniform delay remaining = 125 Accumulated Delay = 2 567 ; else_if { channel = 2 } body end 568 096 1d03 btfss z___byte,z___bit 569 ; else body start 570 ; Uniform delay remaining = 127 Accumulated Delay = 0 571 ; mask := 8 572 097 3008 movlw 8 573 ; 1 instructions found for sharing 574 ; Uniform delay remaining = 125 Accumulated Delay = 2 575 ; else body end 576 ; if exp=` channel = 2 ' single true and false skip delay=6 577 ; Other expression=`{ channel = 2 }' delay=6 578 ; 1 shared instructions follow 579 ; 1 instructions found for sharing 580 ; if exp=` channel = 1 ' total delay=10 581 ; if exp=` channel = 1 ' generic 582 label177__0end: 583 ; Other expression=`{ channel = 1 }' delay=10 584 ; 1 shared instructions follow 585 ; 1 instructions found for sharing 586 ; if exp=` channel = 0 ' total delay=14 587 ; if exp=` channel = 0 ' generic 588 label175__0end: 589 ; Other expression=`{ channel = 0 }' delay=14 590 ; 1 shared instructions follow 591 098 00b8 movwf delay__mask 592 ; if { channel = 0 } end 593 ; Uniform delay remaining = 112 Accumulated Delay = 16 594 ; Delaying 60 uS is way longer than necessary for the conversion 595 ; Uniform delay remaining = 112 Accumulated Delay = 16 596 ; to complete . 597 ; Uniform delay remaining = 112 Accumulated Delay = 16 598 ; nop 60 599 ; Delay 60 cycles 600 099 3013 movlw 19 601 09a 00b9 movwf delay__186byte1 602 delay__186delay0: 603 09b 0bb9 decfsz delay__186byte1,f 604 09c 289b goto delay__186delay0 605 09d 0000 nop 606 09e 0000 nop 607 ; Uniform delay remaining = 52 Accumulated Delay = 76 608 ; analogs ~~ {{ channel }} := addres 609 09f 081e movf addres,w 610 0a0 00b9 movwf delay__187byte0 611 0a1 3020 movlw LOW analogs 612 0a2 0732 addwf delay__channel,w 613 0a3 0084 movwf fsr___register 614 0a4 0839 movf delay__187byte0,w 615 0a5 0080 movwf indf___register 616 ; Uniform delay remaining = 45 Accumulated Delay = 83 617 ; if { addres < thresholds_low ~~ {{ channel }} } start 618 0a6 3024 movlw LOW thresholds_low 619 0a7 0732 addwf delay__channel,w 620 0a8 0084 movwf fsr___register 621 0a9 0800 movf indf___register,w 622 0aa 021e subwf addres,w 623 ; expression=`{ addres < thresholds_low ~~ {{ channel }} }' exp_delay=5 true_delay=3 false_delay=0 true_size=3 false_size=0 624 0ab 1c03 btfss c___byte,c___bit 625 0ac 28b0 goto label188__0true 626 label188__0false: 627 ; Delay 2 cycles 628 0ad 0000 nop 629 0ae 0000 nop 630 0af 28b3 goto label188__0end 631 label188__0true: 632 ; if { addres < thresholds_low ~~ {{ channel }} } body start 633 ; Uniform delay remaining = 45 Accumulated Delay = 0 634 ; inputs := inputs & {{ mask ^ io_mask }} 635 0b0 300f movlw 15 636 0b1 0638 xorwf delay__mask,w 637 0b2 05ac andwf inputs,f 638 ; Uniform delay remaining = 42 Accumulated Delay = 3 639 ; Uniform delay remaining = 42 Accumulated Delay = 3 640 ; if { addres < thresholds_low ~~ {{ channel }} } body end 641 ; if exp=` addres < thresholds_low ~~ {{ channel }} ' total delay=11 642 ; if exp=` addres < thresholds_low ~~ {{ channel }} ' generic 643 label188__0end: 644 ; Other expression=`{ addres < thresholds_low ~~ {{ channel }} }' delay=11 645 ; if { addres < thresholds_low ~~ {{ channel }} } end 646 ; Uniform delay remaining = 34 Accumulated Delay = 94 647 ; if { addres > thresholds_high ~~ {{ channel }} } start 648 0b3 3028 movlw LOW thresholds_high 649 0b4 0732 addwf delay__channel,w 650 0b5 0084 movwf fsr___register 651 0b6 0800 movf indf___register,w 652 0b7 021e subwf addres,w 653 0b8 1d03 btfss z___byte,z___bit 654 0b9 1403 bsf c___byte,c___bit 655 ; expression=`{ addres > thresholds_high ~~ {{ channel }} }' exp_delay=7 true_delay=2 false_delay=0 true_size=2 false_size=0 656 0ba 1803 btfsc c___byte,c___bit 657 0bb 28be goto label191__0true 658 label191__0false: 659 ; Delay 1 cycles 660 0bc 0000 nop 661 0bd 28c0 goto label191__0end 662 label191__0true: 663 ; if { addres > thresholds_high ~~ {{ channel }} } body start 664 ; Uniform delay remaining = 34 Accumulated Delay = 0 665 ; inputs := inputs | mask 666 0be 0838 movf delay__mask,w 667 0bf 04ac iorwf inputs,f 668 ; Uniform delay remaining = 32 Accumulated Delay = 2 669 ; Uniform delay remaining = 32 Accumulated Delay = 2 670 ; if { addres > thresholds_high ~~ {{ channel }} } body end 671 ; if exp=` addres > thresholds_high ~~ {{ channel }} ' total delay=12 672 ; if exp=` addres > thresholds_high ~~ {{ channel }} ' generic 673 label191__0end: 674 ; Other expression=`{ addres > thresholds_high ~~ {{ channel }} }' delay=12 675 ; if { addres > thresholds_high ~~ {{ channel }} } end 676 ; Uniform delay remaining = 22 Accumulated Delay = 106 677 ; inputs := inputs & io_mask 678 0c0 300f movlw 15 679 0c1 05ac andwf inputs,f 680 ; Uniform delay remaining = 20 Accumulated Delay = 108 681 ; Uniform delay remaining = 20 Accumulated Delay = 108 682 ; else body end 683 ; if exp=` counter @ 0 ' total delay=111 684 ; if exp=` counter @ 0 ' generic 685 label152__1end: 686 ; Other expression=`{ counter @ 0 }' delay=111 687 ; if { counter @ 0 } end 688 ; Uniform delay remaining = 17 Accumulated Delay = 117 689 ; Uniform delay remaining = 17 Accumulated Delay = 117 690 ; Soak up remaining 17 cycles 691 ; Delay 17 cycles 692 0c2 3005 movlw 5 693 0c3 00b9 movwf delay__131byte1 694 delay__131delay0: 695 0c4 0bb9 decfsz delay__131byte1,f 696 0c5 28c4 goto delay__131delay0 697 0c6 0000 nop 698 ; procedure delay end 699 0c7 3400 retlw 0 700 ; optimize 1 701 702 ; procedure get_byte start 703 get_byte: 704 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 705 ; Procedure must be called with PCLATH set to code bank 0 706 003b get_byte__variables__base equ global__variables__bank0+27 707 003b get_byte__bytes__base equ get_byte__variables__base+0 708 003e get_byte__bits__base equ get_byte__variables__base+3 709 0003 get_byte__total__bytes equ 3 710 ; arguments_none 711 003b get_byte__0return__byte equ get_byte__bytes__base+0 712 ; Wait for a character and return it . 713 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 714 ; way the next call to get_byte < > will sychronize on the start 715 ; bit instead of possibly starting a little later . 716 003c get_byte__count equ get_byte__bytes__base+1 717 003d get_byte__char equ get_byte__bytes__base+2 718 ; Wait for start bit : 719 ; receiving := 1 720 0c8 1540 bsf receiving__byte,receiving__bit 721 ; `while serial_in ...' start 722 get_byte__214while__continue: 723 ; expression=`serial_in' exp_delay=0 true_delay=139 false_delay=2 true_size=2 false_size=1 724 0c9 1d85 btfss serial_in__byte,serial_in__bit 725 0ca 28cd goto get_byte__214while__break 726 ; call delay {{ }} 727 0cb 2048 call delay 728 0cc 28c9 goto get_byte__214while__continue 729 ; if exp=`serial_in' false goto 730 ; Other expression=`serial_in' delay=-1 731 get_byte__214while__break: 732 ; `while serial_in ...' end 733 ; Clear interrupts and interrupt pending : 734 ; interrupt_enable := 0 735 0cd 1040 bcf interrupt_enable__byte,interrupt_enable__bit 736 ; Skip over start bit : 737 ; call delay {{ }} 738 0ce 2048 call delay 739 ; call delay {{ }} 740 0cf 2048 call delay 741 ; call delay {{ }} 742 0d0 2048 call delay 743 ; Sample in the middle third of each data bit : 744 ; char := 0 745 0d1 01bd clrf get_byte__char 746 ; `count_down count 8 ...' start 747 0d2 3008 movlw 8 748 0d3 00bc movwf get_byte__count 749 get_byte__228_loop: 750 ; call delay {{ }} 751 0d4 2048 call delay 752 ; char := char >> 1 753 0d5 1003 bcf c___byte,c___bit 754 0d6 0cbd rrf get_byte__char,f 755 ; if { serial_in } start 756 ; expression=`{ serial_in }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 757 0d7 1d85 btfss serial_in__byte,serial_in__bit 758 0d8 28db goto label231__0end 759 ; if { serial_in } body start 760 ; char := char | 0x80 761 0d9 3080 movlw 128 762 0da 04bd iorwf get_byte__char,f 763 ; if { serial_in } body end 764 label231__0end: 765 ; if exp=`serial_in' empty false 766 ; Other expression=`{ serial_in }' delay=-1 767 ; if { serial_in } end 768 ; call delay {{ }} 769 0db 2048 call delay 770 ; call delay {{ }} 771 0dc 2048 call delay 772 0dd 0bbc decfsz get_byte__count,f 773 0de 28d4 goto get_byte__228_loop 774 get_byte__228_done: 775 ; `count_down count 8 ...' end 776 ; Skip over 2 / 3 ' s of stop bit : 777 ; call delay {{ }} 778 0df 2048 call delay 779 ; call delay {{ }} 780 0e0 2048 call delay 781 ; return char 782 0e1 083d movf get_byte__char,w 783 0e2 00bb movwf get_byte__0return__byte 784 0e3 3400 retlw 0 785 ; procedure get_byte end 786 787 ; procedure send_byte start 788 send_byte: 789 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 790 ; Procedure must be called with PCLATH set to code bank 0 791 003e send_byte__variables__base equ global__variables__bank0+30 792 003e send_byte__bytes__base equ send_byte__variables__base+0 793 0040 send_byte__bits__base equ send_byte__variables__base+2 794 0002 send_byte__total__bytes equ 2 795 003e send_byte__char equ send_byte__bytes__base+0 796 ; Send < char > to < tx > : 797 003f send_byte__count equ send_byte__bytes__base+1 798 ; < receiving > will be 1 if the last get / put routine was a get . 799 ; Before we start transmitting a response back , we want to ensure 800 ; that there has been enough time to turn the line line around . 801 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 802 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 803 ; for good measure . Technically , the second call to delay < > 804 ; is not really needed . 805 ; if { receiving } start 806 ; expression=`{ receiving }' exp_delay=0 true_delay=275 false_delay=0 true_size=3 false_size=0 807 0e4 1d40 btfss receiving__byte,receiving__bit 808 0e5 28e9 goto label260__0end 809 ; if { receiving } body start 810 ; receiving := 0 811 0e6 1140 bcf receiving__byte,receiving__bit 812 ; call delay {{ }} 813 0e7 2048 call delay 814 ; call delay {{ }} 815 0e8 2048 call delay 816 ; if { receiving } body end 817 label260__0end: 818 ; if exp=`receiving' empty false 819 ; Other expression=`{ receiving }' delay=-1 820 ; if { receiving } end 821 ; Send the start bit : 822 ; serial_out := 0 823 0e9 1285 bcf serial_out__byte,serial_out__bit 824 ; call delay {{ }} 825 0ea 2048 call delay 826 ; call delay {{ }} 827 0eb 2048 call delay 828 ; call delay {{ }} 829 0ec 2048 call delay 830 ; Send the data : 831 ; `count_down count 8 ...' start 832 0ed 3008 movlw 8 833 0ee 00bf movwf send_byte__count 834 send_byte__273_loop: 835 ; serial_out := char @ 0 836 ; Alias variable for select char @ 0 837 003e send_byte__char__274select0 equ send_byte__char+0 838 003e send_byte__char__274select0__byte equ send_byte__char+0 839 0000 send_byte__char__274select0__bit equ 0 840 0ef 1c3e btfss send_byte__char__274select0__byte,send_byte__char__274select0__bit 841 0f0 1285 bcf serial_out__byte,serial_out__bit 842 0f1 183e btfsc send_byte__char__274select0__byte,send_byte__char__274select0__bit 843 0f2 1685 bsf serial_out__byte,serial_out__bit 844 ; char := char >> 1 845 0f3 1003 bcf c___byte,c___bit 846 0f4 0cbe rrf send_byte__char,f 847 ; call delay {{ }} 848 0f5 2048 call delay 849 ; call delay {{ }} 850 0f6 2048 call delay 851 ; call delay {{ }} 852 0f7 2048 call delay 853 0f8 0bbf decfsz send_byte__count,f 854 0f9 28ef goto send_byte__273_loop 855 send_byte__273_done: 856 ; `count_down count 8 ...' end 857 ; Send the stop bit : 858 ; serial_out := 1 859 0fa 1685 bsf serial_out__byte,serial_out__bit 860 ; call delay {{ }} 861 0fb 2048 call delay 862 ; call delay {{ }} 863 0fc 2048 call delay 864 ; call delay {{ }} 865 0fd 2048 call delay 866 ; procedure send_byte end 867 0fe 3400 retlw 0 868 ; origin 0x200 869 org 512 870 ; bank 1 871 ; Default register bank is now 1 872 ; comment {The main routine can span the 256 byte boundary :} 873 874 ; procedure main start 875 main: 876 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 877 ; Procedure must be called with PCLATH set to code bank 0 878 00a0 main__variables__base equ global__variables__bank1+0 879 00a0 main__bytes__base equ main__variables__base+0 880 00a6 main__bits__base equ main__variables__base+6 881 0006 main__total__bytes equ 6 882 00a5 main__449byte0 equ main__bytes__base+5 883 00a5 main__399byte0 equ main__bytes__base+5 884 00a5 main__333byte0 equ main__bytes__base+5 885 00a5 main__442byte0 equ main__bytes__base+5 886 00a5 main__403byte0 equ main__bytes__base+5 887 00a5 main__388byte0 equ main__bytes__base+5 888 00a5 main__336byte0 equ main__bytes__base+5 889 ; arguments_none 890 00a0 main__bit equ main__bytes__base+0 891 00a1 main__command equ main__bytes__base+1 892 00a2 main__glitch equ main__bytes__base+2 893 00a3 main__id_index equ main__bytes__base+3 894 00a4 main__result equ main__bytes__base+4 895 ; Let ROOT = http : / / web . gramlich . com / projects / robobricks . 896 ; For InOut4A specific commands see : 897 ; ROOT / InOut4 / rev_a / index . html 898 ; For shared commands see : 899 ; ROOT / specifications . html # Software_Protocol 900 ; For shared interruptcommands see : 901 ; ROOT / specifications . html # Interrupts 902 ; Initialize the A / D module : 903 ; addcon1 := 0 904 200 019f clrf addcon1 905 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : 906 ; addcon0 := 0x41 907 201 3041 movlw 65 908 ; Switch from register bank 1 to register bank 0 (which contains addcon0) 909 202 1283 bcf rp0___byte,rp0___bit 910 ; Register bank is now 0 911 203 009f movwf addcon0 912 ; adif := 0 913 204 130c bcf adif__byte,adif__bit 914 ; adie := 0 915 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) 916 205 1683 bsf rp0___byte,rp0___bit 917 ; Register bank is now 1 918 206 130c bcf adie__byte,adie__bit 919 ; gie := 0 920 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) 921 207 1283 bcf rp0___byte,rp0___bit 922 ; Register bank is now 0 923 208 138b bcf gie__byte,gie__bit 924 ; Set the direction : 925 ; interrupt_enable := 0 926 209 1040 bcf interrupt_enable__byte,interrupt_enable__bit 927 ; interrupt_pending := 0 928 20a 10c0 bcf interrupt_pending__byte,interrupt_pending__bit 929 ; falling := 0 930 20b 01ae clrf falling 931 ; high := 0 932 20c 01af clrf high 933 ; low := 0 934 20d 01b0 clrf low 935 ; raising := 0 936 20e 01b1 clrf raising 937 ; glitch := 0 938 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) 939 20f 1683 bsf rp0___byte,rp0___bit 940 ; Register bank is now 1 941 210 01a2 clrf main__glitch 942 ; id_index := 0 943 211 01a3 clrf main__id_index 944 ; loop_forever ... start 945 main__328loop__forever: 946 ; Wait for a command : 947 ; command := get_byte {{ }} 948 ; Switch from register bank 1 to register bank 0 949 212 1283 bcf rp0___byte,rp0___bit 950 ; Register bank is now 0 951 213 20c8 call get_byte 952 214 083b movf get_byte__0return__byte,w 953 ; Switch from register bank 0 to register bank 1 (which contains main__command) 954 215 1683 bsf rp0___byte,rp0___bit 955 ; Register bank is now 1 956 216 00a1 movwf main__command 957 ; Dispatch on command : 958 ; switch { command >> 6 } 959 217 3002 movlw HIGH switch__333block_start 960 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 961 218 1283 bcf rp0___byte,rp0___bit 962 ; Register bank is now 0 963 219 008a movwf pclath___register 964 ; Switch from register bank 0 to register bank 1 (which contains main__command) 965 21a 1683 bsf rp0___byte,rp0___bit 966 ; Register bank is now 1 967 21b 0e21 swapf main__command,w 968 21c 00a5 movwf main__333byte0 969 21d 0ca5 rrf main__333byte0,f 970 21e 0c25 rrf main__333byte0,w 971 21f 3903 andlw 3 972 ; case 0 973 ; case 1 974 ; case 2 975 ; case 3 976 switch__333block_start: 977 220 0782 addwf pcl___register,f 978 221 2a25 goto switch__333block334 979 222 2ad0 goto switch__333block416 980 223 2af7 goto switch__333block437 981 224 2af8 goto switch__333block440 982 switch__333block_end: 983 ; switch_check 333 switch__333block_start switch__333block_end 984 switch__333block334: 985 ; Command = 00 xx xxxx : 986 ; switch { command >> 3 } 987 225 3002 movlw HIGH switch__336block_start 988 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 989 226 1283 bcf rp0___byte,rp0___bit 990 ; Register bank is now 0 991 227 008a movwf pclath___register 992 ; Switch from register bank 0 to register bank 1 (which contains main__command) 993 228 1683 bsf rp0___byte,rp0___bit 994 ; Register bank is now 1 995 229 0c21 rrf main__command,w 996 22a 00a5 movwf main__336byte0 997 22b 0ca5 rrf main__336byte0,f 998 22c 0c25 rrf main__336byte0,w 999 22d 391f andlw 31 1000 ; case 0 1001 ; case 1 1002 ; case 2 3 1003 ; case 4 5 1004 switch__336block_start: 1005 22e 0782 addwf pcl___register,f 1006 22f 2a37 goto switch__336block337 1007 230 2a5d goto switch__336block357 1008 231 2a90 goto switch__336block385 1009 232 2a90 goto switch__336block385 1010 233 2ac8 goto switch__336block407 1011 234 2ac8 goto switch__336block407 1012 235 2acf goto switch__336default411 1013 236 2acf goto switch__336default411 1014 switch__336block_end: 1015 ; switch_check 336 switch__336block_start switch__336block_end 1016 switch__336block337: 1017 ; Command = 0000 0 xxx : 1018 ; switch { command & 7 } 1019 237 3002 movlw HIGH switch__339block_start 1020 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1021 238 1283 bcf rp0___byte,rp0___bit 1022 ; Register bank is now 0 1023 239 008a movwf pclath___register 1024 23a 3007 movlw 7 1025 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1026 23b 1683 bsf rp0___byte,rp0___bit 1027 ; Register bank is now 1 1028 23c 0521 andwf main__command,w 1029 ; case 0 1 2 3 1030 ; case 4 1031 ; case 5 1032 switch__339block_start: 1033 23d 0782 addwf pcl___register,f 1034 23e 2a46 goto switch__339block340 1035 23f 2a46 goto switch__339block340 1036 240 2a46 goto switch__339block340 1037 241 2a46 goto switch__339block340 1038 242 2a4f goto switch__339block344 1039 243 2a56 goto switch__339block348 1040 244 2a5c goto switch__339default352 1041 245 2a5c goto switch__339default352 1042 switch__339block_end: 1043 ; switch_check 339 switch__339block_start switch__339block_end 1044 switch__339block340: 1045 ; Read Pin < Command = 0000 00 bb > : 1046 ; call send_byte {{ analogs ~~ {{ command }} }} 1047 246 3020 movlw LOW analogs 1048 247 0721 addwf main__command,w 1049 248 0084 movwf fsr___register 1050 249 0800 movf indf___register,w 1051 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1052 24a 1283 bcf rp0___byte,rp0___bit 1053 ; Register bank is now 0 1054 24b 00be movwf send_byte__char 1055 24c 20e4 call send_byte 1056 ; Switch from register bank 0 to register bank 1 1057 24d 1683 bsf rp0___byte,rp0___bit 1058 ; Register bank is now 1 1059 24e 2a5c goto switch__339end 1060 switch__339block344: 1061 ; Read Binary Values < Command = 0000 0100 > : 1062 ; call send_byte {{ inputs ^ complement }} 1063 ; Switch from register bank 1 to register bank 0 (which contains inputs) 1064 24f 1283 bcf rp0___byte,rp0___bit 1065 ; Register bank is now 0 1066 250 082c movf inputs,w 1067 251 062d xorwf complement,w 1068 252 00be movwf send_byte__char 1069 253 20e4 call send_byte 1070 ; Switch from register bank 0 to register bank 1 1071 254 1683 bsf rp0___byte,rp0___bit 1072 ; Register bank is now 1 1073 255 2a5c goto switch__339end 1074 switch__339block348: 1075 ; Read Raw Binary < Command = 0000 0101 > : 1076 ; call send_byte {{ inputs }} 1077 ; Switch from register bank 1 to register bank 0 (which contains inputs) 1078 256 1283 bcf rp0___byte,rp0___bit 1079 ; Register bank is now 0 1080 257 082c movf inputs,w 1081 258 00be movwf send_byte__char 1082 259 20e4 call send_byte 1083 ; Switch from register bank 0 to register bank 1 1084 25a 1683 bsf rp0___byte,rp0___bit 1085 ; Register bank is now 1 1086 25b 2a5c goto switch__339end 1087 switch__339default352: 1088 ; Undefine command : 1089 switch__339end: 1090 25c 2acf goto switch__336end 1091 switch__336block357: 1092 ; Command = 0000 1 xxx : 1093 ; switch { command & 7 } 1094 25d 3002 movlw HIGH switch__359block_start 1095 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1096 25e 1283 bcf rp0___byte,rp0___bit 1097 ; Register bank is now 0 1098 25f 008a movwf pclath___register 1099 260 3007 movlw 7 1100 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1101 261 1683 bsf rp0___byte,rp0___bit 1102 ; Register bank is now 1 1103 262 0521 andwf main__command,w 1104 ; case 0 1105 ; case 1 1106 ; case 2 1107 ; case 3 1108 ; case 4 1109 switch__359block_start: 1110 263 0782 addwf pcl___register,f 1111 264 2a6c goto switch__359block360 1112 265 2a73 goto switch__359block364 1113 266 2a7a goto switch__359block368 1114 267 2a81 goto switch__359block372 1115 268 2a88 goto switch__359block376 1116 269 2a8f goto switch__359default380 1117 26a 2a8f goto switch__359default380 1118 26b 2a8f goto switch__359default380 1119 switch__359block_end: 1120 ; switch_check 359 switch__359block_start switch__359block_end 1121 switch__359block360: 1122 ; Set Complement Mask < Command = 0000 1000 > : 1123 ; complement := get_byte {{ }} & io_mask 1124 ; Switch from register bank 1 to register bank 0 1125 26c 1283 bcf rp0___byte,rp0___bit 1126 ; Register bank is now 0 1127 26d 20c8 call get_byte 1128 26e 083b movf get_byte__0return__byte,w 1129 26f 390f andlw 15 1130 270 00ad movwf complement 1131 ; Switch from register bank 0 to register bank 1 1132 271 1683 bsf rp0___byte,rp0___bit 1133 ; Register bank is now 1 1134 272 2a8f goto switch__359end 1135 switch__359block364: 1136 ; Set High Mask < Command = 0000 1001 > : 1137 ; high := get_byte {{ }} & io_mask 1138 ; Switch from register bank 1 to register bank 0 1139 273 1283 bcf rp0___byte,rp0___bit 1140 ; Register bank is now 0 1141 274 20c8 call get_byte 1142 275 083b movf get_byte__0return__byte,w 1143 276 390f andlw 15 1144 277 00af movwf high 1145 ; Switch from register bank 0 to register bank 1 1146 278 1683 bsf rp0___byte,rp0___bit 1147 ; Register bank is now 1 1148 279 2a8f goto switch__359end 1149 switch__359block368: 1150 ; Set Low Mask < Command = 0000 1010 > : 1151 ; low := get_byte {{ }} & io_mask 1152 ; Switch from register bank 1 to register bank 0 1153 27a 1283 bcf rp0___byte,rp0___bit 1154 ; Register bank is now 0 1155 27b 20c8 call get_byte 1156 27c 083b movf get_byte__0return__byte,w 1157 27d 390f andlw 15 1158 27e 00b0 movwf low 1159 ; Switch from register bank 0 to register bank 1 1160 27f 1683 bsf rp0___byte,rp0___bit 1161 ; Register bank is now 1 1162 280 2a8f goto switch__359end 1163 switch__359block372: 1164 ; Set Raising Mask < Command = 0000 1011 > : 1165 ; raising := get_byte {{ }} & io_mask 1166 ; Switch from register bank 1 to register bank 0 1167 281 1283 bcf rp0___byte,rp0___bit 1168 ; Register bank is now 0 1169 282 20c8 call get_byte 1170 283 083b movf get_byte__0return__byte,w 1171 284 390f andlw 15 1172 285 00b1 movwf raising 1173 ; Switch from register bank 0 to register bank 1 1174 286 1683 bsf rp0___byte,rp0___bit 1175 ; Register bank is now 1 1176 287 2a8f goto switch__359end 1177 switch__359block376: 1178 ; Set Falling Mask < Command = 0000 1100 > : 1179 ; falling := get_byte {{ }} & io_mask 1180 ; Switch from register bank 1 to register bank 0 1181 288 1283 bcf rp0___byte,rp0___bit 1182 ; Register bank is now 0 1183 289 20c8 call get_byte 1184 28a 083b movf get_byte__0return__byte,w 1185 28b 390f andlw 15 1186 28c 00ae movwf falling 1187 ; Switch from register bank 0 to register bank 1 1188 28d 1683 bsf rp0___byte,rp0___bit 1189 ; Register bank is now 1 1190 28e 2a8f goto switch__359end 1191 switch__359default380: 1192 ; Undefined command : 1193 switch__359end: 1194 28f 2acf goto switch__336end 1195 switch__336block385: 1196 ; Command = 0001 0 xxx : 1197 ; bit := command & 3 1198 290 3003 movlw 3 1199 291 0521 andwf main__command,w 1200 292 00a0 movwf main__bit 1201 ; switch { {{ command >> 2 }} & 3 } 1202 293 3002 movlw HIGH switch__388block_start 1203 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1204 294 1283 bcf rp0___byte,rp0___bit 1205 ; Register bank is now 0 1206 295 008a movwf pclath___register 1207 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1208 296 1683 bsf rp0___byte,rp0___bit 1209 ; Register bank is now 1 1210 297 0c21 rrf main__command,w 1211 298 00a5 movwf main__388byte0 1212 299 0c25 rrf main__388byte0,w 1213 29a 3903 andlw 3 1214 ; case 0 1215 ; case 1 1216 ; case 2 1217 ; case 3 1218 switch__388block_start: 1219 29b 0782 addwf pcl___register,f 1220 29c 2aa0 goto switch__388block389 1221 29d 2aa9 goto switch__388block393 1222 29e 2ab2 goto switch__388block397 1223 29f 2abd goto switch__388block401 1224 switch__388block_end: 1225 ; switch_check 388 switch__388block_start switch__388block_end 1226 switch__388block389: 1227 ; Read High Threshold < Command = 0001 00 bb > : 1228 ; call send_byte {{ thresholds_high ~~ {{ bit }} }} 1229 2a0 3028 movlw LOW thresholds_high 1230 2a1 0720 addwf main__bit,w 1231 2a2 0084 movwf fsr___register 1232 2a3 0800 movf indf___register,w 1233 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1234 2a4 1283 bcf rp0___byte,rp0___bit 1235 ; Register bank is now 0 1236 2a5 00be movwf send_byte__char 1237 2a6 20e4 call send_byte 1238 ; Switch from register bank 0 to register bank 1 1239 2a7 1683 bsf rp0___byte,rp0___bit 1240 ; Register bank is now 1 1241 2a8 2ac7 goto switch__388end 1242 switch__388block393: 1243 ; Read Low Threshold < Command = 0001 01 bb > : 1244 ; call send_byte {{ thresholds_low ~~ {{ bit }} }} 1245 2a9 3024 movlw LOW thresholds_low 1246 2aa 0720 addwf main__bit,w 1247 2ab 0084 movwf fsr___register 1248 2ac 0800 movf indf___register,w 1249 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1250 2ad 1283 bcf rp0___byte,rp0___bit 1251 ; Register bank is now 0 1252 2ae 00be movwf send_byte__char 1253 2af 20e4 call send_byte 1254 ; Switch from register bank 0 to register bank 1 1255 2b0 1683 bsf rp0___byte,rp0___bit 1256 ; Register bank is now 1 1257 2b1 2ac7 goto switch__388end 1258 switch__388block397: 1259 ; Set High Threshold < Command = 0001 10 bb > : 1260 ; thresholds_high ~~ {{ bit }} := get_byte {{ }} 1261 ; Switch from register bank 1 to register bank 0 1262 2b2 1283 bcf rp0___byte,rp0___bit 1263 ; Register bank is now 0 1264 2b3 20c8 call get_byte 1265 2b4 083b movf get_byte__0return__byte,w 1266 ; Switch from register bank 0 to register bank 1 (which contains main__399byte0) 1267 2b5 1683 bsf rp0___byte,rp0___bit 1268 ; Register bank is now 1 1269 2b6 00a5 movwf main__399byte0 1270 2b7 3028 movlw LOW thresholds_high 1271 2b8 0720 addwf main__bit,w 1272 2b9 0084 movwf fsr___register 1273 2ba 0825 movf main__399byte0,w 1274 2bb 0080 movwf indf___register 1275 2bc 2ac7 goto switch__388end 1276 switch__388block401: 1277 ; Set Low Threshold < Command = 0001 11 bb > : 1278 ; thresholds_low ~~ {{ bit }} := get_byte {{ }} 1279 ; Switch from register bank 1 to register bank 0 1280 2bd 1283 bcf rp0___byte,rp0___bit 1281 ; Register bank is now 0 1282 2be 20c8 call get_byte 1283 2bf 083b movf get_byte__0return__byte,w 1284 ; Switch from register bank 0 to register bank 1 (which contains main__403byte0) 1285 2c0 1683 bsf rp0___byte,rp0___bit 1286 ; Register bank is now 1 1287 2c1 00a5 movwf main__403byte0 1288 2c2 3024 movlw LOW thresholds_low 1289 2c3 0720 addwf main__bit,w 1290 2c4 0084 movwf fsr___register 1291 2c5 0825 movf main__403byte0,w 1292 2c6 0080 movwf indf___register 1293 switch__388end: 1294 2c7 2acf goto switch__336end 1295 switch__336block407: 1296 ; Set Complement Mask < Command = 0001 cccc > : 1297 ; complement := get_byte {{ }} & io_mask 1298 ; Switch from register bank 1 to register bank 0 1299 2c8 1283 bcf rp0___byte,rp0___bit 1300 ; Register bank is now 0 1301 2c9 20c8 call get_byte 1302 2ca 083b movf get_byte__0return__byte,w 1303 2cb 390f andlw 15 1304 2cc 00ad movwf complement 1305 ; Switch from register bank 0 to register bank 1 1306 2cd 1683 bsf rp0___byte,rp0___bit 1307 ; Register bank is now 1 1308 2ce 2acf goto switch__336end 1309 switch__336default411: 1310 ; Undefined commands ; do nothing : 1311 switch__336end: 1312 2cf 2ba0 goto switch__333end 1313 switch__333block416: 1314 ; Command = 01 xx xxxx : 1315 ; switch { {{ command >> 4 }} & 3 } 1316 2d0 3002 movlw HIGH switch__418block_start 1317 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1318 2d1 1283 bcf rp0___byte,rp0___bit 1319 ; Register bank is now 0 1320 2d2 008a movwf pclath___register 1321 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1322 2d3 1683 bsf rp0___byte,rp0___bit 1323 ; Register bank is now 1 1324 2d4 0e21 swapf main__command,w 1325 2d5 3903 andlw 3 1326 ; case 0 1327 ; case 1 1328 ; case 2 1329 ; case 3 1330 switch__418block_start: 1331 2d6 0782 addwf pcl___register,f 1332 2d7 2adb goto switch__418block419 1333 2d8 2ae2 goto switch__418block423 1334 2d9 2ae9 goto switch__418block427 1335 2da 2af0 goto switch__418block431 1336 switch__418block_end: 1337 ; switch_check 418 switch__418block_start switch__418block_end 1338 switch__418block419: 1339 ; Set High Mask < Command = 0100 hhhh > : 1340 ; high := get_byte {{ }} & io_mask 1341 ; Switch from register bank 1 to register bank 0 1342 2db 1283 bcf rp0___byte,rp0___bit 1343 ; Register bank is now 0 1344 2dc 20c8 call get_byte 1345 2dd 083b movf get_byte__0return__byte,w 1346 2de 390f andlw 15 1347 2df 00af movwf high 1348 ; Switch from register bank 0 to register bank 1 1349 2e0 1683 bsf rp0___byte,rp0___bit 1350 ; Register bank is now 1 1351 2e1 2af6 goto switch__418end 1352 switch__418block423: 1353 ; Set Low Mask < Command = 0101 llll > : 1354 ; low := get_byte {{ }} & io_mask 1355 ; Switch from register bank 1 to register bank 0 1356 2e2 1283 bcf rp0___byte,rp0___bit 1357 ; Register bank is now 0 1358 2e3 20c8 call get_byte 1359 2e4 083b movf get_byte__0return__byte,w 1360 2e5 390f andlw 15 1361 2e6 00b0 movwf low 1362 ; Switch from register bank 0 to register bank 1 1363 2e7 1683 bsf rp0___byte,rp0___bit 1364 ; Register bank is now 1 1365 2e8 2af6 goto switch__418end 1366 switch__418block427: 1367 ; Set Raising Mask < Command = 0110 rrrr > : 1368 ; raising := get_byte {{ }} & io_mask 1369 ; Switch from register bank 1 to register bank 0 1370 2e9 1283 bcf rp0___byte,rp0___bit 1371 ; Register bank is now 0 1372 2ea 20c8 call get_byte 1373 2eb 083b movf get_byte__0return__byte,w 1374 2ec 390f andlw 15 1375 2ed 00b1 movwf raising 1376 ; Switch from register bank 0 to register bank 1 1377 2ee 1683 bsf rp0___byte,rp0___bit 1378 ; Register bank is now 1 1379 2ef 2af6 goto switch__418end 1380 switch__418block431: 1381 ; Set Falling Mask < Command = 0111 ffff > : 1382 ; falling := get_byte {{ }} & io_mask 1383 ; Switch from register bank 1 to register bank 0 1384 2f0 1283 bcf rp0___byte,rp0___bit 1385 ; Register bank is now 0 1386 2f1 20c8 call get_byte 1387 2f2 083b movf get_byte__0return__byte,w 1388 2f3 390f andlw 15 1389 2f4 00ae movwf falling 1390 ; Switch from register bank 0 to register bank 1 1391 2f5 1683 bsf rp0___byte,rp0___bit 1392 ; Register bank is now 1 1393 switch__418end: 1394 2f6 2ba0 goto switch__333end 1395 switch__333block437: 1396 ; Do nothing < Command = 10 xx xxxx > : 1397 2f7 2ba0 goto switch__333end 1398 switch__333block440: 1399 ; Command = 11 xx xxxx : 1400 ; switch { {{ command >> 3 }} & 7 } 1401 2f8 3003 movlw HIGH switch__442block_start 1402 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1403 2f9 1283 bcf rp0___byte,rp0___bit 1404 ; Register bank is now 0 1405 2fa 008a movwf pclath___register 1406 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1407 2fb 1683 bsf rp0___byte,rp0___bit 1408 ; Register bank is now 1 1409 2fc 0c21 rrf main__command,w 1410 2fd 00a5 movwf main__442byte0 1411 2fe 0ca5 rrf main__442byte0,f 1412 2ff 0c25 rrf main__442byte0,w 1413 300 3907 andlw 7 1414 ; case 0 1 2 3 4 1415 ; case 5 1416 ; case 6 1417 ; case 7 1418 switch__442block_start: 1419 301 0782 addwf pcl___register,f 1420 302 2b0a goto switch__442block443 1421 303 2b0a goto switch__442block443 1422 304 2b0a goto switch__442block443 1423 305 2b0a goto switch__442block443 1424 306 2b0a goto switch__442block443 1425 307 2b0b goto switch__442block447 1426 308 2b2b goto switch__442block461 1427 309 2b63 goto switch__442block479 1428 switch__442block_end: 1429 ; switch_check 442 switch__442block_start switch__442block_end 1430 switch__442block443: 1431 ; Command = 1100 xxxx or 1110 0 xxx : 1432 ; Do nothing : 1433 30a 2ba0 goto switch__442end 1434 switch__442block447: 1435 ; Read Interrupt Bits < Command = 1110 1111 > : 1436 ; if { {{ command & 7 }} = 7 } start 1437 30b 3007 movlw 7 1438 30c 0521 andwf main__command,w 1439 30d 00a5 movwf main__449byte0 1440 30e 3007 movlw 7 1441 30f 0225 subwf main__449byte0,w 1442 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 1443 310 1d03 btfss z___byte,z___bit 1444 311 2b2a goto label449__1end 1445 ; if { {{ command & 7 }} = 7 } body start 1446 ; Return Interrupt Bits : 1447 ; result := 0 1448 312 01a4 clrf main__result 1449 ; if { interrupt_enable } start 1450 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1451 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1452 313 1283 bcf rp0___byte,rp0___bit 1453 ; Register bank is now 0 1454 314 1103 bcf z___byte,z___bit 1455 315 1840 btfsc interrupt_enable__byte,interrupt_enable__bit 1456 316 1503 bsf z___byte,z___bit 1457 ; Switch from register bank 0 to register bank 1 1458 317 1683 bsf rp0___byte,rp0___bit 1459 ; Register bank is now 1 1460 318 1d03 btfss z___byte,z___bit 1461 319 2b1c goto label452__0end 1462 ; if { interrupt_enable } body start 1463 ; result := result | 2 1464 31a 3002 movlw 2 1465 31b 04a4 iorwf main__result,f 1466 ; if { interrupt_enable } body end 1467 label452__0end: 1468 ; if exp=`interrupt_enable' empty false 1469 ; Other expression=`{ interrupt_enable }' delay=-1 1470 ; if { interrupt_enable } end 1471 ; if { interrupt_pending } start 1472 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1473 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1474 31c 1283 bcf rp0___byte,rp0___bit 1475 ; Register bank is now 0 1476 31d 1103 bcf z___byte,z___bit 1477 31e 18c0 btfsc interrupt_pending__byte,interrupt_pending__bit 1478 31f 1503 bsf z___byte,z___bit 1479 ; Switch from register bank 0 to register bank 1 1480 320 1683 bsf rp0___byte,rp0___bit 1481 ; Register bank is now 1 1482 321 1d03 btfss z___byte,z___bit 1483 322 2b25 goto label455__0end 1484 ; if { interrupt_pending } body start 1485 ; result := result | 1 1486 323 3001 movlw 1 1487 324 04a4 iorwf main__result,f 1488 ; if { interrupt_pending } body end 1489 label455__0end: 1490 ; if exp=`interrupt_pending' empty false 1491 ; Other expression=`{ interrupt_pending }' delay=-1 1492 ; if { interrupt_pending } end 1493 ; call send_byte {{ result }} 1494 325 0824 movf main__result,w 1495 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1496 326 1283 bcf rp0___byte,rp0___bit 1497 ; Register bank is now 0 1498 327 00be movwf send_byte__char 1499 328 20e4 call send_byte 1500 ; if { {{ command & 7 }} = 7 } body end 1501 ; Switch from register bank 0 to register bank 1 1502 329 1683 bsf rp0___byte,rp0___bit 1503 ; Register bank is now 1 1504 label449__1end: 1505 ; if exp=` {{ command & 7 }} = 7 ' empty false 1506 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 1507 ; if { {{ command & 7 }} = 7 } end 1508 32a 2ba0 goto switch__442end 1509 switch__442block461: 1510 ; Shared Interrupt commands < Command = 1111 0 xxx > : 1511 ; switch { command & 7 } 1512 32b 3003 movlw HIGH switch__463block_start 1513 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1514 32c 1283 bcf rp0___byte,rp0___bit 1515 ; Register bank is now 0 1516 32d 008a movwf pclath___register 1517 32e 3007 movlw 7 1518 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1519 32f 1683 bsf rp0___byte,rp0___bit 1520 ; Register bank is now 1 1521 330 0521 andwf main__command,w 1522 ; case 0 1 2 3 1523 ; case 4 5 1524 ; case 6 7 1525 switch__463block_start: 1526 331 0782 addwf pcl___register,f 1527 332 2b3a goto switch__463block464 1528 333 2b3a goto switch__463block464 1529 334 2b3a goto switch__463block464 1530 335 2b3a goto switch__463block464 1531 336 2b4d goto switch__463block469 1532 337 2b4d goto switch__463block469 1533 338 2b58 goto switch__463block473 1534 339 2b58 goto switch__463block473 1535 switch__463block_end: 1536 ; switch_check 463 switch__463block_start switch__463block_end 1537 switch__463block464: 1538 ; Set interrupt bits < Command = 1111 10 ep > : 1539 ; interrupt_enable := command @ 1 1540 ; Alias variable for select command @ 1 1541 00a1 main__command__466select0 equ main__command+0 1542 00a1 main__command__466select0__byte equ main__command+0 1543 0001 main__command__466select0__bit equ 1 1544 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1545 33a 1283 bcf rp0___byte,rp0___bit 1546 ; Register bank is now 0 1547 33b 1040 bcf interrupt_enable__byte,interrupt_enable__bit 1548 ; Switch from register bank 0 to register bank 1 (which contains main__command__466select0__byte) 1549 33c 1683 bsf rp0___byte,rp0___bit 1550 ; Register bank is now 1 1551 33d 1103 bcf z___byte,z___bit 1552 33e 18a1 btfsc main__command__466select0__byte,main__command__466select0__bit 1553 33f 1503 bsf z___byte,z___bit 1554 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1555 340 1283 bcf rp0___byte,rp0___bit 1556 ; Register bank is now 0 1557 341 1903 btfsc z___byte,z___bit 1558 342 1440 bsf interrupt_enable__byte,interrupt_enable__bit 1559 ; interrupt_pending := command @ 0 1560 ; Alias variable for select command @ 0 1561 00a1 main__command__467select0 equ main__command+0 1562 00a1 main__command__467select0__byte equ main__command+0 1563 0000 main__command__467select0__bit equ 0 1564 343 10c0 bcf interrupt_pending__byte,interrupt_pending__bit 1565 ; Switch from register bank 0 to register bank 1 (which contains main__command__467select0__byte) 1566 344 1683 bsf rp0___byte,rp0___bit 1567 ; Register bank is now 1 1568 345 1103 bcf z___byte,z___bit 1569 346 1821 btfsc main__command__467select0__byte,main__command__467select0__bit 1570 347 1503 bsf z___byte,z___bit 1571 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1572 348 1283 bcf rp0___byte,rp0___bit 1573 ; Register bank is now 0 1574 349 1903 btfsc z___byte,z___bit 1575 34a 14c0 bsf interrupt_pending__byte,interrupt_pending__bit 1576 ; Switch from register bank 0 to register bank 1 1577 34b 1683 bsf rp0___byte,rp0___bit 1578 ; Register bank is now 1 1579 34c 2b62 goto switch__463end 1580 switch__463block469: 1581 ; Set Interrupt Pending < Command = 1111 110 p > : 1582 ; interrupt_pending := command @ 0 1583 ; Alias variable for select command @ 0 1584 00a1 main__command__471select0 equ main__command+0 1585 00a1 main__command__471select0__byte equ main__command+0 1586 0000 main__command__471select0__bit equ 0 1587 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1588 34d 1283 bcf rp0___byte,rp0___bit 1589 ; Register bank is now 0 1590 34e 10c0 bcf interrupt_pending__byte,interrupt_pending__bit 1591 ; Switch from register bank 0 to register bank 1 (which contains main__command__471select0__byte) 1592 34f 1683 bsf rp0___byte,rp0___bit 1593 ; Register bank is now 1 1594 350 1103 bcf z___byte,z___bit 1595 351 1821 btfsc main__command__471select0__byte,main__command__471select0__bit 1596 352 1503 bsf z___byte,z___bit 1597 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1598 353 1283 bcf rp0___byte,rp0___bit 1599 ; Register bank is now 0 1600 354 1903 btfsc z___byte,z___bit 1601 355 14c0 bsf interrupt_pending__byte,interrupt_pending__bit 1602 ; Switch from register bank 0 to register bank 1 1603 356 1683 bsf rp0___byte,rp0___bit 1604 ; Register bank is now 1 1605 357 2b62 goto switch__463end 1606 switch__463block473: 1607 ; Set Interrupt Enable < Command = 1110 111 e > : 1608 ; interrupt_enable := command @ 0 1609 ; Alias variable for select command @ 0 1610 00a1 main__command__475select0 equ main__command+0 1611 00a1 main__command__475select0__byte equ main__command+0 1612 0000 main__command__475select0__bit equ 0 1613 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1614 358 1283 bcf rp0___byte,rp0___bit 1615 ; Register bank is now 0 1616 359 1040 bcf interrupt_enable__byte,interrupt_enable__bit 1617 ; Switch from register bank 0 to register bank 1 (which contains main__command__475select0__byte) 1618 35a 1683 bsf rp0___byte,rp0___bit 1619 ; Register bank is now 1 1620 35b 1103 bcf z___byte,z___bit 1621 35c 1821 btfsc main__command__475select0__byte,main__command__475select0__bit 1622 35d 1503 bsf z___byte,z___bit 1623 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1624 35e 1283 bcf rp0___byte,rp0___bit 1625 ; Register bank is now 0 1626 35f 1903 btfsc z___byte,z___bit 1627 360 1440 bsf interrupt_enable__byte,interrupt_enable__bit 1628 ; Switch from register bank 0 to register bank 1 1629 361 1683 bsf rp0___byte,rp0___bit 1630 ; Register bank is now 1 1631 switch__463end: 1632 362 2ba0 goto switch__442end 1633 switch__442block479: 1634 ; Shared commands < Command = 1111 1 xxx > : 1635 ; switch { command & 7 } 1636 363 3003 movlw HIGH switch__481block_start 1637 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1638 364 1283 bcf rp0___byte,rp0___bit 1639 ; Register bank is now 0 1640 365 008a movwf pclath___register 1641 366 3007 movlw 7 1642 ; Switch from register bank 0 to register bank 1 (which contains main__command) 1643 367 1683 bsf rp0___byte,rp0___bit 1644 ; Register bank is now 1 1645 368 0521 andwf main__command,w 1646 ; case 0 1647 ; case 1 1648 ; case 2 1649 ; case 3 1650 ; case 4 1651 ; case 5 1652 ; case 6 1653 ; case 7 1654 switch__481block_start: 1655 369 0782 addwf pcl___register,f 1656 36a 2b72 goto switch__481block482 1657 36b 2b75 goto switch__481block486 1658 36c 2b78 goto switch__481block490 1659 36d 2b7e goto switch__481block494 1660 36e 2b83 goto switch__481block498 1661 36f 2b94 goto switch__481block509 1662 370 2b96 goto switch__481block513 1663 371 2b9d goto switch__481block518 1664 switch__481block_end: 1665 ; switch_check 481 switch__481block_start switch__481block_end 1666 switch__481block482: 1667 ; Clock Decrement < Command = 1111 1000 > : 1668 ; osccal := osccal - osccal_unit 1669 372 30f0 movlw 240 1670 373 0785 addwf osccal,f 1671 374 2ba0 goto switch__481end 1672 switch__481block486: 1673 ; Clock Increment < Command = 1111 1001 > : 1674 ; osccal := osccal + osccal_unit 1675 375 3010 movlw 16 1676 376 0785 addwf osccal,f 1677 377 2ba0 goto switch__481end 1678 switch__481block490: 1679 ; Clock Read < Command = 1111 1010 > : 1680 ; call send_byte {{ osccal }} 1681 378 0805 movf osccal,w 1682 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1683 379 1283 bcf rp0___byte,rp0___bit 1684 ; Register bank is now 0 1685 37a 00be movwf send_byte__char 1686 37b 20e4 call send_byte 1687 ; Switch from register bank 0 to register bank 1 1688 37c 1683 bsf rp0___byte,rp0___bit 1689 ; Register bank is now 1 1690 37d 2ba0 goto switch__481end 1691 switch__481block494: 1692 ; Clock Pulse < Command = 1111 1011 > : 1693 ; call send_byte {{ 0 }} 1694 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1695 37e 1283 bcf rp0___byte,rp0___bit 1696 ; Register bank is now 0 1697 37f 01be clrf send_byte__char 1698 380 20e4 call send_byte 1699 ; Switch from register bank 0 to register bank 1 1700 381 1683 bsf rp0___byte,rp0___bit 1701 ; Register bank is now 1 1702 382 2ba0 goto switch__481end 1703 switch__481block498: 1704 ; ID Next < Command = 1111 1100 > : 1705 ; if { id_index >= id . size } start 1706 383 3033 movlw 51 1707 384 0223 subwf main__id_index,w 1708 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1709 385 1803 btfsc c___byte,c___bit 1710 ; if { id_index >= id . size } body start 1711 ; id_index := 0 1712 386 01a3 clrf main__id_index 1713 ; if { id_index >= id . size } body end 1714 ; if exp=` id_index >= id . size ' false skip delay=4 1715 ; Other expression=`{ id_index >= id . size }' delay=4 1716 ; if { id_index >= id . size } end 1717 ; call send_byte {{ id ~~ {{ id_index }} }} 1718 387 0a23 incf main__id_index,w 1719 ; Switch from register bank 1 to register bank 0 (which contains pclath___register) 1720 388 1283 bcf rp0___byte,rp0___bit 1721 ; Register bank is now 0 1722 389 018a clrf pclath___register 1723 38a 2013 call id 1724 38b 00be movwf send_byte__char 1725 38c 20e4 call send_byte 1726 ; id_index := id_index + 1 1727 ; Switch from register bank 0 to register bank 1 (which contains main__id_index) 1728 38d 1683 bsf rp0___byte,rp0___bit 1729 ; Register bank is now 1 1730 38e 0aa3 incf main__id_index,f 1731 ; if { id_index >= id_size } start 1732 38f 3033 movlw 51 1733 390 0223 subwf main__id_index,w 1734 ; expression=`{ id_index >= id_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1735 391 1803 btfsc c___byte,c___bit 1736 ; if { id_index >= id_size } body start 1737 ; id_index := 0 1738 392 01a3 clrf main__id_index 1739 ; if { id_index >= id_size } body end 1740 ; if exp=` id_index >= id_size ' false skip delay=4 1741 ; Other expression=`{ id_index >= id_size }' delay=4 1742 ; if { id_index >= id_size } end 1743 393 2ba0 goto switch__481end 1744 switch__481block509: 1745 ; ID Reset < Command = 1111 1101 > : 1746 ; id_index := 0 1747 394 01a3 clrf main__id_index 1748 395 2ba0 goto switch__481end 1749 switch__481block513: 1750 ; Glitch Read < Command = 1111 1110 > : 1751 ; call send_byte {{ glitch }} 1752 396 0822 movf main__glitch,w 1753 ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) 1754 397 1283 bcf rp0___byte,rp0___bit 1755 ; Register bank is now 0 1756 398 00be movwf send_byte__char 1757 399 20e4 call send_byte 1758 ; glitch := 0 1759 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) 1760 39a 1683 bsf rp0___byte,rp0___bit 1761 ; Register bank is now 1 1762 39b 01a2 clrf main__glitch 1763 39c 2ba0 goto switch__481end 1764 switch__481block518: 1765 ; Glitch < Command = 1111 1111 > : 1766 ; if { glitch != 0xff } start 1767 39d 0a22 incf main__glitch,w 1768 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1769 39e 1d03 btfss z___byte,z___bit 1770 ; if { glitch != 0xff } body start 1771 ; glitch := glitch + 1 1772 39f 0aa2 incf main__glitch,f 1773 ; if { glitch != 0xff } body end 1774 ; if exp=` glitch != 0xff ' false skip delay=3 1775 ; Other expression=`{ glitch != 0xff }' delay=3 1776 ; if { glitch != 0xff } end 1777 switch__481end: 1778 switch__442end: 1779 switch__333end: 1780 3a0 2a12 goto main__328loop__forever 1781 ; loop_forever ... end 1782 ; procedure main end 1783 1784 ; Register bank 0 used 32 bytes of 96 available bytes 1785 ; Register bank 1 used 6 bytes of 32 available bytes 1786 1787 end