radix dec global__variables__bank0 equ 32 global__variables__bank1 equ 160 global__bit__variables__bank0 equ 64 global__bit__variables__bank1 equ 166 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 rp0___byte equ 3 rp0___bit equ 5 rp1___byte equ 3 rp1___bit equ 6 irp___byte equ 3 irp___bit equ 7 trisa___register equ 0x85 trisb___register equ 0x86 fsr___register equ 4 pclath___register equ 10 org 0 start: nop nop nop goto skip___interrupt interrupt___vector: retfie skip___interrupt: ; Use oscillator calibration stored in high memory call 2047 ; Switch from register bank 0 to register bank 1 (which contains 143) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf 143 ; Initialize A/D system to allow digital I/O movlw 7 movwf 159 ; Switch from register bank 1 to register bank 0 (which contains 31) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf 31 ; Initialize TRIS registers movlw 223 tris 5 clrf pclath___register ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the InOut4 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / inout4 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12ce674 cp = off pwrte = off wdte = off mclre = off fosc = intrc_no_clock ; 16244=0x3f74 8199=0x2007 __config 16244 configuration___address equ 8199 ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {define serial communication control constants} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 osccal equ 5 ; constant osccal_unit 0x10 osccal_unit equ 16 ; comment {Analog to digital conversion result register :} addres equ 30 ; comment {Analog to digital conversion register 0 :} addcon0 equ 31 ; bind adon addcon0 @ 0 adon equ addcon0+0 adon__byte equ addcon0+0 adon__bit equ 0 ; bind go_done addcon0 @ 2 go_done equ addcon0+0 go_done__byte equ addcon0+0 go_done__bit equ 2 ; bind chs0 addcon0 @ 3 chs0 equ addcon0+0 chs0__byte equ addcon0+0 chs0__bit equ 3 ; bind chs1 addcon0 @ 4 chs1 equ addcon0+0 chs1__byte equ addcon0+0 chs1__bit equ 4 ; bind adcs0 addcon0 @ 6 adcs0 equ addcon0+0 adcs0__byte equ addcon0+0 adcs0__bit equ 6 ; bind adcs1 addcon0 @ 7 adcs1 equ addcon0+0 adcs1__byte equ addcon0+0 adcs1__bit equ 7 ; comment {Interrupt Control Register :} intcon equ 11 ; bind gpif intcon @ 0 gpif equ intcon+0 gpif__byte equ intcon+0 gpif__bit equ 0 ; bind intf intcon @ 1 intf equ intcon+0 intf__byte equ intcon+0 intf__bit equ 1 ; bind toif intcon @ 2 toif equ intcon+0 toif__byte equ intcon+0 toif__bit equ 2 ; bind gpie intcon @ 3 gpie equ intcon+0 gpie__byte equ intcon+0 gpie__bit equ 3 ; bind inte intcon @ 4 inte equ intcon+0 inte__byte equ intcon+0 inte__bit equ 4 ; bind toie intcon @ 5 toie equ intcon+0 toie__byte equ intcon+0 toie__bit equ 5 ; bind peie intcon @ 6 peie equ intcon+0 peie__byte equ intcon+0 peie__bit equ 6 ; bind gie intcon @ 7 gie equ intcon+0 gie__byte equ intcon+0 gie__bit equ 7 pir1 equ 12 ; bind adif pir1 @ 6 adif equ pir1+0 adif__byte equ pir1+0 adif__bit equ 6 pie1 equ 140 ; bind adie pie1 @ 6 adie equ pie1+0 adie__byte equ pie1+0 adie__bit equ 6 ; comment {Analog to digital conversion register 1 :} addcon1 equ 159 ; bind pcfg0 addcon1 @ 0 pcfg0 equ addcon1+0 pcfg0__byte equ addcon1+0 pcfg0__bit equ 0 ; bind pcfg1 addcon1 @ 1 pcfg1 equ addcon1+0 pcfg1__byte equ addcon1+0 pcfg1__bit equ 1 ; bind pcfg2 addcon1 @ 2 pcfg2 equ addcon1+0 pcfg2__byte equ addcon1+0 pcfg2__bit equ 2 ; constant ain_bit0 0 ain_bit0 equ 0 ; constant ain_bit1 1 ain_bit1 equ 1 ; constant ain_bit2 2 ain_bit2 equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; constant ain_bit3 4 ain_bit3 equ 4 ; constant serial_out_bit 5 serial_out_bit equ 5 ; constant ain_mask0 {{ 1 << ain_bit0 }} ain_mask0 equ 1 ; constant ain_mask1 {{ 1 << ain_bit1 }} ain_mask1 equ 2 ; constant ain_mask2 {{ 1 << ain_bit2 }} ain_mask2 equ 4 ; constant ain_mask3 {{ 1 << ain_bit3 }} ain_mask3 equ 16 ; constant serial_in_mask {{ 1 << serial_in_bit }} serial_in_mask equ 8 ; constant serial_out_mask {{ 1 << serial_out_bit }} serial_out_mask equ 32 ; constant io_mask 0xf io_mask equ 15 ; constant ain_mask {{ ain_mask0 | ain_mask1 | ain_mask2 | ain_mask3 }} ain_mask equ 23 ; constant serial_mask {{ serial_in_mask | serial_out_mask }} serial_mask equ 40 ; comment {define port bit assignments} porta equ 5 ain0__byte equ 5 ain0__bit equ 0 ain1__byte equ 5 ain1__bit equ 1 ain2__byte equ 5 ain2__bit equ 2 ain3__byte equ 5 ain3__bit equ 4 serial_in__byte equ 5 serial_in__bit equ 3 serial_out__byte equ 5 serial_out__bit equ 5 ; constant analogs_size 4 analogs_size equ 4 ; string_constants Start ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 string___fetch: movwf pcl___register ; id = 1 , 0 , 19 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 10 , 0s'AnalogIn4A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 51 retlw 51 ; 1 retlw 1 ; 0 retlw 0 ; 19 retlw 19 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 145 ; random number retlw 56 ; random number retlw 253 ; random number retlw 220 ; random number retlw 78 ; random number retlw 53 ; random number retlw 214 ; random number retlw 4 ; random number retlw 219 ; random number retlw 255 ; random number retlw 167 ; random number retlw 166 ; random number retlw 133 ; random number retlw 165 ; random number retlw 36 ; random number retlw 124 ; random number ; 10 retlw 10 ; `AnalogIn4A' retlw 65 retlw 110 retlw 97 retlw 108 retlw 111 retlw 103 retlw 73 retlw 110 retlw 52 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End ; constant id_size 8 + 16 + 1 + 10 + 1 + 15 id_size equ 51 ; bank 0 ; Default register bank is now 0 analogs equ global__variables__bank0+0 thresholds_low equ global__variables__bank0+4 thresholds_high equ global__variables__bank0+8 inputs equ global__variables__bank0+12 complement equ global__variables__bank0+13 ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 falling equ global__variables__bank0+14 high equ global__variables__bank0+15 low equ global__variables__bank0+16 raising equ global__variables__bank0+17 ; comment {For now put all the smaller routines first so that they can live} ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} ; comment {can only call routines that are within the first 256 bytes < i . e .} ; comment {the first half > of the code page .} ; bank 0 ; Default register bank is now 0 ; procedure delay start ; optimize 0 delay: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 delay__variables__base equ global__variables__bank0+18 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+8 delay__total__bytes equ 9 delay__175byte2 equ delay__bytes__base+7 delay__152byte3 equ delay__bytes__base+7 delay__187byte0 equ delay__bytes__base+7 delay__186byte1 equ delay__bytes__base+7 delay__131byte1 equ delay__bytes__base+7 delay__163byte0 equ delay__bytes__base+7 delay__154byte0 equ delay__bytes__base+7 ; arguments_none ; uniform_delay instructions_per_delay ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; This procedure will delay for one third of a bit time . ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__channel equ delay__bytes__base+0 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__current equ delay__bytes__base+1 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__changed equ delay__bytes__base+2 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__previous equ delay__bytes__base+3 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__not_current equ delay__bytes__base+4 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__counter equ delay__bytes__base+5 ; Uniform delay remaining = 134 Accumulated Delay = 0 delay__mask equ delay__bytes__base+6 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Uniform delay remaining = 134 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 134 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 133 Accumulated Delay = 1 ; Uniform delay remaining = 133 Accumulated Delay = 1 ; channel := {{ counter >> 1 }} & 3 bcf c___byte,c___bit rrf delay__counter,w andlw 3 movwf delay__channel ; Uniform delay remaining = 129 Accumulated Delay = 5 ; counter := counter + 1 incf delay__counter,f ; Uniform delay remaining = 128 Accumulated Delay = 6 ; if { counter @ 0 } start ; Alias variable for select counter @ 0 delay__counter__152select0 equ delay__counter+0 delay__counter__152select0__byte equ delay__counter+0 delay__counter__152select0__bit equ 0 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=40 false_delay=108 true_size=41 false_size=68 btfss delay__counter__152select0__byte,delay__counter__152select0__bit goto label152__1false label152__1true: ; if { counter @ 0 } body start ; Uniform delay remaining = 128 Accumulated Delay = 0 ; Set up and wait for acquistion : ; Uniform delay remaining = 128 Accumulated Delay = 0 ; addcon0 := 0x41 | {{ channel << 3 }} & 0x18 rlf delay__channel,w movwf delay__154byte0 rlf delay__154byte0,f rlf delay__154byte0,w andlw 248 andlw 24 iorlw 65 movwf addcon0 ; Uniform delay remaining = 120 Accumulated Delay = 8 ; Setup for interrupts : ; Uniform delay remaining = 120 Accumulated Delay = 8 ; previous := current movf delay__current,w movwf delay__previous ; Uniform delay remaining = 118 Accumulated Delay = 10 ; Read the I / O port once : ; Uniform delay remaining = 118 Accumulated Delay = 10 ; current := inputs ^ complement movf inputs,w xorwf complement,w movwf delay__current ; Uniform delay remaining = 115 Accumulated Delay = 13 ; not_current := current ^ 0xf movlw 15 xorwf delay__current,w movwf delay__not_current ; Uniform delay remaining = 112 Accumulated Delay = 16 ; changed := current ^ previous movf delay__current,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 109 Accumulated Delay = 19 ; Uniform delay remaining = 109 Accumulated Delay = 19 ; See about triggering the interrupt_pending flag : ; Uniform delay remaining = 109 Accumulated Delay = 19 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start movf low,w andwf delay__not_current,w movwf delay__163byte0 movf high,w andwf delay__current,w iorwf delay__163byte0,f movf delay__changed,w andwf delay__current,w andwf raising,w iorwf delay__163byte0,f movf delay__changed,w andwf delay__not_current,w andwf falling,w iorwf delay__163byte0,w ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start ; Uniform delay remaining = 109 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 108 Accumulated Delay = 1 ; Uniform delay remaining = 108 Accumulated Delay = 1 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end ; Uniform delay remaining = 93 Accumulated Delay = 35 ; Uniform delay remaining = 93 Accumulated Delay = 35 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 93 Accumulated Delay = 35 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label168__2true label168__2false: ; Delay 1 cycles nop goto and168__0false label168__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_enable__byte,interrupt_enable__bit and168__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 93 Accumulated Delay = 0 ; Shove serial out to low : ; Uniform delay remaining = 93 Accumulated Delay = 0 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 92 Accumulated Delay = 1 ; Uniform delay remaining = 92 Accumulated Delay = 1 ; if { interrupt_pending && interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`interrupt_enable' delay=2 ; if exp=`interrupt_pending' total delay=5 ; if exp=`interrupt_pending' generic label168__2end: ; Other expression=`interrupt_pending' delay=5 and168__0false: and168__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 88 Accumulated Delay = 40 ; Uniform delay remaining = 88 Accumulated Delay = 40 ; if { counter @ 0 } body end ; Delay 67 cycles movlw 22 movwf delay__152byte3 delay__152delay2: decfsz delay__152byte3,f goto delay__152delay2 goto label152__1end label152__1false: ; else body start ; Uniform delay remaining = 128 Accumulated Delay = 0 ; Start the conversion : ; Uniform delay remaining = 128 Accumulated Delay = 0 ; go_done := 1 bsf go_done__byte,go_done__bit ; Uniform delay remaining = 127 Accumulated Delay = 1 ; if { channel = 0 } start movf delay__channel,w ; expression=`{ channel = 0 }' exp_delay=1 true_delay=1 false_delay=10 true_size=1 false_size=15 btfss z___byte,z___bit goto label175__0false label175__0true: ; if { channel = 0 } body start ; Uniform delay remaining = 127 Accumulated Delay = 0 ; mask := 1 movlw 1 ; 1 instructions found for sharing ; Uniform delay remaining = 125 Accumulated Delay = 2 ; if { channel = 0 } body end ; Delay 8 cycles movlw 2 movwf delay__175byte2 delay__175delay1: decfsz delay__175byte2,f goto delay__175delay1 nop goto label175__0end label175__0false: decf delay__channel,w ; expression=`{ channel = 1 }' exp_delay=1 true_delay=1 false_delay=6 true_size=1 false_size=6 btfss z___byte,z___bit goto label177__0false label177__0true: ; else_if { channel = 1 } body start ; Uniform delay remaining = 127 Accumulated Delay = 0 ; mask := 2 movlw 2 ; 1 instructions found for sharing ; Uniform delay remaining = 125 Accumulated Delay = 2 ; else_if { channel = 1 } body end ; Delay 4 cycles nop nop nop nop goto label177__0end label177__0false: movlw 2 subwf delay__channel,w ; expression=`{ channel = 2 }' exp_delay=2 true_delay=1 false_delay=1 true_size=1 false_size=1 btfsc z___byte,z___bit ; else_if { channel = 2 } body start ; Uniform delay remaining = 127 Accumulated Delay = 0 ; mask := 4 movlw 4 ; 1 instructions found for sharing ; Uniform delay remaining = 125 Accumulated Delay = 2 ; else_if { channel = 2 } body end btfss z___byte,z___bit ; else body start ; Uniform delay remaining = 127 Accumulated Delay = 0 ; mask := 8 movlw 8 ; 1 instructions found for sharing ; Uniform delay remaining = 125 Accumulated Delay = 2 ; else body end ; if exp=` channel = 2 ' single true and false skip delay=6 ; Other expression=`{ channel = 2 }' delay=6 ; 1 shared instructions follow ; 1 instructions found for sharing ; if exp=` channel = 1 ' total delay=10 ; if exp=` channel = 1 ' generic label177__0end: ; Other expression=`{ channel = 1 }' delay=10 ; 1 shared instructions follow ; 1 instructions found for sharing ; if exp=` channel = 0 ' total delay=14 ; if exp=` channel = 0 ' generic label175__0end: ; Other expression=`{ channel = 0 }' delay=14 ; 1 shared instructions follow movwf delay__mask ; if { channel = 0 } end ; Uniform delay remaining = 112 Accumulated Delay = 16 ; Delaying 60 uS is way longer than necessary for the conversion ; Uniform delay remaining = 112 Accumulated Delay = 16 ; to complete . ; Uniform delay remaining = 112 Accumulated Delay = 16 ; nop 60 ; Delay 60 cycles movlw 19 movwf delay__186byte1 delay__186delay0: decfsz delay__186byte1,f goto delay__186delay0 nop nop ; Uniform delay remaining = 52 Accumulated Delay = 76 ; analogs ~~ {{ channel }} := addres movf addres,w movwf delay__187byte0 movlw LOW analogs addwf delay__channel,w movwf fsr___register movf delay__187byte0,w movwf indf___register ; Uniform delay remaining = 45 Accumulated Delay = 83 ; if { addres < thresholds_low ~~ {{ channel }} } start movlw LOW thresholds_low addwf delay__channel,w movwf fsr___register movf indf___register,w subwf addres,w ; expression=`{ addres < thresholds_low ~~ {{ channel }} }' exp_delay=5 true_delay=3 false_delay=0 true_size=3 false_size=0 btfss c___byte,c___bit goto label188__0true label188__0false: ; Delay 2 cycles nop nop goto label188__0end label188__0true: ; if { addres < thresholds_low ~~ {{ channel }} } body start ; Uniform delay remaining = 45 Accumulated Delay = 0 ; inputs := inputs & {{ mask ^ io_mask }} movlw 15 xorwf delay__mask,w andwf inputs,f ; Uniform delay remaining = 42 Accumulated Delay = 3 ; Uniform delay remaining = 42 Accumulated Delay = 3 ; if { addres < thresholds_low ~~ {{ channel }} } body end ; if exp=` addres < thresholds_low ~~ {{ channel }} ' total delay=11 ; if exp=` addres < thresholds_low ~~ {{ channel }} ' generic label188__0end: ; Other expression=`{ addres < thresholds_low ~~ {{ channel }} }' delay=11 ; if { addres < thresholds_low ~~ {{ channel }} } end ; Uniform delay remaining = 34 Accumulated Delay = 94 ; if { addres > thresholds_high ~~ {{ channel }} } start movlw LOW thresholds_high addwf delay__channel,w movwf fsr___register movf indf___register,w subwf addres,w btfss z___byte,z___bit bsf c___byte,c___bit ; expression=`{ addres > thresholds_high ~~ {{ channel }} }' exp_delay=7 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc c___byte,c___bit goto label191__0true label191__0false: ; Delay 1 cycles nop goto label191__0end label191__0true: ; if { addres > thresholds_high ~~ {{ channel }} } body start ; Uniform delay remaining = 34 Accumulated Delay = 0 ; inputs := inputs | mask movf delay__mask,w iorwf inputs,f ; Uniform delay remaining = 32 Accumulated Delay = 2 ; Uniform delay remaining = 32 Accumulated Delay = 2 ; if { addres > thresholds_high ~~ {{ channel }} } body end ; if exp=` addres > thresholds_high ~~ {{ channel }} ' total delay=12 ; if exp=` addres > thresholds_high ~~ {{ channel }} ' generic label191__0end: ; Other expression=`{ addres > thresholds_high ~~ {{ channel }} }' delay=12 ; if { addres > thresholds_high ~~ {{ channel }} } end ; Uniform delay remaining = 22 Accumulated Delay = 106 ; inputs := inputs & io_mask movlw 15 andwf inputs,f ; Uniform delay remaining = 20 Accumulated Delay = 108 ; Uniform delay remaining = 20 Accumulated Delay = 108 ; else body end ; if exp=` counter @ 0 ' total delay=111 ; if exp=` counter @ 0 ' generic label152__1end: ; Other expression=`{ counter @ 0 }' delay=111 ; if { counter @ 0 } end ; Uniform delay remaining = 17 Accumulated Delay = 117 ; Uniform delay remaining = 17 Accumulated Delay = 117 ; Soak up remaining 17 cycles ; Delay 17 cycles movlw 5 movwf delay__131byte1 delay__131delay0: decfsz delay__131byte1,f goto delay__131delay0 nop ; procedure delay end retlw 0 ; optimize 1 ; procedure get_byte start get_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 get_byte__variables__base equ global__variables__bank0+27 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__214while__continue: ; expression=`serial_in' exp_delay=0 true_delay=139 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__214while__break ; call delay {{ }} call delay goto get_byte__214while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__214while__break: ; `while serial_in ...' end ; Clear interrupts and interrupt pending : ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; char := 0 clrf get_byte__char ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__228_loop: ; call delay {{ }} call delay ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss serial_in__byte,serial_in__bit goto label231__0end ; if { serial_in } body start ; char := char | 0x80 movlw 128 iorwf get_byte__char,f ; if { serial_in } body end label231__0end: ; if exp=`serial_in' empty false ; Other expression=`{ serial_in }' delay=-1 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz get_byte__count,f goto get_byte__228_loop get_byte__228_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 ; Procedure must be called with PCLATH set to code bank 0 send_byte__variables__base equ global__variables__bank0+30 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=275 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label260__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label260__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf send_byte__count send_byte__273_loop: ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__274select0 equ send_byte__char+0 send_byte__char__274select0__byte equ send_byte__char+0 send_byte__char__274select0__bit equ 0 btfss send_byte__char__274select0__byte,send_byte__char__274select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__274select0__byte,send_byte__char__274select0__bit bsf serial_out__byte,serial_out__bit ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay decfsz send_byte__count,f goto send_byte__273_loop send_byte__273_done: ; `count_down count 8 ...' end ; Send the stop bit : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; procedure send_byte end retlw 0 ; origin 0x200 org 512 ; bank 1 ; Default register bank is now 1 ; comment {The main routine can span the 256 byte boundary :} ; procedure main start main: ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 ; Procedure must be called with PCLATH set to code bank 0 main__variables__base equ global__variables__bank1+0 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+6 main__total__bytes equ 6 main__449byte0 equ main__bytes__base+5 main__399byte0 equ main__bytes__base+5 main__333byte0 equ main__bytes__base+5 main__442byte0 equ main__bytes__base+5 main__403byte0 equ main__bytes__base+5 main__388byte0 equ main__bytes__base+5 main__336byte0 equ main__bytes__base+5 ; arguments_none main__bit equ main__bytes__base+0 main__command equ main__bytes__base+1 main__glitch equ main__bytes__base+2 main__id_index equ main__bytes__base+3 main__result equ main__bytes__base+4 ; Let ROOT = http : / / web . gramlich . com / projects / robobricks . ; For InOut4A specific commands see : ; ROOT / InOut4 / rev_a / index . html ; For shared commands see : ; ROOT / specifications . html # Software_Protocol ; For shared interruptcommands see : ; ROOT / specifications . html # Interrupts ; Initialize the A / D module : ; addcon1 := 0 clrf addcon1 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : ; addcon0 := 0x41 movlw 65 ; Switch from register bank 1 to register bank 0 (which contains addcon0) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf addcon0 ; adif := 0 bcf adif__byte,adif__bit ; adie := 0 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf adie__byte,adie__bit ; gie := 0 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf gie__byte,gie__bit ; Set the direction : ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; falling := 0 clrf falling ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch ; id_index := 0 clrf main__id_index ; loop_forever ... start main__328loop__forever: ; Wait for a command : ; command := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__command ; Dispatch on command : ; switch { command >> 6 } movlw HIGH switch__333block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 swapf main__command,w movwf main__333byte0 rrf main__333byte0,f rrf main__333byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__333block_start: addwf pcl___register,f goto switch__333block334 goto switch__333block416 goto switch__333block437 goto switch__333block440 switch__333block_end: ; switch_check 333 switch__333block_start switch__333block_end switch__333block334: ; Command = 00 xx xxxx : ; switch { command >> 3 } movlw HIGH switch__336block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf main__command,w movwf main__336byte0 rrf main__336byte0,f rrf main__336byte0,w andlw 31 ; case 0 ; case 1 ; case 2 3 ; case 4 5 switch__336block_start: addwf pcl___register,f goto switch__336block337 goto switch__336block357 goto switch__336block385 goto switch__336block385 goto switch__336block407 goto switch__336block407 goto switch__336default411 goto switch__336default411 switch__336block_end: ; switch_check 336 switch__336block_start switch__336block_end switch__336block337: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw HIGH switch__339block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register movlw 7 ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 andwf main__command,w ; case 0 1 2 3 ; case 4 ; case 5 switch__339block_start: addwf pcl___register,f goto switch__339block340 goto switch__339block340 goto switch__339block340 goto switch__339block340 goto switch__339block344 goto switch__339block348 goto switch__339default352 goto switch__339default352 switch__339block_end: ; switch_check 339 switch__339block_start switch__339block_end switch__339block340: ; Read Pin < Command = 0000 00 bb > : ; call send_byte {{ analogs ~~ {{ command }} }} movlw LOW analogs addwf main__command,w movwf fsr___register movf indf___register,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__339end switch__339block344: ; Read Binary Values < Command = 0000 0100 > : ; call send_byte {{ inputs ^ complement }} ; Switch from register bank 1 to register bank 0 (which contains inputs) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf inputs,w xorwf complement,w movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__339end switch__339block348: ; Read Raw Binary < Command = 0000 0101 > : ; call send_byte {{ inputs }} ; Switch from register bank 1 to register bank 0 (which contains inputs) bcf rp0___byte,rp0___bit ; Register bank is now 0 movf inputs,w movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__339end switch__339default352: ; Undefine command : switch__339end: goto switch__336end switch__336block357: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw HIGH switch__359block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register movlw 7 ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 switch__359block_start: addwf pcl___register,f goto switch__359block360 goto switch__359block364 goto switch__359block368 goto switch__359block372 goto switch__359block376 goto switch__359default380 goto switch__359default380 goto switch__359default380 switch__359block_end: ; switch_check 359 switch__359block_start switch__359block_end switch__359block360: ; Set Complement Mask < Command = 0000 1000 > : ; complement := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf complement ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__359end switch__359block364: ; Set High Mask < Command = 0000 1001 > : ; high := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__359end switch__359block368: ; Set Low Mask < Command = 0000 1010 > : ; low := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__359end switch__359block372: ; Set Raising Mask < Command = 0000 1011 > : ; raising := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf raising ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__359end switch__359block376: ; Set Falling Mask < Command = 0000 1100 > : ; falling := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf falling ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__359end switch__359default380: ; Undefined command : switch__359end: goto switch__336end switch__336block385: ; Command = 0001 0 xxx : ; bit := command & 3 movlw 3 andwf main__command,w movwf main__bit ; switch { {{ command >> 2 }} & 3 } movlw HIGH switch__388block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf main__command,w movwf main__388byte0 rrf main__388byte0,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__388block_start: addwf pcl___register,f goto switch__388block389 goto switch__388block393 goto switch__388block397 goto switch__388block401 switch__388block_end: ; switch_check 388 switch__388block_start switch__388block_end switch__388block389: ; Read High Threshold < Command = 0001 00 bb > : ; call send_byte {{ thresholds_high ~~ {{ bit }} }} movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf indf___register,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__388end switch__388block393: ; Read Low Threshold < Command = 0001 01 bb > : ; call send_byte {{ thresholds_low ~~ {{ bit }} }} movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf indf___register,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__388end switch__388block397: ; Set High Threshold < Command = 0001 10 bb > : ; thresholds_high ~~ {{ bit }} := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__399byte0) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__399byte0 movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf main__399byte0,w movwf indf___register goto switch__388end switch__388block401: ; Set Low Threshold < Command = 0001 11 bb > : ; thresholds_low ~~ {{ bit }} := get_byte {{ }} ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w ; Switch from register bank 0 to register bank 1 (which contains main__403byte0) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf main__403byte0 movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf main__403byte0,w movwf indf___register switch__388end: goto switch__336end switch__336block407: ; Set Complement Mask < Command = 0001 cccc > : ; complement := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf complement ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__336end switch__336default411: ; Undefined commands ; do nothing : switch__336end: goto switch__333end switch__333block416: ; Command = 01 xx xxxx : ; switch { {{ command >> 4 }} & 3 } movlw HIGH switch__418block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 swapf main__command,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__418block_start: addwf pcl___register,f goto switch__418block419 goto switch__418block423 goto switch__418block427 goto switch__418block431 switch__418block_end: ; switch_check 418 switch__418block_start switch__418block_end switch__418block419: ; Set High Mask < Command = 0100 hhhh > : ; high := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf high ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__418end switch__418block423: ; Set Low Mask < Command = 0101 llll > : ; low := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf low ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__418end switch__418block427: ; Set Raising Mask < Command = 0110 rrrr > : ; raising := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf raising ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__418end switch__418block431: ; Set Falling Mask < Command = 0111 ffff > : ; falling := get_byte {{ }} & io_mask ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 call get_byte movf get_byte__0return__byte,w andlw 15 movwf falling ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__418end: goto switch__333end switch__333block437: ; Do nothing < Command = 10 xx xxxx > : goto switch__333end switch__333block440: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } movlw HIGH switch__442block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 rrf main__command,w movwf main__442byte0 rrf main__442byte0,f rrf main__442byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 switch__442block_start: addwf pcl___register,f goto switch__442block443 goto switch__442block443 goto switch__442block443 goto switch__442block443 goto switch__442block443 goto switch__442block447 goto switch__442block461 goto switch__442block479 switch__442block_end: ; switch_check 442 switch__442block_start switch__442block_end switch__442block443: ; Command = 1100 xxxx or 1110 0 xxx : ; Do nothing : goto switch__442end switch__442block447: ; Read Interrupt Bits < Command = 1110 1111 > : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__449byte0 movlw 7 subwf main__449byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 btfss z___byte,z___bit goto label449__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits : ; result := 0 clrf main__result ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_enable__byte,interrupt_enable__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label452__0end ; if { interrupt_enable } body start ; result := result | 2 movlw 2 iorwf main__result,f ; if { interrupt_enable } body end label452__0end: ; if exp=`interrupt_enable' empty false ; Other expression=`{ interrupt_enable }' delay=-1 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf z___byte,z___bit btfsc interrupt_pending__byte,interrupt_pending__bit bsf z___byte,z___bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 btfss z___byte,z___bit goto label455__0end ; if { interrupt_pending } body start ; result := result | 1 movlw 1 iorwf main__result,f ; if { interrupt_pending } body end label455__0end: ; if exp=`interrupt_pending' empty false ; Other expression=`{ interrupt_pending }' delay=-1 ; if { interrupt_pending } end ; call send_byte {{ result }} movf main__result,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; if { {{ command & 7 }} = 7 } body end ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 label449__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__442end switch__442block461: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw HIGH switch__463block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register movlw 7 ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 switch__463block_start: addwf pcl___register,f goto switch__463block464 goto switch__463block464 goto switch__463block464 goto switch__463block464 goto switch__463block469 goto switch__463block469 goto switch__463block473 goto switch__463block473 switch__463block_end: ; switch_check 463 switch__463block_start switch__463block_end switch__463block464: ; Set interrupt bits < Command = 1111 10 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__466select0 equ main__command+0 main__command__466select0__byte equ main__command+0 main__command__466select0__bit equ 1 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__466select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__466select0__byte,main__command__466select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__467select0 equ main__command+0 main__command__467select0__byte equ main__command+0 main__command__467select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__467select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__467select0__byte,main__command__467select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__463end switch__463block469: ; Set Interrupt Pending < Command = 1111 110 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__471select0 equ main__command+0 main__command__471select0__byte equ main__command+0 main__command__471select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__471select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__471select0__byte,main__command__471select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_pending__byte,interrupt_pending__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__463end switch__463block473: ; Set Interrupt Enable < Command = 1110 111 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__475select0 equ main__command+0 main__command__475select0__byte equ main__command+0 main__command__475select0__bit equ 0 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 (which contains main__command__475select0__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf z___byte,z___bit btfsc main__command__475select0__byte,main__command__475select0__bit bsf z___byte,z___bit ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 btfsc z___byte,z___bit bsf interrupt_enable__byte,interrupt_enable__bit ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 switch__463end: goto switch__442end switch__442block479: ; Shared commands < Command = 1111 1 xxx > : ; switch { command & 7 } movlw HIGH switch__481block_start ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf pclath___register movlw 7 ; Switch from register bank 0 to register bank 1 (which contains main__command) bsf rp0___byte,rp0___bit ; Register bank is now 1 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 switch__481block_start: addwf pcl___register,f goto switch__481block482 goto switch__481block486 goto switch__481block490 goto switch__481block494 goto switch__481block498 goto switch__481block509 goto switch__481block513 goto switch__481block518 switch__481block_end: ; switch_check 481 switch__481block_start switch__481block_end switch__481block482: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 240 addwf osccal,f goto switch__481end switch__481block486: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 16 addwf osccal,f goto switch__481end switch__481block490: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} movf osccal,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__481end switch__481block494: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf send_byte__char call send_byte ; Switch from register bank 0 to register bank 1 bsf rp0___byte,rp0___bit ; Register bank is now 1 goto switch__481end switch__481block498: ; ID Next < Command = 1111 1100 > : ; if { id_index >= id . size } start movlw 51 subwf main__id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end ; call send_byte {{ id ~~ {{ id_index }} }} incf main__id_index,w ; Switch from register bank 1 to register bank 0 (which contains pclath___register) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf pclath___register call id movwf send_byte__char call send_byte ; id_index := id_index + 1 ; Switch from register bank 0 to register bank 1 (which contains main__id_index) bsf rp0___byte,rp0___bit ; Register bank is now 1 incf main__id_index,f ; if { id_index >= id_size } start movlw 51 subwf main__id_index,w ; expression=`{ id_index >= id_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id_size } body start ; id_index := 0 clrf main__id_index ; if { id_index >= id_size } body end ; if exp=` id_index >= id_size ' false skip delay=4 ; Other expression=`{ id_index >= id_size }' delay=4 ; if { id_index >= id_size } end goto switch__481end switch__481block509: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf main__id_index goto switch__481end switch__481block513: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf main__glitch,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte ; glitch := 0 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) bsf rp0___byte,rp0___bit ; Register bank is now 1 clrf main__glitch goto switch__481end switch__481block518: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf main__glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf main__glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__481end: switch__442end: switch__333end: goto main__328loop__forever ; loop_forever ... end ; procedure main end ; Register bank 0 used 32 bytes of 96 available bytes ; Register bank 1 used 6 bytes of 32 available bytes end