radix dec global__variables__bank0 equ 32 global__variables__bank1 equ 160 global__bit__variables__bank0 equ 67 global__bit__variables__bank1 equ 160 indf___register equ 0 pcl___register equ 2 c___byte equ 3 c___bit equ 0 z___byte equ 3 z___bit equ 2 rp0___byte equ 3 rp0___bit equ 5 rp1___byte equ 3 rp1___bit equ 6 irp___byte equ 3 irp___bit equ 7 trisa___register equ 0x85 trisb___register equ 0x86 fsr___register equ 4 pclath___register equ 10 org 0 start: nop nop nop goto skip___interrupt interrupt___vector: retfie skip___interrupt: ; Use oscillator calibration stored in high memory call 2047 ; Switch from register bank 0 to register bank 1 (which contains 143) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf 143 ; Initialize A/D system to allow digital I/O movlw 7 movwf 159 ; Switch from register bank 1 to register bank 0 (which contains 31) bcf rp0___byte,rp0___bit ; Register bank is now 0 clrf 31 ; Initialize TRIS registers movlw 207 tris 5 clrf pclath___register goto main ; comment ############################################################################# ; comment {} ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} ; comment {All rights reserved .} ; comment {} ; comment {Permission to use , copy , modify , distribute , and sell this software} ; comment {for any purpose is hereby granted without fee provided that the above} ; comment {copyright notice and this permission are retained . The author makes} ; comment {no representations about the suitability of this software for any purpose .} ; comment {It is provided { as is } without express or implied warranty .} ; comment {} ; comment {This is the code that implements the AIROD2 RoboBrick . Basically} ; comment {it just waits for commands that come in at 2400 baud and responds} ; comment {to them . See} ; comment {} ; comment {http : / / web . gramlich . net / projects / robobricks / airod2 / index . html} ; comment {} ; comment {for more details .} ; comment {} ; comment ############################################################################# ; processor pic12ce674 cp = off pwrte = off wdte = off mclre = off fosc = intrc_no_clock ; 16244=0x3f74 8199=0x2007 __config 16244 configuration___address equ 8199 ; comment {define processor constants} ; constant clock_rate 4000000 clock_rate equ 4000000 ; constant clocks_per_instruction 4 clocks_per_instruction equ 4 ; constant instruction_rate clock_rate / clocks_per_instruction instruction_rate equ 1000000 ; comment {define serial communication control constants} ; constant baud_rate 2400 baud_rate equ 2400 ; constant instructions_per_bit instruction_rate / baud_rate instructions_per_bit equ 416 ; constant delays_per_bit 3 delays_per_bit equ 3 ; constant instructions_per_delay instructions_per_bit / delays_per_bit instructions_per_delay equ 138 ; constant extra_instructions_per_bit 9 extra_instructions_per_bit equ 9 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit extra_instructions_per_delay equ 3 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay delay_instructions equ 135 ; comment {Oscillator Mask :} osccal equ 143 ; constant osccal_unit 0x10 osccal_unit equ 16 ; comment {Analog to digital conversion result register :} addres equ 30 ; comment {Analog to digital conversion register 0 :} addcon0 equ 31 ; bind adon addcon0 @ 0 adon equ addcon0+0 adon__byte equ addcon0+0 adon__bit equ 0 ; bind go_done addcon0 @ 2 go_done equ addcon0+0 go_done__byte equ addcon0+0 go_done__bit equ 2 ; bind chs0 addcon0 @ 3 chs0 equ addcon0+0 chs0__byte equ addcon0+0 chs0__bit equ 3 ; bind chs1 addcon0 @ 4 chs1 equ addcon0+0 chs1__byte equ addcon0+0 chs1__bit equ 4 ; bind adcs0 addcon0 @ 6 adcs0 equ addcon0+0 adcs0__byte equ addcon0+0 adcs0__bit equ 6 ; bind adcs1 addcon0 @ 7 adcs1 equ addcon0+0 adcs1__byte equ addcon0+0 adcs1__bit equ 7 ; comment {Interrupt Control Register :} intcon equ 11 ; bind gpif intcon @ 0 gpif equ intcon+0 gpif__byte equ intcon+0 gpif__bit equ 0 ; bind intf intcon @ 1 intf equ intcon+0 intf__byte equ intcon+0 intf__bit equ 1 ; bind toif intcon @ 2 toif equ intcon+0 toif__byte equ intcon+0 toif__bit equ 2 ; bind gpie intcon @ 3 gpie equ intcon+0 gpie__byte equ intcon+0 gpie__bit equ 3 ; bind inte intcon @ 4 inte equ intcon+0 inte__byte equ intcon+0 inte__bit equ 4 ; bind toie intcon @ 5 toie equ intcon+0 toie__byte equ intcon+0 toie__bit equ 5 ; bind peie intcon @ 6 peie equ intcon+0 peie__byte equ intcon+0 peie__bit equ 6 ; bind gie intcon @ 7 gie equ intcon+0 gie__byte equ intcon+0 gie__bit equ 7 pir1 equ 12 ; bind adif pir1 @ 6 adif equ pir1+0 adif__byte equ pir1+0 adif__bit equ 6 pie1 equ 140 ; bind adie pie1 @ 6 adie equ pie1+0 adie__byte equ pie1+0 adie__bit equ 6 ; comment {Analog to digital conversion register 1 :} addcon1 equ 159 ; bind pcfg0 addcon1 @ 0 pcfg0 equ addcon1+0 pcfg0__byte equ addcon1+0 pcfg0__bit equ 0 ; bind pcfg1 addcon1 @ 1 pcfg1 equ addcon1+0 pcfg1__byte equ addcon1+0 pcfg1__bit equ 1 ; bind pcfg2 addcon1 @ 2 pcfg2 equ addcon1+0 pcfg2__byte equ addcon1+0 pcfg2__bit equ 2 ; constant airod0_bit 0 airod0_bit equ 0 ; constant vref_bit 1 vref_bit equ 1 ; constant airod1_bit 2 airod1_bit equ 2 ; constant serial_in_bit 3 serial_in_bit equ 3 ; constant enable_bit 4 enable_bit equ 4 ; constant serial_out_bit 5 serial_out_bit equ 5 ; constant io_mask 3 io_mask equ 3 ; comment {define port bit assignments} porta equ 5 airod0__byte equ 5 airod0__bit equ 0 vref__byte equ 5 vref__bit equ 1 airod1__byte equ 5 airod1__bit equ 2 enable__byte equ 5 enable__bit equ 4 serial_in__byte equ 5 serial_in__bit equ 3 serial_out__byte equ 5 serial_out__bit equ 5 ; constant analogs_size 2 analogs_size equ 2 ; string_constants Start string___fetch: movwf pcl___register ; id = 1 , 0 , 20 , 0 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'AIROD2A' , 15 , 0s'Gramlich&Benson' id___string equ 0 id: addwf pcl___register,f ; Length = 48 retlw 48 ; 1 retlw 1 ; 0 retlw 0 ; 20 retlw 20 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0 retlw 0 ; 0r'16' retlw 99 ; random number retlw 49 ; random number retlw 196 ; random number retlw 70 ; random number retlw 24 ; random number retlw 225 ; random number retlw 147 ; random number retlw 243 ; random number retlw 67 ; random number retlw 63 ; random number retlw 14 ; random number retlw 237 ; random number retlw 73 ; random number retlw 37 ; random number retlw 150 ; random number retlw 216 ; random number ; 7 retlw 7 ; `AIROD2A' retlw 65 retlw 73 retlw 82 retlw 79 retlw 68 retlw 50 retlw 65 ; 15 retlw 15 ; `Gramlich&Benson' retlw 71 retlw 114 retlw 97 retlw 109 retlw 108 retlw 105 retlw 99 retlw 104 retlw 38 retlw 66 retlw 101 retlw 110 retlw 115 retlw 111 retlw 110 ; string__constants End analogs equ global__variables__bank0+0 thresholds_low equ global__variables__bank0+2 thresholds_high equ global__variables__bank0+4 inputs equ global__variables__bank0+6 complement equ global__variables__bank0+7 glitch equ global__variables__bank0+8 id_index equ global__variables__bank0+9 ; comment {Interrupt masks :} interrupt_enable equ global__bit__variables__bank0+0 interrupt_enable__byte equ global__bit__variables__bank0+0 interrupt_enable__bit equ 0 interrupt_pending equ global__bit__variables__bank0+0 interrupt_pending__byte equ global__bit__variables__bank0+0 interrupt_pending__bit equ 1 receiving equ global__bit__variables__bank0+0 receiving__byte equ global__bit__variables__bank0+0 receiving__bit equ 2 falling equ global__variables__bank0+10 high equ global__variables__bank0+11 low equ global__variables__bank0+12 raising equ global__variables__bank0+13 ; procedure main start main: main__variables__base equ global__variables__bank0+14 main__bytes__base equ main__variables__base+0 main__bits__base equ main__variables__base+4 main__total__bytes equ 5 main__269byte0 equ main__bytes__base+3 main__144byte0 equ main__bytes__base+3 main__276byte0 equ main__bytes__base+3 main__227byte0 equ main__bytes__base+3 main__223byte0 equ main__bytes__base+3 main__233byte0 equ main__bytes__base+3 main__147byte0 equ main__bytes__base+3 ; arguments_none main__bit equ main__bytes__base+0 main__command equ main__bytes__base+1 main__temporary equ main__bytes__base+2 ; Initialize the A / D module : ; GP4 = Digital , GP2 = Analog , GP1 = Vref , GP0 = Analog ; addcon1 := 3 movlw 3 ; Switch from register bank 0 to register bank 1 (which contains addcon1) bsf rp0___byte,rp0___bit ; Register bank is now 1 movwf addcon1 ; A / D Conversion clock is Fosc / 8 < Tad = 2 uS > and AD is on : ; addcon0 := 0x41 movlw 65 ; Switch from register bank 1 to register bank 0 (which contains addcon0) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf addcon0 ; adif := 0 bcf adif__byte,adif__bit ; adie := 0 ; Switch from register bank 0 to register bank 1 (which contains adie__byte) bsf rp0___byte,rp0___bit ; Register bank is now 1 bcf adie__byte,adie__bit ; gie := 0 ; Switch from register bank 1 to register bank 0 (which contains gie__byte) bcf rp0___byte,rp0___bit ; Register bank is now 0 bcf gie__byte,gie__bit ; call reset {{ }} call reset ; Set the direction : ; loop_forever ... start main__139loop__forever: ; Wait for a command : ; command := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__command ; Dispatch on command : ; switch { command >> 6 } movlw HIGH switch__144block_start movwf pclath___register swapf main__command,w movwf main__144byte0 rrf main__144byte0,f rrf main__144byte0,w andlw 3 ; case 0 ; case 1 2 ; case 3 switch__144block_start: addwf pcl___register,f goto switch__144block145 goto switch__144block264 goto switch__144block264 goto switch__144block267 switch__144block_end: ; switch_check 144 switch__144block_start switch__144block_end switch__144block145: ; Command = 00 xx xxxx : ; switch { command >> 3 } movlw HIGH switch__147block_start movwf pclath___register rrf main__command,w movwf main__147byte0 rrf main__147byte0,f rrf main__147byte0,w andlw 31 ; case 0 ; case 1 ; case 2 ; case 4 5 6 switch__147block_start: addwf pcl___register,f goto switch__147block148 goto switch__147block181 goto switch__147block209 goto switch__147default259 goto switch__147block231 goto switch__147block231 goto switch__147block231 goto switch__147default259 switch__147block_end: ; switch_check 147 switch__147block_start switch__147block_end switch__147block148: ; Command = 0000 0 xxx : ; switch { command & 7 } movlw HIGH switch__150block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 7 switch__150block_start: addwf pcl___register,f goto switch__150block151 goto switch__150block151 goto switch__150block155 goto switch__150block159 goto switch__150block163 goto switch__150block167 goto switch__150block175 goto switch__150block175 switch__150block_end: ; switch_check 150 switch__150block_start switch__150block_end switch__150block151: ; Read Pin < Command = 0000 000 b > : ; call send_byte {{ analogs ~~ {{ command }} }} movlw LOW analogs addwf main__command,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__150end switch__150block155: ; Read Binary Values < Command = 0000 0010 > : ; call send_byte {{ inputs ^ complement }} movf inputs,w xorwf complement,w movwf send_byte__char call send_byte goto switch__150end switch__150block159: ; Read Raw Binary < Command = 0000 0011 > : ; call send_byte {{ inputs }} movf inputs,w movwf send_byte__char call send_byte goto switch__150end switch__150block163: ; Reset < Command = 0000 0100 > : ; call reset {{ }} call reset goto switch__150end switch__150block167: ; Read Enable Bit < Command = 0000 0110 > : ; temporary := 0 clrf main__temporary ; if { enable } start ; expression=`{ enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc enable__byte,enable__bit ; if { enable } body start ; temporary @ 0 := 1 ; Select temporary @ 0 main__temporary__171select0 equ main__temporary+0 main__temporary__171select0__byte equ main__temporary+0 main__temporary__171select0__bit equ 0 bsf main__temporary__171select0__byte,main__temporary__171select0__bit ; if { enable } body end ; if exp=`enable' false skip delay=2 ; Other expression=`{ enable }' delay=2 ; if { enable } end ; call send_byte {{ temporary }} movf main__temporary,w movwf send_byte__char call send_byte goto switch__150end switch__150block175: ; Set Enable Bit < Command = 0000 011 e > : ; enable := command @ 0 ; Alias variable for select command @ 0 main__command__177select0 equ main__command+0 main__command__177select0__byte equ main__command+0 main__command__177select0__bit equ 0 btfss main__command__177select0__byte,main__command__177select0__bit bcf enable__byte,enable__bit btfsc main__command__177select0__byte,main__command__177select0__bit bsf enable__byte,enable__bit switch__150end: goto switch__147end switch__147block181: ; Command = 0000 1 xxx : ; switch { command & 7 } movlw HIGH switch__183block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 switch__183block_start: addwf pcl___register,f goto switch__183block184 goto switch__183block188 goto switch__183block192 goto switch__183block196 goto switch__183block200 goto switch__183default204 goto switch__183default204 goto switch__183default204 switch__183block_end: ; switch_check 183 switch__183block_start switch__183block_end switch__183block184: ; Read Complement Mask < Command = 0000 1000 > : ; call send_byte {{ complement }} movf complement,w movwf send_byte__char call send_byte goto switch__183end switch__183block188: ; Read High Mask < Command = 0000 1001 > : ; call send_byte {{ high }} movf high,w movwf send_byte__char call send_byte goto switch__183end switch__183block192: ; Read Low Mask < Command = 0000 1010 > : ; call send_byte {{ low }} movf low,w movwf send_byte__char call send_byte goto switch__183end switch__183block196: ; Read Raising Mask < Command = 0000 1011 > : ; call send_byte {{ raising }} movf raising,w movwf send_byte__char call send_byte goto switch__183end switch__183block200: ; Read Falling Mask < Command = 0000 1100 > : ; call send_byte {{ falling }} movf falling,w movwf send_byte__char call send_byte goto switch__183end switch__183default204: ; Undefined command : switch__183end: goto switch__147end switch__147block209: ; Command = 0001 0 xxx : ; bit := command & 1 movlw 1 andwf main__command,w movwf main__bit ; switch { {{ command >> 1 }} & 3 } movlw HIGH switch__212block_start movwf pclath___register bcf c___byte,c___bit rrf main__command,w andlw 3 ; case 0 ; case 1 ; case 2 ; case 3 switch__212block_start: addwf pcl___register,f goto switch__212block213 goto switch__212block217 goto switch__212block221 goto switch__212block225 switch__212block_end: ; switch_check 212 switch__212block_start switch__212block_end switch__212block213: ; Read High Threshold < Command = 0001 000 b > : ; call send_byte {{ thresholds_high ~~ {{ bit }} }} movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__212end switch__212block217: ; Read Low Threshold < Command = 0001 001 b > : ; call send_byte {{ thresholds_low ~~ {{ bit }} }} movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf indf___register,w movwf send_byte__char call send_byte goto switch__212end switch__212block221: ; Set High Threshold < Command = 0001 010 b > : ; thresholds_high ~~ {{ bit }} := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__223byte0 movlw LOW thresholds_high addwf main__bit,w movwf fsr___register movf main__223byte0,w movwf indf___register goto switch__212end switch__212block225: ; Set Low Threshold < Command = 0001 011 b > : ; thresholds_low ~~ {{ bit }} := get_byte {{ }} call get_byte movf get_byte__0return__byte,w movwf main__227byte0 movlw LOW thresholds_low addwf main__bit,w movwf fsr___register movf main__227byte0,w movwf indf___register switch__212end: goto switch__147end switch__147block231: ; temporary := command & io_mask movlw 3 andwf main__command,w movwf main__temporary ; switch { {{ command >> 2 }} & 7 } movlw HIGH switch__233block_start movwf pclath___register rrf main__command,w movwf main__233byte0 rrf main__233byte0,w andlw 7 ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 switch__233block_start: addwf pcl___register,f goto switch__233block234 goto switch__233block238 goto switch__233block242 goto switch__233block246 goto switch__233block250 goto switch__233default254 goto switch__233default254 goto switch__233default254 switch__233block_end: ; switch_check 233 switch__233block_start switch__233block_end switch__233block234: ; Set Complement Mask < Command = 0010 00 cc > : ; complement := temporary movf main__temporary,w movwf complement goto switch__233end switch__233block238: ; Set High Mask < Command = 0010 01 hh > : ; high := temporary movf main__temporary,w movwf high goto switch__233end switch__233block242: ; Set Low Mask < Command = 0010 10 ll > : ; low := temporary movf main__temporary,w movwf low goto switch__233end switch__233block246: ; Set Raising Mask < Command = 0010 11 rr > : ; raising := temporary movf main__temporary,w movwf raising goto switch__233end switch__233block250: ; Set Falling Mask < Command = 0011 00 ff > : ; falling := temporary movf main__temporary,w movwf falling goto switch__233end switch__233default254: ; Do nothing : switch__233end: goto switch__147end switch__147default259: ; Do nothing : switch__147end: goto switch__144end switch__144block264: ; Do nothing < Command = 10 xx xxxx > : goto switch__144end switch__144block267: ; Command = 11 xx xxxx : ; switch { {{ command >> 3 }} & 7 } movlw HIGH switch__269block_start movwf pclath___register rrf main__command,w movwf main__269byte0 rrf main__269byte0,f rrf main__269byte0,w andlw 7 ; case 0 1 2 3 4 ; case 5 ; case 6 ; case 7 switch__269block_start: addwf pcl___register,f goto switch__269block270 goto switch__269block270 goto switch__269block270 goto switch__269block270 goto switch__269block270 goto switch__269block274 goto switch__269block288 goto switch__269block306 switch__269block_end: ; switch_check 269 switch__269block_start switch__269block_end switch__269block270: ; Command = 1100 xxxx or 1110 0 xxx : ; Do nothing : goto switch__269end switch__269block274: ; Read Interrupt Bits < Command = 1110 1111 > : ; if { {{ command & 7 }} = 7 } start movlw 7 andwf main__command,w movwf main__276byte0 movlw 7 subwf main__276byte0,w ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=6 false_delay=0 true_size=8 false_size=0 btfss z___byte,z___bit goto label276__1end ; if { {{ command & 7 }} = 7 } body start ; Return Interrupt Bits : ; temporary := 0 clrf main__temporary ; if { interrupt_enable } start ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_enable__byte,interrupt_enable__bit ; if { interrupt_enable } body start ; temporary @ 1 := 1 ; Select temporary @ 1 main__temporary__280select0 equ main__temporary+0 main__temporary__280select0__byte equ main__temporary+0 main__temporary__280select0__bit equ 1 bsf main__temporary__280select0__byte,main__temporary__280select0__bit ; if { interrupt_enable } body end ; if exp=`interrupt_enable' false skip delay=2 ; Other expression=`{ interrupt_enable }' delay=2 ; if { interrupt_enable } end ; if { interrupt_pending } start ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc interrupt_pending__byte,interrupt_pending__bit ; if { interrupt_pending } body start ; temporary @ 0 := 1 ; Select temporary @ 0 main__temporary__283select0 equ main__temporary+0 main__temporary__283select0__byte equ main__temporary+0 main__temporary__283select0__bit equ 0 bsf main__temporary__283select0__byte,main__temporary__283select0__bit ; if { interrupt_pending } body end ; if exp=`interrupt_pending' false skip delay=2 ; Other expression=`{ interrupt_pending }' delay=2 ; if { interrupt_pending } end ; call send_byte {{ temporary }} movf main__temporary,w movwf send_byte__char call send_byte ; if { {{ command & 7 }} = 7 } body end label276__1end: ; if exp=` {{ command & 7 }} = 7 ' empty false ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 ; if { {{ command & 7 }} = 7 } end goto switch__269end switch__269block288: ; Shared Interrupt commands < Command = 1111 0 xxx > : ; switch { command & 7 } movlw HIGH switch__290block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 1 2 3 ; case 4 5 ; case 6 7 switch__290block_start: addwf pcl___register,f goto switch__290block291 goto switch__290block291 goto switch__290block291 goto switch__290block291 goto switch__290block296 goto switch__290block296 goto switch__290block300 goto switch__290block300 switch__290block_end: ; switch_check 290 switch__290block_start switch__290block_end switch__290block291: ; Set interrupt bits < Command = 1111 10 ep > : ; interrupt_enable := command @ 1 ; Alias variable for select command @ 1 main__command__293select0 equ main__command+0 main__command__293select0__byte equ main__command+0 main__command__293select0__bit equ 1 bcf interrupt_enable__byte,interrupt_enable__bit btfsc main__command__293select0__byte,main__command__293select0__bit bsf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__294select0 equ main__command+0 main__command__294select0__byte equ main__command+0 main__command__294select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc main__command__294select0__byte,main__command__294select0__bit bsf interrupt_pending__byte,interrupt_pending__bit goto switch__290end switch__290block296: ; Set Interrupt Pending < Command = 1111 110 p > : ; interrupt_pending := command @ 0 ; Alias variable for select command @ 0 main__command__298select0 equ main__command+0 main__command__298select0__byte equ main__command+0 main__command__298select0__bit equ 0 bcf interrupt_pending__byte,interrupt_pending__bit btfsc main__command__298select0__byte,main__command__298select0__bit bsf interrupt_pending__byte,interrupt_pending__bit goto switch__290end switch__290block300: ; Set Interrupt Enable < Command = 1110 111 e > : ; interrupt_enable := command @ 0 ; Alias variable for select command @ 0 main__command__302select0 equ main__command+0 main__command__302select0__byte equ main__command+0 main__command__302select0__bit equ 0 bcf interrupt_enable__byte,interrupt_enable__bit btfsc main__command__302select0__byte,main__command__302select0__bit bsf interrupt_enable__byte,interrupt_enable__bit switch__290end: goto switch__269end switch__269block306: ; Shared commands < Command = 1111 1 xxx > : ; switch { command & 7 } movlw HIGH switch__308block_start movwf pclath___register movlw 7 andwf main__command,w ; case 0 ; case 1 ; case 2 ; case 3 ; case 4 ; case 5 ; case 6 ; case 7 switch__308block_start: addwf pcl___register,f goto switch__308block309 goto switch__308block313 goto switch__308block317 goto switch__308block321 goto switch__308block325 goto switch__308block333 goto switch__308block337 goto switch__308block342 switch__308block_end: ; switch_check 308 switch__308block_start switch__308block_end switch__308block309: ; Clock Decrement < Command = 1111 1000 > : ; osccal := osccal - osccal_unit movlw 240 ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 addwf osccal,f ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 goto switch__308end switch__308block313: ; Clock Increment < Command = 1111 1001 > : ; osccal := osccal + osccal_unit movlw 16 ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 addwf osccal,f ; Switch from register bank 1 to register bank 0 bcf rp0___byte,rp0___bit ; Register bank is now 0 goto switch__308end switch__308block317: ; Clock Read < Command = 1111 1010 > : ; call send_byte {{ osccal }} ; Switch from register bank 0 to register bank 1 (which contains osccal) bsf rp0___byte,rp0___bit ; Register bank is now 1 movf osccal,w ; Switch from register bank 1 to register bank 0 (which contains send_byte__char) bcf rp0___byte,rp0___bit ; Register bank is now 0 movwf send_byte__char call send_byte goto switch__308end switch__308block321: ; Clock Pulse < Command = 1111 1011 > : ; call send_byte {{ 0 }} clrf send_byte__char call send_byte goto switch__308end switch__308block325: ; ID Next < Command = 1111 1100 > : ; call send_byte {{ id ~~ {{ id_index }} }} incf id_index,w clrf pclath___register call id movwf send_byte__char call send_byte ; id_index := id_index + 1 incf id_index,f ; if { id_index >= id . size } start movlw 48 subwf id_index,w ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc c___byte,c___bit ; if { id_index >= id . size } body start ; id_index := 0 clrf id_index ; if { id_index >= id . size } body end ; if exp=` id_index >= id . size ' false skip delay=4 ; Other expression=`{ id_index >= id . size }' delay=4 ; if { id_index >= id . size } end goto switch__308end switch__308block333: ; ID Reset < Command = 1111 1101 > : ; id_index := 0 clrf id_index goto switch__308end switch__308block337: ; Glitch Read < Command = 1111 1110 > : ; call send_byte {{ glitch }} movf glitch,w movwf send_byte__char call send_byte ; glitch := 0 clrf glitch goto switch__308end switch__308block342: ; Glitch < Command = 1111 1111 > : ; if { glitch != 0xff } start incf glitch,w ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { glitch != 0xff } body start ; glitch := glitch + 1 incf glitch,f ; if { glitch != 0xff } body end ; if exp=` glitch != 0xff ' false skip delay=3 ; Other expression=`{ glitch != 0xff }' delay=3 ; if { glitch != 0xff } end switch__308end: switch__269end: switch__144end: goto main__139loop__forever ; loop_forever ... end ; procedure main end ; procedure delay start ; optimize 0 delay: delay__variables__base equ global__variables__bank0+19 delay__bytes__base equ delay__variables__base+0 delay__bits__base equ delay__variables__base+9 delay__total__bytes equ 9 delay__356byte1 equ delay__bytes__base+8 delay__412byte0 equ delay__bytes__base+8 delay__389byte0 equ delay__bytes__base+8 delay__378byte3 equ delay__bytes__base+8 delay__410byte1 equ delay__bytes__base+8 ; arguments_none ; uniform_delay delay_instructions ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; This procedure will delay for one third of a bit time . ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__channel equ delay__bytes__base+0 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__current equ delay__bytes__base+1 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__changed equ delay__bytes__base+2 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__previous equ delay__bytes__base+3 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__not_current equ delay__bytes__base+4 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__counter equ delay__bytes__base+5 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__mask equ delay__bytes__base+6 ; Uniform delay remaining = 131 Accumulated Delay = 0 delay__result equ delay__bytes__base+7 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Uniform delay remaining = 131 Accumulated Delay = 0 ; Kick the dog : ; Uniform delay remaining = 131 Accumulated Delay = 0 ; watch_dog_reset clrwdt ; Uniform delay remaining = 130 Accumulated Delay = 1 ; Uniform delay remaining = 130 Accumulated Delay = 1 ; channel := {{ counter >> 1 }} & 1 bcf c___byte,c___bit rrf delay__counter,w andlw 1 movwf delay__channel ; Uniform delay remaining = 126 Accumulated Delay = 5 ; counter := counter + 1 incf delay__counter,f ; Uniform delay remaining = 125 Accumulated Delay = 6 ; if { counter @ 0 } start ; Alias variable for select counter @ 0 delay__counter__378select0 equ delay__counter+0 delay__counter__378select0__byte equ delay__counter+0 delay__counter__378select0__bit equ 0 ; expression=`{ counter @ 0 }' exp_delay=0 true_delay=40 false_delay=100 true_size=44 false_size=49 btfss delay__counter__378select0__byte,delay__counter__378select0__bit goto label378__1false label378__1true: ; if { counter @ 0 } body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Set up and wait for acquistion : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; addcon0 := {{ channel << 4 }} | 0x41 swapf delay__channel,w andlw 240 iorlw 65 movwf addcon0 ; Uniform delay remaining = 121 Accumulated Delay = 4 ; Setup for interrupts : ; Uniform delay remaining = 121 Accumulated Delay = 4 ; previous := current movf delay__current,w movwf delay__previous ; Uniform delay remaining = 119 Accumulated Delay = 6 ; Read the I / O port once : ; Uniform delay remaining = 119 Accumulated Delay = 6 ; current := inputs ^ complement movf inputs,w xorwf complement,w movwf delay__current ; Uniform delay remaining = 116 Accumulated Delay = 9 ; not_current := current ^ io_mask movlw 3 xorwf delay__current,w movwf delay__not_current ; Uniform delay remaining = 113 Accumulated Delay = 12 ; changed := current ^ previous movf delay__current,w xorwf delay__previous,w movwf delay__changed ; Uniform delay remaining = 110 Accumulated Delay = 15 ; Uniform delay remaining = 110 Accumulated Delay = 15 ; See about triggering the interrupt_pending flag : ; Uniform delay remaining = 110 Accumulated Delay = 15 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } start movf low,w andwf delay__not_current,w movwf delay__389byte0 movf high,w andwf delay__current,w iorwf delay__389byte0,f movf delay__changed,w andwf delay__current,w andwf raising,w iorwf delay__389byte0,f movf delay__changed,w andwf delay__not_current,w andwf falling,w iorwf delay__389byte0,w ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 btfss z___byte,z___bit ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body start ; Uniform delay remaining = 110 Accumulated Delay = 0 ; interrupt_pending := 1 bsf interrupt_pending__byte,interrupt_pending__bit ; Uniform delay remaining = 109 Accumulated Delay = 1 ; Uniform delay remaining = 109 Accumulated Delay = 1 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } body end ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 ' false skip delay=16 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 }' delay=16 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & not_current & falling }} != 0 } end ; Uniform delay remaining = 94 Accumulated Delay = 31 ; Uniform delay remaining = 94 Accumulated Delay = 31 ; Send an interrupt if interrupts are enabled : ; Uniform delay remaining = 94 Accumulated Delay = 31 ; if { interrupt_pending && interrupt_enable } start ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 btfsc interrupt_pending__byte,interrupt_pending__bit goto label394__2true label394__2false: ; Delay 2 cycles nop nop goto and394__0false label394__2true: ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 btfss interrupt_enable__byte,interrupt_enable__bit goto label394__1false label394__1true: and394__0true: ; if { interrupt_pending && interrupt_enable } body start ; Uniform delay remaining = 94 Accumulated Delay = 0 ; Shove serial out to low : ; Uniform delay remaining = 94 Accumulated Delay = 0 ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; Uniform delay remaining = 93 Accumulated Delay = 1 ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; Uniform delay remaining = 92 Accumulated Delay = 2 ; Uniform delay remaining = 92 Accumulated Delay = 2 ; if { interrupt_pending && interrupt_enable } body end goto label394__1end label394__1false: ; Delay 3 cycles nop nop nop ; if exp=`interrupt_enable' total delay=6 ; if exp=`interrupt_enable' generic label394__1end: ; Other expression=`interrupt_enable' delay=6 ; if exp=`interrupt_pending' total delay=9 ; if exp=`interrupt_pending' generic label394__2end: ; Other expression=`interrupt_pending' delay=9 and394__0false: and394__0end: ; if { interrupt_pending && interrupt_enable } end ; Uniform delay remaining = 85 Accumulated Delay = 40 ; Uniform delay remaining = 85 Accumulated Delay = 40 ; if { counter @ 0 } body end ; Delay 59 cycles movlw 19 movwf delay__378byte3 delay__378delay2: decfsz delay__378byte3,f goto delay__378delay2 nop goto label378__1end label378__1false: ; else body start ; Uniform delay remaining = 125 Accumulated Delay = 0 ; Start the conversion : ; Uniform delay remaining = 125 Accumulated Delay = 0 ; go_done := 1 bsf go_done__byte,go_done__bit ; Uniform delay remaining = 124 Accumulated Delay = 1 ; mask := 0 clrf delay__mask ; Uniform delay remaining = 123 Accumulated Delay = 2 ; if { channel @ 0 } start ; Alias variable for select channel @ 0 delay__channel__403select0 equ delay__channel+0 delay__channel__403select0__byte equ delay__channel+0 delay__channel__403select0__bit equ 0 ; expression=`{ channel @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 btfsc delay__channel__403select0__byte,delay__channel__403select0__bit ; if { channel @ 0 } body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 1 := 1 ; Select mask @ 1 delay__mask__404select0 equ delay__mask+0 delay__mask__404select0__byte equ delay__mask+0 delay__mask__404select0__bit equ 1 bsf delay__mask__404select0__byte,delay__mask__404select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; if { channel @ 0 } body end btfss delay__channel__403select0__byte,delay__channel__403select0__bit ; else body start ; Uniform delay remaining = 123 Accumulated Delay = 0 ; mask @ 0 := 1 ; Select mask @ 0 delay__mask__406select0 equ delay__mask+0 delay__mask__406select0__byte equ delay__mask+0 delay__mask__406select0__bit equ 0 bsf delay__mask__406select0__byte,delay__mask__406select0__bit ; Uniform delay remaining = 122 Accumulated Delay = 1 ; Uniform delay remaining = 122 Accumulated Delay = 1 ; else body end ; if exp=` channel @ 0 ' single true and false skip delay=4 ; Other expression=`{ channel @ 0 }' delay=4 ; if { channel @ 0 } end ; Uniform delay remaining = 119 Accumulated Delay = 6 ; Delaying 60 uS is way longer than necessary for the conversion ; Uniform delay remaining = 119 Accumulated Delay = 6 ; to complete . ; Uniform delay remaining = 119 Accumulated Delay = 6 ; nop 60 ; Delay 60 cycles movlw 19 movwf delay__410byte1 delay__410delay0: decfsz delay__410byte1,f goto delay__410delay0 nop nop ; Uniform delay remaining = 59 Accumulated Delay = 66 ; result := addres movf addres,w movwf delay__result ; Uniform delay remaining = 57 Accumulated Delay = 68 ; analogs ~~ {{ channel }} := result movf delay__result,w movwf delay__412byte0 movlw LOW analogs addwf delay__channel,w movwf fsr___register movf delay__412byte0,w movwf indf___register ; Uniform delay remaining = 50 Accumulated Delay = 75 ; if { result <= thresholds_low ~~ {{ channel }} } start movlw LOW thresholds_low addwf delay__channel,w movwf fsr___register movf indf___register,w subwf delay__result,w btfsc z___byte,z___bit bcf c___byte,c___bit ; expression=`{ result <= thresholds_low ~~ {{ channel }} }' exp_delay=7 true_delay=3 false_delay=0 true_size=3 false_size=0 btfss c___byte,c___bit goto label413__0true label413__0false: ; Delay 2 cycles nop nop goto label413__0end label413__0true: ; if { result <= thresholds_low ~~ {{ channel }} } body start ; Uniform delay remaining = 50 Accumulated Delay = 0 ; inputs := inputs & {{ mask ^ io_mask }} movlw 3 xorwf delay__mask,w andwf inputs,f ; Uniform delay remaining = 47 Accumulated Delay = 3 ; Uniform delay remaining = 47 Accumulated Delay = 3 ; if { result <= thresholds_low ~~ {{ channel }} } body end ; if exp=` result <= thresholds_low ~~ {{ channel }} ' total delay=13 ; if exp=` result <= thresholds_low ~~ {{ channel }} ' generic label413__0end: ; Other expression=`{ result <= thresholds_low ~~ {{ channel }} }' delay=13 ; if { result <= thresholds_low ~~ {{ channel }} } end ; Uniform delay remaining = 37 Accumulated Delay = 88 ; if { result >= thresholds_high ~~ {{ channel }} } start movlw LOW thresholds_high addwf delay__channel,w movwf fsr___register movf indf___register,w subwf delay__result,w ; expression=`{ result >= thresholds_high ~~ {{ channel }} }' exp_delay=5 true_delay=2 false_delay=0 true_size=2 false_size=0 btfsc c___byte,c___bit goto label416__0true label416__0false: ; Delay 1 cycles nop goto label416__0end label416__0true: ; if { result >= thresholds_high ~~ {{ channel }} } body start ; Uniform delay remaining = 37 Accumulated Delay = 0 ; inputs := inputs | mask movf delay__mask,w iorwf inputs,f ; Uniform delay remaining = 35 Accumulated Delay = 2 ; Uniform delay remaining = 35 Accumulated Delay = 2 ; if { result >= thresholds_high ~~ {{ channel }} } body end ; if exp=` result >= thresholds_high ~~ {{ channel }} ' total delay=10 ; if exp=` result >= thresholds_high ~~ {{ channel }} ' generic label416__0end: ; Other expression=`{ result >= thresholds_high ~~ {{ channel }} }' delay=10 ; if { result >= thresholds_high ~~ {{ channel }} } end ; Uniform delay remaining = 27 Accumulated Delay = 98 ; inputs := inputs & io_mask movlw 3 andwf inputs,f ; Uniform delay remaining = 25 Accumulated Delay = 100 ; Uniform delay remaining = 25 Accumulated Delay = 100 ; else body end ; if exp=` counter @ 0 ' total delay=103 ; if exp=` counter @ 0 ' generic label378__1end: ; Other expression=`{ counter @ 0 }' delay=103 ; if { counter @ 0 } end ; Uniform delay remaining = 22 Accumulated Delay = 109 ; Uniform delay remaining = 22 Accumulated Delay = 109 ; Soak up remaining 22 cycles ; Delay 22 cycles movlw 7 movwf delay__356byte1 delay__356delay0: decfsz delay__356byte1,f goto delay__356delay0 ; procedure delay end retlw 0 ; optimize 1 ; procedure get_byte start get_byte: get_byte__variables__base equ global__variables__bank0+28 get_byte__bytes__base equ get_byte__variables__base+0 get_byte__bits__base equ get_byte__variables__base+3 get_byte__total__bytes equ 3 ; arguments_none get_byte__0return__byte equ get_byte__bytes__base+0 ; Wait for a character and return it . ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That ; way the next call to get_byte < > will sychronize on the start ; bit instead of possibly starting a little later . get_byte__count equ get_byte__bytes__base+1 get_byte__char equ get_byte__bytes__base+2 ; Wait for start bit : ; receiving := 1 bsf receiving__byte,receiving__bit ; `while serial_in ...' start get_byte__439while__continue: ; expression=`serial_in' exp_delay=0 true_delay=136 false_delay=2 true_size=2 false_size=1 btfss serial_in__byte,serial_in__bit goto get_byte__439while__break ; call delay {{ }} call delay goto get_byte__439while__continue ; if exp=`serial_in' false goto ; Other expression=`serial_in' delay=-1 get_byte__439while__break: ; `while serial_in ...' end ; Clear interrupts and interrupt pending : ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; Skip over start bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; Sample in the middle third of each data bit : ; 1 cycle : ; char := 0 clrf get_byte__char ; 2 cycles to set up loop : ; 1 + 1 + 2 = 4 ; nop extra_instructions_per_bit - 4 ; Delay 5 cycles nop nop nop nop nop ; `count_down count 8 ...' start movlw 8 movwf get_byte__count get_byte__458_loop: ; call delay {{ }} call delay ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf get_byte__char,f ; 2 cycles : ; if { serial_in } start ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 btfsc serial_in__byte,serial_in__bit ; if { serial_in } body start ; char @ 7 := 1 ; Select char @ 7 get_byte__char__464select0 equ get_byte__char+0 get_byte__char__464select0__byte equ get_byte__char+0 get_byte__char__464select0__bit equ 7 bsf get_byte__char__464select0__byte,get_byte__char__464select0__bit ; if { serial_in } body end ; if exp=`serial_in' false skip delay=2 ; Other expression=`{ serial_in }' delay=2 ; if { serial_in } end ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 2 + 2 + 3 = 7 ; nop extra_instructions_per_bit - 7 ; Delay 2 cycles nop nop decfsz get_byte__count,f goto get_byte__458_loop get_byte__458_done: ; `count_down count 8 ...' end ; Skip over 2 / 3 ' s of stop bit : ; call delay {{ }} call delay ; call delay {{ }} call delay ; return char movf get_byte__char,w movwf get_byte__0return__byte retlw 0 ; procedure get_byte end ; procedure send_byte start send_byte: send_byte__variables__base equ global__variables__bank0+31 send_byte__bytes__base equ send_byte__variables__base+0 send_byte__bits__base equ send_byte__variables__base+2 send_byte__total__bytes equ 2 send_byte__char equ send_byte__bytes__base+0 ; Send < char > to < tx > : send_byte__count equ send_byte__bytes__base+1 ; < receiving > will be 1 if the last get / put routine was a get . ; Before we start transmitting a response back , we want to ensure ; that there has been enough time to turn the line line around . ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just ; for good measure . Technically , the second call to delay < > ; is not really needed . ; if { receiving } start ; expression=`{ receiving }' exp_delay=0 true_delay=269 false_delay=0 true_size=3 false_size=0 btfss receiving__byte,receiving__bit goto label495__0end ; if { receiving } body start ; receiving := 0 bcf receiving__byte,receiving__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; if { receiving } body end label495__0end: ; if exp=`receiving' empty false ; Other expression=`{ receiving }' delay=-1 ; if { receiving } end ; Send the start bit : ; 1 cycle : ; serial_out := 0 bcf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for loop setup : ; 1 + 2 = 3 ; nop extra_instructions_per_bit - 3 ; Delay 6 cycles nop nop nop nop nop nop ; Send the data : ; `count_down count 8 ...' start movlw 8 movwf send_byte__count send_byte__512_loop: ; 4 cycles : ; serial_out := char @ 0 ; Alias variable for select char @ 0 send_byte__char__514select0 equ send_byte__char+0 send_byte__char__514select0__byte equ send_byte__char+0 send_byte__char__514select0__bit equ 0 btfss send_byte__char__514select0__byte,send_byte__char__514select0__bit bcf serial_out__byte,serial_out__bit btfsc send_byte__char__514select0__byte,send_byte__char__514select0__bit bsf serial_out__byte,serial_out__bit ; 2 cycles : ; char := char >> 1 bcf c___byte,c___bit rrf send_byte__char,f ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 3 cycles at end of loop : ; 4 + 2 + 3 = 9 = no NOP ' s needed : decfsz send_byte__count,f goto send_byte__512_loop send_byte__512_done: ; `count_down count 8 ...' end ; Send the stop bit : ; 1 cycle to close out previous loop : ; nop 1 ; Delay 1 cycles nop ; 1 cycle : ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; call delay {{ }} call delay ; call delay {{ }} call delay ; call delay {{ }} call delay ; 2 cycles for call / return : ; 2 cycles for argument : ; 1 + 2 + 2 = 5 ; nop extra_instructions_per_bit - 5 ; Delay 4 cycles nop nop nop nop ; procedure send_byte end retlw 0 ; procedure reset start reset: reset__variables__base equ global__variables__bank0+33 reset__bytes__base equ reset__variables__base+0 reset__bits__base equ reset__variables__base+2 reset__total__bytes equ 2 reset__557byte0 equ reset__bytes__base+1 reset__558byte0 equ reset__bytes__base+1 ; arguments_none ; This procedure will initialize all of the registers : reset__index equ reset__bytes__base+0 ; inputs := 0 clrf inputs ; high := 0 clrf high ; low := 0 clrf low ; raising := 0 clrf raising ; falling := 0 clrf falling ; complement := 0 clrf complement ; interrupt_enable := 0 bcf interrupt_enable__byte,interrupt_enable__bit ; interrupt_pending := 0 bcf interrupt_pending__byte,interrupt_pending__bit ; index := 0 clrf reset__index ; enable := 1 bsf enable__byte,enable__bit ; `while index < 2 ...' start reset__556while__continue: movlw 2 subwf reset__index,w ; expression=` index < 2 ' exp_delay=2 true_delay=17 false_delay=2 true_size=16 false_size=1 btfsc c___byte,c___bit goto reset__556while__break ; thresholds_high ~~ {{ index }} := 0xc0 movlw 192 movwf reset__557byte0 movlw LOW thresholds_high addwf reset__index,w movwf fsr___register movf reset__557byte0,w movwf indf___register ; thresholds_low ~~ {{ index }} := 0x40 movlw 64 movwf reset__558byte0 movlw LOW thresholds_low addwf reset__index,w movwf fsr___register movf reset__558byte0,w movwf indf___register ; index := index + 1 incf reset__index,f goto reset__556while__continue ; if exp=` index < 2 ' false goto ; Other expression=` index < 2 ' delay=-1 reset__556while__break: ; `while index < 2 ...' end ; glitch := 0 clrf glitch ; id_index := 0 clrf id_index ; serial_out := 1 bsf serial_out__byte,serial_out__bit ; procedure reset end retlw 0 ; Register bank 0 used 35 bytes of 96 available bytes ; Register bank 1 used 0 bytes of 32 available bytes end