radix dec ; Code bank 0; Start address: 0; End address: 1023 org 0 ; #pin 12 = vref ; Define start addresses for data regions shared___globals equ 32 __indf equ 0 __pcl equ 2 __status equ 3 __fsr equ 4 __c___byte equ 3 __c___bit equ 0 __z___byte equ 3 __z___bit equ 2 __rp0___byte equ 3 __rp0___bit equ 5 __rp1___byte equ 3 __rp1___bit equ 6 __irp___byte equ 3 __irp___bit equ 7 __pclath equ 10 __cb0___byte equ 10 __cb0___bit equ 3 __cb1___byte equ 10 __cb1___bit equ 4 ; # Copyright (c) 2005 by Wayne C. Gramlich ; # All rights reserved. ; buffer = 'micro_step' ; line_number = 6 ; library _pic16f676 entered ; # Copyright (c) 2004 by Wayne C. Gramlich ; # All rights reserved. ; buffer = '_pic16f676' ; line_number = 5 ; processor pic16f676 ; line_number = 6 ; configure_address 0x2007 ; line_number = 7 ; configure_fill 0x0000 ; line_number = 8 ; configure_option bg: bg11 = 0x3000 ; line_number = 9 ; configure_option bg: bg10 = 0x2000 ; line_number = 10 ; configure_option bg: bg01 = 0x1000 ; line_number = 11 ; configure_option bg: bg00 = 0x0000 ; line_number = 12 ; configure_option cpd: on = 0x000 ; line_number = 13 ; configure_option cpd: off = 0x100 ; line_number = 14 ; configure_option cp: on = 0x00 ; line_number = 15 ; configure_option cp: off = 0x80 ; line_number = 16 ; configure_option boden: on = 0x40 ; line_number = 17 ; configure_option boden: off = 0x00 ; line_number = 18 ; configure_option mclre: on = 0x20 ; line_number = 19 ; configure_option mclre: off = 0x00 ; line_number = 20 ; configure_option pwrte: on = 0x00 ; line_number = 21 ; configure_option pwrte: off = 0x10 ; line_number = 22 ; configure_option wdte: on = 8 ; line_number = 23 ; configure_option wdte: off = 0 ; line_number = 24 ; configure_option fosc: rc_clk = 7 ; line_number = 25 ; configure_option fosc: rc_no_clk = 6 ; line_number = 26 ; configure_option fosc: int_clk = 5 ; line_number = 27 ; configure_option fosc: int_no_clk = 4 ; line_number = 28 ; configure_option fosc: ec = 3 ; line_number = 29 ; configure_option fosc: hs = 2 ; line_number = 30 ; configure_option fosc: xt = 1 ; line_number = 31 ; configure_option fosc: lp = 0 ; line_number = 32 ; code_bank 0x0 : 0x3ff ; line_number = 33 ; data_bank 0x0 : 0x7f ; line_number = 34 ; data_bank 0x80 : 0xff ; line_number = 35 ; shared_region 0x20 : 0x5f ; line_number = 36 ; interrupts_possible ; line_number = 37 ; osccal_register_symbol _osccal ; line_number = 38 ; osccal_at_address 0x3ff ; line_number = 39 ; packages pdip=14, soic=14, tssop=14 ; line_number = 40 ; pin vdd, power_supply ; line_number = 41 ; pin_bindings pdip=1, soic=1, tssop=1 ; line_number = 42 ; pin ra5_in, ra5_out, t1cki, osc1, clkin ; line_number = 43 ; pin_bindings pdip=2, soic=2, tssop=2 ; line_number = 44 ; bind_to _porta@5 ; line_number = 45 ; or_if ra5_in _trisa 32 ; line_number = 46 ; or_if ra5_out _trisa 0 ; line_number = 47 ; pin ra4_in, ra4_out, t1g, osc2, an3, clkout ; line_number = 48 ; pin_bindings pdip=3, soic=3, tssop=3 ; line_number = 49 ; bind_to _porta@4 ; line_number = 50 ; or_if ra4_in _trisa 16 ; line_number = 51 ; or_if ra4_out _trisa 0 ; line_number = 52 ; or_if an3 _trisa 16 ; line_number = 53 ; or_if an3 _ansel 8 ; line_number = 54 ; or_if an3 _adcon0 1 ; line_number = 55 ; pin ra3_in, mclr, vpp ; line_number = 56 ; pin_bindings pdip=4, soic=4, tssop=4 ; line_number = 57 ; bind_to _porta@4 ; line_number = 58 ; or_if ra3_in _trisa 8 ; line_number = 59 ; pin rc5_in, rc5_out ; line_number = 60 ; pin_bindings pdip=5, soic=5, tssop=5 ; line_number = 61 ; bind_to _portc@5 ; line_number = 62 ; or_if rc5_in _trisc 32 ; line_number = 63 ; or_if rc5_out _trisc 0 ; line_number = 64 ; pin rc4_in, rc4_out ; line_number = 65 ; pin_bindings pdip=6, soic=6, tssop=6 ; line_number = 66 ; bind_to _portc@4 ; line_number = 67 ; or_if rc4_in _trisc 16 ; line_number = 68 ; or_if rc4_out _trisc 0 ; line_number = 69 ; pin rc3_in, rc3_out, an7 ; line_number = 70 ; pin_bindings pdip=7, soic=7, tssop=7 ; line_number = 71 ; bind_to _portc@3 ; line_number = 72 ; or_if rc3_in _trisc 8 ; line_number = 73 ; or_if rc3_out _trisc 0 ; line_number = 74 ; or_if an7 _trisc 8 ; line_number = 75 ; or_if an7 _ansel 128 ; line_number = 76 ; or_if an7 _adcon0 1 ; line_number = 77 ; pin rc2_in, rc2_out, an6 ; line_number = 78 ; pin_bindings pdip=8, soic=8, tssop=8 ; line_number = 79 ; bind_to _portc@2 ; line_number = 80 ; or_if rc2_in _trisc 4 ; line_number = 81 ; or_if rc2_out _trisc 0 ; line_number = 82 ; or_if an6 _trisc 4 ; line_number = 83 ; or_if an6 _ansel 64 ; line_number = 84 ; or_if an6 _adcon0 1 ; line_number = 85 ; pin rc1_in, rc1_out, an5 ; line_number = 86 ; pin_bindings pdip=9, soic=9, tssop=9 ; line_number = 87 ; bind_to _portc@1 ; line_number = 88 ; or_if rc1_in _trisc 2 ; line_number = 89 ; or_if rc1_out _trisc 0 ; line_number = 90 ; or_if an5 _trisc 2 ; line_number = 91 ; or_if an5 _ansel 32 ; line_number = 92 ; or_if an5 _adcon0 1 ; line_number = 93 ; pin rc0_in, rc0_out, an4 ; line_number = 94 ; pin_bindings pdip=10, soic=10, tssop=10 ; line_number = 95 ; bind_to _portc@0 ; line_number = 96 ; or_if rc0_in _trisc 1 ; line_number = 97 ; or_if rc0_out _trisc 0 ; line_number = 98 ; or_if an4 _trisc 1 ; line_number = 99 ; or_if an4 _ansel 16 ; line_number = 100 ; or_if an4 _adcon0 1 ; line_number = 101 ; pin ra2_in, ra2_out, an2, cout, t0cki, int ; line_number = 102 ; pin_bindings pdip=11, soic=11, tssop=11 ; line_number = 103 ; bind_to _porta@2 ; line_number = 104 ; or_if ra2_in _trisa 4 ; line_number = 105 ; or_if ra2_out _trisa 0 ; line_number = 106 ; or_if an2 _trisa 4 ; line_number = 107 ; or_if an2 _ansel 4 ; line_number = 108 ; or_if an2 _adcon0 1 ; line_number = 109 ; pin ra1_in, ra1_out, an1, cin_minus, vref, icspclk ; line_number = 110 ; pin_bindings pdip=12, soic=12, tssop=12 ; line_number = 111 ; bind_to _porta@1 ; line_number = 112 ; or_if ra1_in _trisa 2 ; line_number = 113 ; or_if ra1_out _trisa 0 ; line_number = 114 ; or_if an1 _trisa 2 ; line_number = 115 ; or_if an1 _ansel 2 ; line_number = 116 ; or_if an1 _adcon0 1 ; line_number = 117 ; or_if vref _trisa 2 ; line_number = 118 ; or_if vref _ansel 2 ; line_number = 119 ; or_if vref _adcon0 33 ; line_number = 120 ; pin ra0_in, ra0_out, an0, cin_plus, icspdat ; line_number = 121 ; pin_bindings pdip=13, soic=13, tssop=13 ; line_number = 122 ; bind_to _porta@0 ; line_number = 123 ; or_if ra0_in _trisa 1 ; line_number = 124 ; or_if ra0_out _trisa 0 ; line_number = 125 ; or_if an0 _trisa 1 ; line_number = 126 ; or_if an0 _ansel 1 ; line_number = 127 ; or_if an0 _adcon0 1 ; line_number = 128 ; pin vss, ground ; line_number = 129 ; pin_bindings pdip=14, soic=14, tssop=14 ; line_number = 134 ; library _pic16f630_676 entered ; # Copyright (c) 2004 by Wayne C. Gramlich ; # All rights reserved. ; # Shared register definitions for the PIC16F630 and PIC16F676. ; buffer = '_pic16f630_676' ; line_number = 7 ; register _indf = _indf equ 0 ; line_number = 9 ; register _tmr0 = _tmr0 equ 1 ; line_number = 11 ; register _pcl = _pcl equ 2 ; line_number = 13 ; register _status = _status equ 3 ; line_number = 14 ; bind _rp0 = _status@5 _rp0___byte equ _status _rp0___bit equ 5 ; line_number = 15 ; bind _to = _status@4 _to___byte equ _status _to___bit equ 4 ; line_number = 16 ; bind _pd = _status@3 _pd___byte equ _status _pd___bit equ 3 ; line_number = 17 ; bind _z = _status@2 _z___byte equ _status _z___bit equ 2 ; line_number = 18 ; bind _dc = _status@1 _dc___byte equ _status _dc___bit equ 1 ; line_number = 19 ; bind _c = _status@0 _c___byte equ _status _c___bit equ 0 ; line_number = 21 ; register _fsr = _fsr equ 4 ; line_number = 23 ; register _porta = _porta equ 5 ; line_number = 24 ; register _ra = _ra equ 5 ; line_number = 25 ; bind _ra5 = _porta@5 _ra5___byte equ _porta _ra5___bit equ 5 ; line_number = 26 ; bind _ra4 = _porta@4 _ra4___byte equ _porta _ra4___bit equ 4 ; line_number = 27 ; bind _ra3 = _porta@3 _ra3___byte equ _porta _ra3___bit equ 3 ; line_number = 28 ; bind _ra2 = _porta@2 _ra2___byte equ _porta _ra2___bit equ 2 ; line_number = 29 ; bind _ra1 = _porta@1 _ra1___byte equ _porta _ra1___bit equ 1 ; line_number = 30 ; bind _ra0 = _porta@0 _ra0___byte equ _porta _ra0___bit equ 0 ; line_number = 32 ; register _portc = _portc equ 7 ; line_number = 33 ; register _rc = _rc equ 7 ; line_number = 34 ; bind _rc5 = _portc@5 _rc5___byte equ _portc _rc5___bit equ 5 ; line_number = 35 ; bind _rc4 = _portc@4 _rc4___byte equ _portc _rc4___bit equ 4 ; line_number = 36 ; bind _rc3 = _portc@3 _rc3___byte equ _portc _rc3___bit equ 3 ; line_number = 37 ; bind _rc2 = _portc@2 _rc2___byte equ _portc _rc2___bit equ 2 ; line_number = 38 ; bind _rc1 = _portc@1 _rc1___byte equ _portc _rc1___bit equ 1 ; line_number = 39 ; bind _rc0 = _portc@0 _rc0___byte equ _portc _rc0___bit equ 0 ; line_number = 41 ; register _pclath = _pclath equ 10 ; line_number = 43 ; register _intcon = _intcon equ 11 ; line_number = 44 ; bind _gie = _intcon@7 _gie___byte equ _intcon _gie___bit equ 7 ; line_number = 45 ; bind _peie = _intcon@6 _peie___byte equ _intcon _peie___bit equ 6 ; line_number = 46 ; bind _t0ie = _intcon@5 _t0ie___byte equ _intcon _t0ie___bit equ 5 ; line_number = 47 ; bind _inte = _intcon@4 _inte___byte equ _intcon _inte___bit equ 4 ; line_number = 48 ; bind _raie = _intcon@3 _raie___byte equ _intcon _raie___bit equ 3 ; line_number = 49 ; bind _t0if = _intcon@2 _t0if___byte equ _intcon _t0if___bit equ 2 ; line_number = 50 ; bind _intf = _intcon@1 _intf___byte equ _intcon _intf___bit equ 1 ; line_number = 51 ; bind _raif = _intcon@0 _raif___byte equ _intcon _raif___bit equ 0 ; line_number = 53 ; register _pir1 = _pir1 equ 12 ; line_number = 54 ; bind _eeif = _pir1@7 _eeif___byte equ _pir1 _eeif___bit equ 7 ; line_number = 55 ; bind _cmif = _pir1@3 _cmif___byte equ _pir1 _cmif___bit equ 3 ; line_number = 56 ; bind _tmr1if = _pir1@0 _tmr1if___byte equ _pir1 _tmr1if___bit equ 0 ; line_number = 58 ; register _tmr1l = _tmr1l equ 14 ; line_number = 60 ; register _tmr1h = _tmr1h equ 15 ; line_number = 62 ; register _t1con = _t1con equ 16 ; line_number = 63 ; bind _t1ge = _t1con@6 _t1ge___byte equ _t1con _t1ge___bit equ 6 ; line_number = 64 ; bind _t1ckps1 = _t1con@5 _t1ckps1___byte equ _t1con _t1ckps1___bit equ 5 ; line_number = 65 ; bind _t1ckps0 = _t1con@4 _t1ckps0___byte equ _t1con _t1ckps0___bit equ 4 ; line_number = 66 ; bind _t1oscen = _t1con@3 _t1oscen___byte equ _t1con _t1oscen___bit equ 3 ; line_number = 67 ; bind _t1sync = _t1con@2 _t1sync___byte equ _t1con _t1sync___bit equ 2 ; line_number = 68 ; bind _tmr1cs = _t1con@1 _tmr1cs___byte equ _t1con _tmr1cs___bit equ 1 ; line_number = 69 ; bind _tmr1on = _t1con@0 _tmr1on___byte equ _t1con _tmr1on___bit equ 0 ; line_number = 71 ; register _cmcon = _cmcon equ 25 ; line_number = 72 ; bind _cout = _cmcon@6 _cout___byte equ _cmcon _cout___bit equ 6 ; line_number = 73 ; bind _cinv = _cmcon@4 _cinv___byte equ _cmcon _cinv___bit equ 4 ; line_number = 74 ; bind _cis = _cmcon@3 _cis___byte equ _cmcon _cis___bit equ 3 ; line_number = 75 ; bind _cm2 = _cmcon@2 _cm2___byte equ _cmcon _cm2___bit equ 2 ; line_number = 76 ; bind _cm1 = _cmcon@1 _cm1___byte equ _cmcon _cm1___bit equ 1 ; line_number = 77 ; bind _cm0 = _cmcon@0 _cm0___byte equ _cmcon _cm0___bit equ 0 ; # Data bank 1 (0x80-0xff): ; line_number = 81 ; register _option_reg = _option_reg equ 128 ; line_number = 82 ; bind _rapu = _option_reg@7 _rapu___byte equ _option_reg _rapu___bit equ 7 ; line_number = 83 ; bind _intedg = _option_reg@6 _intedg___byte equ _option_reg _intedg___bit equ 6 ; line_number = 84 ; bind _t0cs = _option_reg@5 _t0cs___byte equ _option_reg _t0cs___bit equ 5 ; line_number = 85 ; bind _t0se = _option_reg@4 _t0se___byte equ _option_reg _t0se___bit equ 4 ; line_number = 86 ; bind _psa = _option_reg@3 _psa___byte equ _option_reg _psa___bit equ 3 ; line_number = 87 ; bind _ps2 = _option_reg@2 _ps2___byte equ _option_reg _ps2___bit equ 2 ; line_number = 88 ; bind _ps1 = _option_reg@1 _ps1___byte equ _option_reg _ps1___bit equ 1 ; line_number = 89 ; bind _ps0 = _option_reg@0 _ps0___byte equ _option_reg _ps0___bit equ 0 ; line_number = 91 ; register _trisa = _trisa equ 133 ; line_number = 92 ; bind _trisa5 = _trisa@5 _trisa5___byte equ _trisa _trisa5___bit equ 5 ; line_number = 93 ; bind _trisa4 = _trisa@4 _trisa4___byte equ _trisa _trisa4___bit equ 4 ; line_number = 94 ; bind _trisa3 = _trisa@3 _trisa3___byte equ _trisa _trisa3___bit equ 3 ; line_number = 95 ; bind _trisa2 = _trisa@2 _trisa2___byte equ _trisa _trisa2___bit equ 2 ; line_number = 96 ; bind _trisa1 = _trisa@1 _trisa1___byte equ _trisa _trisa1___bit equ 1 ; line_number = 97 ; bind _trisa0 = _trisa@0 _trisa0___byte equ _trisa _trisa0___bit equ 0 ; line_number = 99 ; register _trisc = _trisc equ 135 ; line_number = 100 ; bind _trisc5 = _trisc@5 _trisc5___byte equ _trisc _trisc5___bit equ 5 ; line_number = 101 ; bind _trisc4 = _trisc@4 _trisc4___byte equ _trisc _trisc4___bit equ 4 ; line_number = 102 ; bind _trisc3 = _trisc@3 _trisc3___byte equ _trisc _trisc3___bit equ 3 ; line_number = 103 ; bind _trisc2 = _trisc@2 _trisc2___byte equ _trisc _trisc2___bit equ 2 ; line_number = 104 ; bind _trisc1 = _trisc@1 _trisc1___byte equ _trisc _trisc1___bit equ 1 ; line_number = 105 ; bind _trisc0 = _trisc@0 _trisc0___byte equ _trisc _trisc0___bit equ 0 ; line_number = 107 ; register _pie1 = _pie1 equ 140 ; line_number = 108 ; bind _eeie = _pie1@7 _eeie___byte equ _pie1 _eeie___bit equ 7 ; line_number = 109 ; bind _adie = _pie1@6 _adie___byte equ _pie1 _adie___bit equ 6 ; line_number = 110 ; bind _cmie = _pie1@3 _cmie___byte equ _pie1 _cmie___bit equ 3 ; line_number = 111 ; bind _tmr1ie = _pie1@0 _tmr1ie___byte equ _pie1 _tmr1ie___bit equ 0 ; line_number = 113 ; register _pcon = _pcon equ 142 ; line_number = 114 ; bind _por = _pcon@1 _por___byte equ _pcon _por___bit equ 1 ; line_number = 115 ; bind _bor = _pcon@0 _bor___byte equ _pcon _bor___bit equ 0 ; line_number = 117 ; register _osccal = _osccal equ 144 ; line_number = 118 ; bind _cal5 = _osccal@7 _cal5___byte equ _osccal _cal5___bit equ 7 ; line_number = 119 ; bind _cal4 = _osccal@6 _cal4___byte equ _osccal _cal4___bit equ 6 ; line_number = 120 ; bind _cal3 = _osccal@5 _cal3___byte equ _osccal _cal3___bit equ 5 ; line_number = 121 ; bind _cal2 = _osccal@4 _cal2___byte equ _osccal _cal2___bit equ 4 ; line_number = 122 ; bind _cal1 = _osccal@3 _cal1___byte equ _osccal _cal1___bit equ 3 ; line_number = 123 ; bind _cal0 = _osccal@2 _cal0___byte equ _osccal _cal0___bit equ 2 ; line_number = 124 ; constant _osccal_lsb = 4 _osccal_lsb equ 4 ; line_number = 126 ; register _wpua = _wpua equ 149 ; line_number = 127 ; bind _wpua5 = _wpua@5 _wpua5___byte equ _wpua _wpua5___bit equ 5 ; line_number = 128 ; bind _wpua4 = _wpua@4 _wpua4___byte equ _wpua _wpua4___bit equ 4 ; line_number = 129 ; bind _wpua2 = _wpua@2 _wpua2___byte equ _wpua _wpua2___bit equ 2 ; line_number = 130 ; bind _wpua1 = _wpua@1 _wpua1___byte equ _wpua _wpua1___bit equ 1 ; line_number = 131 ; bind _wpua0 = _wpua@0 _wpua0___byte equ _wpua _wpua0___bit equ 0 ; line_number = 133 ; register _ioca = _ioca equ 150 ; line_number = 134 ; bind _ioca5 = _ioca@5 _ioca5___byte equ _ioca _ioca5___bit equ 5 ; line_number = 135 ; bind _ioca4 = _ioca@4 _ioca4___byte equ _ioca _ioca4___bit equ 4 ; line_number = 136 ; bind _ioca3 = _ioca@3 _ioca3___byte equ _ioca _ioca3___bit equ 3 ; line_number = 137 ; bind _ioca2 = _ioca@2 _ioca2___byte equ _ioca _ioca2___bit equ 2 ; line_number = 138 ; bind _ioca1 = _ioca@1 _ioca1___byte equ _ioca _ioca1___bit equ 1 ; line_number = 139 ; bind _ioca0 = _ioca@0 _ioca0___byte equ _ioca _ioca0___bit equ 0 ; line_number = 141 ; register _vrcon = _vrcon equ 153 ; line_number = 142 ; bind _vren = _vrcon@7 _vren___byte equ _vrcon _vren___bit equ 7 ; line_number = 143 ; bind _vrr = _vrcon@5 _vrr___byte equ _vrcon _vrr___bit equ 5 ; line_number = 144 ; bind _vr3 = _vrcon@3 _vr3___byte equ _vrcon _vr3___bit equ 3 ; line_number = 145 ; bind _vr2 = _vrcon@2 _vr2___byte equ _vrcon _vr2___bit equ 2 ; line_number = 146 ; bind _vr1 = _vrcon@1 _vr1___byte equ _vrcon _vr1___bit equ 1 ; line_number = 147 ; bind _vr0 = _vrcon@0 _vr0___byte equ _vrcon _vr0___bit equ 0 ; line_number = 149 ; register _eedata = _eedata equ 154 ; line_number = 151 ; register _eeadr = _eeadr equ 155 ; line_number = 153 ; register _eecon1 = _eecon1 equ 156 ; line_number = 154 ; bind _wrerr = _eecon1@3 _wrerr___byte equ _eecon1 _wrerr___bit equ 3 ; line_number = 155 ; bind _wren = _eecon1@2 _wren___byte equ _eecon1 _wren___bit equ 2 ; line_number = 156 ; bind _wr = _eecon1@1 _wr___byte equ _eecon1 _wr___bit equ 1 ; line_number = 157 ; bind _rd = _eecon1@0 _rd___byte equ _eecon1 _rd___bit equ 0 ; line_number = 159 ; register _eecon2 = _eecon2 equ 157 ; buffer = '_pic16f676' ; line_number = 134 ; library _pic16f630_676 exited ; # The only difference between the PIC16F676 and the PIC16F630 is that ; # the 'F676 has 8 channels of A/D and the 'F630 does not. ; line_number = 139 ; register _adresh = _adresh equ 30 ; # The {_adif} flag is only avaiable for the PIC16F676: ; line_number = 142 ; bind _adif = _pir1@6 _adif___byte equ _pir1 _adif___bit equ 6 ; line_number = 144 ; register _adcon0 = _adcon0 equ 31 ; line_number = 145 ; bind _adfm = _adcon0@7 _adfm___byte equ _adcon0 _adfm___bit equ 7 ; line_number = 146 ; bind _vcfg = _adcon0@5 _vcfg___byte equ _adcon0 _vcfg___bit equ 5 ; line_number = 147 ; bind _chs2 = _adcon0@4 _chs2___byte equ _adcon0 _chs2___bit equ 4 ; line_number = 148 ; bind _chs1 = _adcon0@3 _chs1___byte equ _adcon0 _chs1___bit equ 3 ; line_number = 149 ; bind _chs0 = _adcon0@2 _chs0___byte equ _adcon0 _chs0___bit equ 2 ; line_number = 150 ; bind _go = _adcon0@1 _go___byte equ _adcon0 _go___bit equ 1 ; line_number = 151 ; bind _adon = _adcon0@0 _adon___byte equ _adcon0 _adon___bit equ 0 ; line_number = 153 ; register _ansel = _ansel equ 145 ; line_number = 154 ; bind _ans7 = _ansel@7 _ans7___byte equ _ansel _ans7___bit equ 7 ; line_number = 155 ; bind _ans6 = _ansel@6 _ans6___byte equ _ansel _ans6___bit equ 6 ; line_number = 156 ; bind _ans5 = _ansel@5 _ans5___byte equ _ansel _ans5___bit equ 5 ; line_number = 157 ; bind _ans4 = _ansel@4 _ans4___byte equ _ansel _ans4___bit equ 4 ; line_number = 158 ; bind _ans3 = _ansel@3 _ans3___byte equ _ansel _ans3___bit equ 3 ; line_number = 159 ; bind _ans2 = _ansel@2 _ans2___byte equ _ansel _ans2___bit equ 2 ; line_number = 160 ; bind _ans1 = _ansel@1 _ans1___byte equ _ansel _ans1___bit equ 1 ; line_number = 161 ; bind _ans0 = _ansel@0 _ans0___byte equ _ansel _ans0___bit equ 0 ; line_number = 163 ; register _adresl = _adresl equ 158 ; line_number = 165 ; register _adcon1 = _adcon1 equ 159 ; line_number = 166 ; bind _adcs2 = _adcon1@6 _adcs2___byte equ _adcon1 _adcs2___bit equ 6 ; line_number = 167 ; bind _adcs1 = _adcon1@5 _adcs1___byte equ _adcon1 _adcs1___bit equ 5 ; line_number = 168 ; bind _adcs0 = _adcon1@4 _adcs0___byte equ _adcon1 _adcs0___bit equ 4 ; buffer = 'micro_step' ; line_number = 6 ; library _pic16f676 exited ; line_number = 8 ; package pdip ; line_number = 9 ; pin 1 = power_supply ; line_number = 10 ; pin 2 = clkin ; line_number = 11 ; pin 3 = an3, name=coil0_in coil0_in___byte equ _porta coil0_in___bit equ 4 ; line_number = 12 ; pin 4 = mclr ; line_number = 13 ; pin 5 = rc5_out, name=coil0a, mask=coil0a_mask coil0a___byte equ _portc coil0a___bit equ 5 coil0a_mask equ 32 ; line_number = 14 ; pin 6 = rc4_out, name=coil0b, mask=coil0b_mask coil0b___byte equ _portc coil0b___bit equ 4 coil0b_mask equ 16 ; line_number = 15 ; pin 7 = rc3_out, name=coil1a, mask=coil1a_mask coil1a___byte equ _portc coil1a___bit equ 3 coil1a_mask equ 8 ; line_number = 16 ; pin 8 = rc2_out, name=coil1b, mask=coil1b_mask coil1b___byte equ _portc coil1b___bit equ 2 coil1b_mask equ 4 ; line_number = 17 ; pin 9 = rc1_in, name=step step___byte equ _portc step___bit equ 1 ; line_number = 18 ; pin 10 = rc0_in, name=dir dir___byte equ _portc dir___bit equ 0 ; line_number = 19 ; pin 11 = ra2_in, name=mode mode___byte equ _porta mode___bit equ 2 ; #pin 12 = vref ; line_number = 21 ; pin 12 = ra1_in ; line_number = 22 ; pin 13 = an0, name=coil1_in coil1_in___byte equ _porta coil1_in___bit equ 0 ; line_number = 23 ; pin 14 = ground ; line_number = 27 ; constant microsecond = 5 microsecond equ 5 ; # Current sense resistor is .50 Ohms. ; # Voltage across resistor is I * R = I * (1/2) ; # A/D measures voltage between 0 an 5 volts between 0 and 255. ; # Thus, the A/D result is A = (255/5) * I * R. ; # Converting I into milliamps: A = (255 / 5) * I/1000 * (1/2) ; # Reworking: A = (I * 255) / (5 * 1000 * 2) ; # More rework: A = (I * 255) / 10000 ; # More Rework: A = (I * 51) / 2000 ; line_number = 38 ; constant coil0_current = 1000 coil0_current equ 1000 ; line_number = 39 ; constant coil0_a2d = (coil0_current * 51) / 2000 coil0_a2d equ 25 ; line_number = 40 ; constant coil1_current = 1000 coil1_current equ 1000 ; line_number = 41 ; constant coil1_a2d = (coil1_current * 51) / 2000 coil1_a2d equ 25 ; # A/D acquistion time is: ; # ; # Tacq = Tamp + Tc + Tcoff ; # ; # where ; # ; # Tamp = 2uS ; # Tc = Chold x (Ric + Rss + Rs) x In(1/2047) ; # Tcoff = (T - 25) x .005 (T measured in degrees Centigrade) ; # ; # For T = 50, Tcoff = 1.25uS ; # Worst case, Ric = 1K, Rss=7K, Rs=10K, Chold=120pf ; # So, Tc ~= 16.47usec. ; # ; # Finally, Tacp = 2 + 16.47 + 1.25 = 19.72uS, call it 20uS. ; line_number = 59 ; origin 0 org 0 ; line_number = 61 ; procedure main main: ; Need to calibrate the oscillator call 1023 bsf __rp0___byte, __rp0___bit movwf _osccal ; Initialize some registers movlw 1 bcf __rp0___byte, __rp0___bit movwf _adcon0 movlw 9 bsf __rp0___byte, __rp0___bit movwf _ansel movlw 23 movwf _trisa movlw 3 movwf _trisc ; arguments_none ; line_number = 63 ; returns_nothing ; line_number = 65 ; local index byte main__index equ shared___globals ; line_number = 66 ; local previous bit main__previous___byte equ shared___globals+63 main__previous___bit equ 0 ; line_number = 67 ; local pulse byte main__pulse equ shared___globals+1 ; line_number = 68 ; local coil0_mask byte main__coil0_mask equ shared___globals+2 ; line_number = 69 ; local coil1_mask byte main__coil1_mask equ shared___globals+3 ; line_number = 70 ; local coil0_current byte main__coil0_current equ shared___globals+4 ; line_number = 71 ; local coil0_limit byte main__coil0_limit equ shared___globals+5 ; line_number = 72 ; local coil1_current byte main__coil1_current equ shared___globals+6 ; line_number = 73 ; local coil1_limit byte main__coil1_limit equ shared___globals+7 ; # Set A/D clock source to Tad = 32 x Tocs = 32 x .2uS = 6.4uS. ; # A/D time = 11 x TAd = 11 x 6.4uS = 70.4uS. ; before procedure statements delay=non-uniform, bit states=(data:X0=>X1 code:XX=>XX) ; line_number = 77 ; _adcon1 := 0x20 movlw 32 movwf _adcon1 ; line_number = 79 ; pulse := 0 movlw 0 bcf __rp0___byte, __rp0___bit movwf main__pulse ; line_number = 80 ; coil0_limit:= coil0_a2d movlw 25 movwf main__coil0_limit ; line_number = 81 ; coil0_mask := coil0a_mask movlw 32 movwf main__coil0_mask ; line_number = 82 ; coil1_limit := coil1_a2d movlw 25 movwf main__coil1_limit ; line_number = 83 ; coil1_mask := coil1a_mask movlw 8 movwf main__coil1_mask ; line_number = 84 ; previous := 0 bcf main__previous___byte, main__previous___bit ; line_number = 85 ; index := 0 movlw 0 movwf main__index ; line_number = 86 ; _rc := 0 movlw 0 movwf _rc ; # Set ADCS<2:0> to 010 = Fosc/32: ; line_number = 89 ; _adcs0 := 0 bsf __rp0___byte, __rp0___bit bcf _adcs0___byte, _adcs0___bit ; line_number = 90 ; _adcs1 := 1 bsf _adcs1___byte, _adcs1___bit ; line_number = 91 ; _adcs2 := 0 bcf _adcs2___byte, _adcs2___bit ; # Right justify the 10-bit value into ADR ; line_number = 94 ; _adfm := 1 bcf __rp0___byte, __rp0___bit bsf _adfm___byte, _adfm___bit ; line_number = 95 ; _adon := 1 bsf _adon___byte, _adon___bit ; line_number = 96 ; loop_forever start main__1: ; # Step/Dir process: ; line_number = 98 ; if step start ; =>bit_code_emit@symbol(): sym=step ; CASE: true.size>1 false.size=1; no GOTO's btfss step___byte, step___bit goto main__3 ; line_number = 99 ; if !previous start ; =>bit_code_emit@symbol(): sym=main__previous ; CASE: true.size=0 && false.size>1 btfsc main__previous___byte, main__previous___bit goto main__2 ; # We have a positive step edge: ; line_number = 101 ; if dir start ; =>bit_code_emit@symbol(): sym=dir ; CASE: true_size=1 && false_size=1 btfsc dir___byte, dir___bit ; line_number = 102 ; index := index + 1 incf main__index,f btfss dir___byte, dir___bit ; line_number = 104 ; index := index - 1 decf main__index,f ; <=bit_code_emit@symbol; sym=dir (data:00=>00 code:XX=>XX) ; line_number = 101 ; if dir done main__2: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=main__previous (data:00=>00 code:XX=>XX) ; line_number = 99 ; if !previous done ; line_number = 105 ; previous := 1 bsf main__previous___byte, main__previous___bit goto main__4 main__3: ; line_number = 107 ; previous := 0 bcf main__previous___byte, main__previous___bit main__4: ; <=bit_code_emit@symbol; sym=step (data:00=>00 code:XX=>XX) ; line_number = 98 ; if step done ; # Ripple table: ; line_number = 110 ; if index@1 start main__select__11___byte equ main__index main__select__11___bit equ 1 ; =>bit_code_emit@symbol(): sym=main__select__11 ; CASE: true_code_size > 1 && false_code_size > 1 btfss main__select__11___byte, main__select__11___bit goto main__12 ; line_number = 111 ; if index@0 start main__select__8___byte equ main__index main__select__8___bit equ 0 ; =>bit_code_emit@symbol(): sym=main__select__8 ; CASE: true_code_size > 1 && false_code_size > 1 btfss main__select__8___byte, main__select__8___bit goto main__9 ; # index & 3 = 3: ; line_number = 113 ; coil0_mask := coil0a_mask movlw 32 movwf main__coil0_mask ; line_number = 114 ; coil1_mask := 0 movlw 0 goto main__10 main__9: ; # index & 3 = 2: ; line_number = 117 ; coil0_mask := 0 movlw 0 movwf main__coil0_mask ; line_number = 118 ; coil1_mask := coil1a_mask movlw 8 main__10: goto main__13 main__12: ; line_number = 120 ; if index@0 start main__select__5___byte equ main__index main__select__5___bit equ 0 ; =>bit_code_emit@symbol(): sym=main__select__5 ; CASE: true_code_size > 1 && false_code_size > 1 btfss main__select__5___byte, main__select__5___bit goto main__6 ; # index & 3 = 1: ; line_number = 122 ; coil0_mask := coil0b_mask movlw 16 movwf main__coil0_mask ; line_number = 123 ; coil1_mask := 0 movlw 0 goto main__7 main__6: ; # index & 3 = 0: ; line_number = 126 ; coil0_mask := 0 movlw 0 movwf main__coil0_mask ; line_number = 127 ; coil1_mask := coil1b_mask movlw 4 main__7: main__13: movwf main__coil1_mask ; <=bit_code_emit@symbol; sym=main__select__8 (data:00=>00 code:XX=>XX) ; line_number = 111 ; if index@0 done ; <=bit_code_emit@symbol; sym=main__select__5 (data:00=>00 code:XX=>XX) ; line_number = 120 ; if index@0 done ; <=bit_code_emit@symbol; sym=main__select__11 (data:00=>00 code:XX=>XX) ; line_number = 110 ; if index@1 done ; # The sense resistor for coil 1 is on RA0/AN0, the we set ; # CHS2<2:0> in ADCON0 to 000 (i.e. AN0): ; line_number = 131 ; _chs0 := 0 bcf _chs0___byte, _chs0___bit ; line_number = 132 ; _chs1 := 0 bcf _chs1___byte, _chs1___bit ; line_number = 133 ; _chs2 := 0 bcf _chs2___byte, _chs2___bit ; # Wait 20uS for the sample and hold to settle out: ; # The loop overhead is 3 cycles (=.6uS) and the minimum ; # time through the loop is 4 cycles = (.8us). Total = 1.2uS. ; # 20/1.2 = 16.66. 17 is the minimum: ; line_number = 139 ; loop_exactly 17 start main__14 equ shared___globals+8 movlw 17 movwf main__14 main__15: ; # Step/Dir process: ; line_number = 141 ; if step start ; =>bit_code_emit@symbol(): sym=step ; CASE: true.size>1 false.size=1; no GOTO's btfss step___byte, step___bit goto main__17 ; line_number = 142 ; if !previous start ; =>bit_code_emit@symbol(): sym=main__previous ; CASE: true.size=0 && false.size>1 btfsc main__previous___byte, main__previous___bit goto main__16 ; # We have a positive step edge: ; line_number = 144 ; if dir start ; =>bit_code_emit@symbol(): sym=dir ; CASE: true_size=1 && false_size=1 btfsc dir___byte, dir___bit ; line_number = 145 ; index := index + 1 incf main__index,f btfss dir___byte, dir___bit ; line_number = 147 ; index := index - 1 decf main__index,f ; <=bit_code_emit@symbol; sym=dir (data:00=>00 code:XX=>XX) ; line_number = 144 ; if dir done main__16: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=main__previous (data:00=>00 code:XX=>XX) ; line_number = 142 ; if !previous done ; line_number = 148 ; previous := 1 bsf main__previous___byte, main__previous___bit goto main__18 main__17: ; line_number = 150 ; previous := 0 bcf main__previous___byte, main__previous___bit main__18: ; <=bit_code_emit@symbol; sym=step (data:00=>00 code:XX=>XX) ; line_number = 141 ; if step done ; line_number = 139 ; loop_exactly 17 wrap-up decfsz main__14,f goto main__15 ; line_number = 139 ; loop_exactly 17 done ; # Trigger the A/D conversion: ; line_number = 153 ; _go := 1 bsf _go___byte, _go___bit ; line_number = 154 ; while _go start main__19: ; =>bit_code_emit@symbol(): sym=_go ; CASE: true_code.size = 0 && false_code.size > 1 btfss _go___byte, _go___bit goto main__23 ; # Step/Dir process: ; line_number = 156 ; if step start ; =>bit_code_emit@symbol(): sym=step ; CASE: true.size>1 false.size=1; no GOTO's btfss step___byte, step___bit goto main__21 ; line_number = 157 ; if !previous start ; =>bit_code_emit@symbol(): sym=main__previous ; CASE: true.size=0 && false.size>1 btfsc main__previous___byte, main__previous___bit goto main__20 ; # We have a positive step edge: ; line_number = 159 ; if dir start ; =>bit_code_emit@symbol(): sym=dir ; CASE: true_size=1 && false_size=1 btfsc dir___byte, dir___bit ; line_number = 160 ; index := index + 1 incf main__index,f btfss dir___byte, dir___bit ; line_number = 162 ; index := index - 1 decf main__index,f ; <=bit_code_emit@symbol; sym=dir (data:00=>00 code:XX=>XX) ; line_number = 159 ; if dir done main__20: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=main__previous (data:00=>00 code:XX=>XX) ; line_number = 157 ; if !previous done ; line_number = 163 ; previous := 1 bsf main__previous___byte, main__previous___bit goto main__22 main__21: ; line_number = 165 ; previous := 0 bcf main__previous___byte, main__previous___bit main__22: ; <=bit_code_emit@symbol; sym=step (data:00=>00 code:XX=>XX) ; line_number = 156 ; if step done goto main__19 ; Recombine size1 = 0 || size2 = 0 main__23: ; <=bit_code_emit@symbol; sym=_go (data:00=>00 code:XX=>XX) ; line_number = 154 ; while _go done ; # Read out the A/D value: ; line_number = 168 ; coil1_current := 255 movlw 255 movwf main__coil1_current ; line_number = 169 ; if _adresh = 0 start ; Left minus Right movf _adresh,w ; =>bit_code_emit@symbol(): sym=__z bsf __rp0___byte, __rp0___bit ; CASE: true_code.size = 0 && false_code.size > 1 btfss __z___byte, __z___bit goto main__24 ; line_number = 170 ; coil1_current := _adresl movf _adresl,w bcf __rp0___byte, __rp0___bit movwf main__coil1_current ; Recombine size1 = 0 || size2 = 0 main__24: ; <=bit_code_emit@symbol; sym=__z (data:00=>0? code:XX=>XX) ; line_number = 169 ; if _adresh = 0 done ; # Process the current values: ; line_number = 173 ; pulse := 0 movlw 0 bcf __rp0___byte, __rp0___bit movwf main__pulse ; line_number = 174 ; if coil0_current < coil0_limit start movf main__coil0_limit,w subwf main__coil0_current,w ; =>bit_code_emit@symbol(): sym=__c ; CASE: true.size=0 && false.size>1 btfsc __c___byte, __c___bit goto main__25 ; line_number = 175 ; pulse := coil0_mask movf main__coil0_mask,w movwf main__pulse main__25: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=__c (data:00=>00 code:XX=>XX) ; line_number = 174 ; if coil0_current < coil0_limit done ; line_number = 176 ; if coil1_current < coil1_limit start movf main__coil1_limit,w subwf main__coil1_current,w ; =>bit_code_emit@symbol(): sym=__c ; CASE: true.size=0 && false.size>1 btfsc __c___byte, __c___bit goto main__26 ; line_number = 177 ; pulse := pulse | coil1_mask movf main__coil1_mask,w iorwf main__pulse,f main__26: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=__c (data:00=>00 code:XX=>XX) ; line_number = 176 ; if coil1_current < coil1_limit done ; line_number = 178 ; _rc := pulse movf main__pulse,w movwf _rc ; # The sense resistor for coil 0 is on RA4/AN3, the we set ; # CHS2<2:0> in ADCON0 to 011 (i.e. AN3): ; line_number = 182 ; _chs0 := 1 bsf _chs0___byte, _chs0___bit ; line_number = 183 ; _chs1 := 1 bsf _chs1___byte, _chs1___bit ; line_number = 184 ; _chs2 := 0 bcf _chs2___byte, _chs2___bit ; # Wait 20uS for the sample and hold to settle out: ; line_number = 187 ; loop_exactly 17 start main__27 equ shared___globals+8 movlw 17 movwf main__27 main__28: ; line_number = 188 ; if step start ; =>bit_code_emit@symbol(): sym=step ; CASE: true.size>1 false.size=1; no GOTO's btfss step___byte, step___bit goto main__30 ; line_number = 189 ; if !previous start ; =>bit_code_emit@symbol(): sym=main__previous ; CASE: true.size=0 && false.size>1 btfsc main__previous___byte, main__previous___bit goto main__29 ; # We have a positive step edge: ; line_number = 191 ; if dir start ; =>bit_code_emit@symbol(): sym=dir ; CASE: true_size=1 && false_size=1 btfsc dir___byte, dir___bit ; line_number = 192 ; index := index + 1 incf main__index,f btfss dir___byte, dir___bit ; line_number = 194 ; index := index - 1 decf main__index,f ; <=bit_code_emit@symbol; sym=dir (data:00=>00 code:XX=>XX) ; line_number = 191 ; if dir done main__29: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=main__previous (data:00=>00 code:XX=>XX) ; line_number = 189 ; if !previous done ; line_number = 195 ; previous := 1 bsf main__previous___byte, main__previous___bit goto main__31 main__30: ; line_number = 197 ; previous := 0 bcf main__previous___byte, main__previous___bit main__31: ; <=bit_code_emit@symbol; sym=step (data:00=>00 code:XX=>XX) ; line_number = 188 ; if step done ; line_number = 187 ; loop_exactly 17 wrap-up decfsz main__27,f goto main__28 ; line_number = 187 ; loop_exactly 17 done ; # Trigger the AN3 A/D conversion: ; line_number = 200 ; _go := 1 bsf _go___byte, _go___bit ; line_number = 201 ; while _go start main__32: ; =>bit_code_emit@symbol(): sym=_go ; CASE: true_code.size = 0 && false_code.size > 1 btfss _go___byte, _go___bit goto main__36 ; line_number = 202 ; if step start ; =>bit_code_emit@symbol(): sym=step ; CASE: true.size>1 false.size=1; no GOTO's btfss step___byte, step___bit goto main__34 ; line_number = 203 ; if !previous start ; =>bit_code_emit@symbol(): sym=main__previous ; CASE: true.size=0 && false.size>1 btfsc main__previous___byte, main__previous___bit goto main__33 ; # We have a positive step edge: ; line_number = 205 ; if dir start ; =>bit_code_emit@symbol(): sym=dir ; CASE: true_size=1 && false_size=1 btfsc dir___byte, dir___bit ; line_number = 206 ; index := index + 1 incf main__index,f btfss dir___byte, dir___bit ; line_number = 208 ; index := index - 1 decf main__index,f ; <=bit_code_emit@symbol; sym=dir (data:00=>00 code:XX=>XX) ; line_number = 205 ; if dir done main__33: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=main__previous (data:00=>00 code:XX=>XX) ; line_number = 203 ; if !previous done ; line_number = 209 ; previous := 1 bsf main__previous___byte, main__previous___bit goto main__35 main__34: ; line_number = 211 ; previous := 0 bcf main__previous___byte, main__previous___bit main__35: ; <=bit_code_emit@symbol; sym=step (data:00=>00 code:XX=>XX) ; line_number = 202 ; if step done goto main__32 ; Recombine size1 = 0 || size2 = 0 main__36: ; <=bit_code_emit@symbol; sym=_go (data:00=>00 code:XX=>XX) ; line_number = 201 ; while _go done ; # Read out the A/D value for AN3: ; line_number = 214 ; coil0_current := 255 movlw 255 movwf main__coil0_current ; line_number = 215 ; if _adresh = 0 start ; Left minus Right movf _adresh,w ; =>bit_code_emit@symbol(): sym=__z bsf __rp0___byte, __rp0___bit ; CASE: true_code.size = 0 && false_code.size > 1 btfss __z___byte, __z___bit goto main__37 ; line_number = 216 ; coil0_current := _adresl movf _adresl,w bcf __rp0___byte, __rp0___bit movwf main__coil0_current ; Recombine size1 = 0 || size2 = 0 main__37: ; <=bit_code_emit@symbol; sym=__z (data:00=>0? code:XX=>XX) ; line_number = 215 ; if _adresh = 0 done ; # Process the current values: ; line_number = 219 ; pulse := 0 movlw 0 bcf __rp0___byte, __rp0___bit movwf main__pulse ; line_number = 220 ; if coil0_current < coil0_limit start movf main__coil0_limit,w subwf main__coil0_current,w ; =>bit_code_emit@symbol(): sym=__c ; CASE: true.size=0 && false.size>1 btfsc __c___byte, __c___bit goto main__38 ; line_number = 221 ; pulse := coil0_mask movf main__coil0_mask,w movwf main__pulse main__38: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=__c (data:00=>00 code:XX=>XX) ; line_number = 220 ; if coil0_current < coil0_limit done ; line_number = 222 ; if coil1_current < coil1_limit start movf main__coil1_limit,w subwf main__coil1_current,w ; =>bit_code_emit@symbol(): sym=__c ; CASE: true.size=0 && false.size>1 btfsc __c___byte, __c___bit goto main__39 ; line_number = 223 ; pulse := pulse | coil1_mask movf main__coil1_mask,w iorwf main__pulse,f ; line_number = 224 ; _rc := pulse movf main__pulse,w movwf _rc main__39: ; Recombine size1 = 0 || size2 = 0 ; <=bit_code_emit@symbol; sym=__c (data:00=>00 code:XX=>XX) ; line_number = 222 ; if coil1_current < coil1_limit done ; line_number = 96 ; loop_forever wrap-up goto main__1 ; line_number = 96 ; loop_forever done ; delay after procedure statements=non-uniform ; # # Convert index into full step coil pulse masks: ; # if index@1 ; # if index@0 ; # # index & 3 = 3: ; # coil0_mask := coil0a_mask ; # coil1_mask := coil1a_mask ; # else ; # # index & 3 = 2: ; # coil0_mask := coil0a_mask ; # coil1_mask := coil1b_mask ; # else ; # if index@0 ; # # index & 3 = 1: ; # coil0_mask := coil0b_mask ; # coil1_mask := coil1b_mask ; # else ; # # index & 3 = 0: ; # coil0_mask := coil0b_mask ; # coil1_mask := coil1a_mask ; Configuration bits ; address = 0x2007, fill = 0x0 ; bg = bg11 (0x3000) ; cpd = off (0x100) ; cp = off (0x80) ; boden = off (0x0) ; mclre = on (0x20) ; pwrte = off (0x10) ; wdte = off (0x0) ; fosc = hs (0x2) ; 12722 = 0x31b2 __config 12722 ; Define start addresses for data regions ; Region="shared___globals" Address=32" Size=64 Bytes=9 Bits=1 Available=54 ; Region="shared___globals" Address=32" Size=64 Bytes=9 Bits=1 Available=54 ; Region="shared___globals" Address=32" Size=64 Bytes=9 Bits=1 Available=54 end