1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0120 global__variables__bank2 equ 288 5 01f0 global__variables__bank3 equ 496 6 003d global__bit__variables__bank0 equ 61 7 00a0 global__bit__variables__bank1 equ 160 8 0120 global__bit__variables__bank2 equ 288 9 01f0 global__bit__variables__bank3 equ 496 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 0003 rp0___byte equ 3 17 0005 rp0___bit equ 5 18 0003 rp1___byte equ 3 19 0006 rp1___bit equ 6 20 0003 irp___byte equ 3 21 0007 irp___bit equ 7 22 0085 trisa___register equ 0x85 23 0086 trisb___register equ 0x86 24 0004 fsr___register equ 4 25 000a pclath___register equ 10 26 org 0 27 start: 28 000 0000 nop 29 001 0000 nop 30 002 0000 nop 31 003 2805 goto skip___interrupt 32 interrupt___vector: 33 004 0009 retfie 34 skip___interrupt: 35 ; Initialize A/D system to allow digital I/O 36 005 3003 movlw 3 37 006 009f movwf 31 38 ; Initialize TRIS registers 39 007 3083 movlw 131 40 ; Switch from register bank 0 to register bank 1 (which contains trisa___register) 41 008 1683 bsf rp0___byte,rp0___bit 42 ; Register bank is now 1 43 009 0085 movwf trisa___register 44 00a 300f movlw 15 45 00b 0086 movwf trisb___register 46 00c 018a clrf pclath___register 47 ; Switch from register bank 1 to register bank 0 48 00d 1283 bcf rp0___byte,rp0___bit 49 ; Register bank is now 0 50 00e 2816 goto main 51 ; comment ############################################################################# 52 ; comment {} 53 ; comment {Copyright < c > 2002 by Wayne C . Gramlich .} 54 ; comment {All rights reserved .} 55 ; comment {} 56 ; comment {Permission to use , copy , modify , distribute , and sell this software} 57 ; comment {for any purpose is hereby granted without fee provided that the above} 58 ; comment {copyright notice and this permission are retained . The author makes} 59 ; comment {no representations about the suitability of this software for any purpose .} 60 ; comment {It is provided { as is } without express or implied warranty .} 61 ; comment {} 62 ; comment {This is control microcode for Wayne ' s motion CNC board at :} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / cnc / motion / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment {Some pin assignments :} 69 ; comment {} 70 ; comment {No Name Kind Description} 71 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 72 ; comment {1 RA2 / AN2 / VREF Digital Out DAC Chip Select} 73 ; comment {2 RA3 / AN3 / CMP1 Digital Out Home Out *} 74 ; comment {3 RA4 / TOCKI / CMP2 Digital In Home} 75 ; comment {4 RA5 / MCLR * / THV Digital In Home In *} 76 ; comment {5 VSS Ground Ground} 77 ; comment {6 RB0 / INT Digital In Step} 78 ; comment {7 RB1 / RX / DT Digital In Receive} 79 ; comment {8 RB2 / TX / CK Digital Out Transmit} 80 ; comment {9 RB3 / CCP1 Digital In Direction} 81 ; comment {10 RB4 / PGM Digital Out Phase 1} 82 ; comment {11 RB5 Digital Out Phase 2} 83 ; comment {12 RB6 / T1OSO / TICK1 Digital Out Phase 0} 84 ; comment {13 RB7 / T1OSI Digital Out Serial Clock} 85 ; comment {14 VDD Power + 5 Volts} 86 ; comment {15 RA6 / OSC2 / CLKOUT Digital Out Serial Data} 87 ; comment {16 RA7 / OSC1 / CLKIN Digital In Oscillator} 88 ; comment {17 RA0 / AN0 Digital In Encoder 0} 89 ; comment {18 RA1 / AN1 Digital In Encoder 1} 90 ; comment {} 91 ; comment ############################################################################# 92 ; processor pic16f628 cp = off cpd = off lvp = off bowden = off mclre = off pwrte = off wdte = off fosc = ec 93 ; 16139=0x3f0b 8199=0x2007 94 __config 16139 95 2007 configuration___address equ 8199 96 ; constant clock_rate 20000000 97 1312d00 clock_rate equ 20000000 98 ; comment {Some character constants :} 99 ; constant sp 32 100 0020 sp equ 32 101 ; constant cr 13 102 000d cr equ 13 103 ; constant lf 10 104 000a lf equ 10 105 ; comment {Some register definitions :} 106 0001 tmr0 equ 1 107 0003 status equ 3 108 ; bind c status @ 0 109 0003 c equ status+0 110 0003 c__byte equ status+0 111 0000 c__bit equ 0 112 ; bind z status @ 2 113 0003 z equ status+0 114 0003 z__byte equ status+0 115 0002 z__bit equ 2 116 000b intcon equ 11 117 ; bind gie intcon @ 7 118 000b gie equ intcon+0 119 000b gie__byte equ intcon+0 120 0007 gie__bit equ 7 121 ; bind t0ie intcon @ 5 122 000b t0ie equ intcon+0 123 000b t0ie__byte equ intcon+0 124 0005 t0ie__bit equ 5 125 ; bind inte intcon @ 4 126 000b inte equ intcon+0 127 000b inte__byte equ intcon+0 128 0004 inte__bit equ 4 129 ; bind rbie intcon @ 3 130 000b rbie equ intcon+0 131 000b rbie__byte equ intcon+0 132 0003 rbie__bit equ 3 133 ; bind t0if intcon @ 2 134 000b t0if equ intcon+0 135 000b t0if__byte equ intcon+0 136 0002 t0if__bit equ 2 137 ; bind intf intcon @ 1 138 000b intf equ intcon+0 139 000b intf__byte equ intcon+0 140 0001 intf__bit equ 1 141 ; bind rbif intcon @ 0 142 000b rbif equ intcon+0 143 000b rbif__byte equ intcon+0 144 0000 rbif__bit equ 0 145 000c pir1 equ 12 146 ; bind eeif pir1 @ 7 147 000c eeif equ pir1+0 148 000c eeif__byte equ pir1+0 149 0007 eeif__bit equ 7 150 ; bind cmif pir1 @ 6 151 000c cmif equ pir1+0 152 000c cmif__byte equ pir1+0 153 0006 cmif__bit equ 6 154 ; bind rcif pir1 @ 5 155 000c rcif equ pir1+0 156 000c rcif__byte equ pir1+0 157 0005 rcif__bit equ 5 158 ; bind txif pir1 @ 4 159 000c txif equ pir1+0 160 000c txif__byte equ pir1+0 161 0004 txif__bit equ 4 162 ; bind ccp1if pir1 @ 2 163 000c ccp1if equ pir1+0 164 000c ccp1if__byte equ pir1+0 165 0002 ccp1if__bit equ 2 166 ; bind tmr2if pir1 @ 1 167 000c tmr2if equ pir1+0 168 000c tmr2if__byte equ pir1+0 169 0001 tmr2if__bit equ 1 170 ; bind tmr1if pir1 @ 0 171 000c tmr1if equ pir1+0 172 000c tmr1if__byte equ pir1+0 173 0000 tmr1if__bit equ 0 174 0018 rcsta equ 24 175 ; bind spen rcsta @ 7 176 0018 spen equ rcsta+0 177 0018 spen__byte equ rcsta+0 178 0007 spen__bit equ 7 179 ; bind rx9 rcsta @ 6 180 0018 rx9 equ rcsta+0 181 0018 rx9__byte equ rcsta+0 182 0006 rx9__bit equ 6 183 ; bind sren rcsta @ 5 184 0018 sren equ rcsta+0 185 0018 sren__byte equ rcsta+0 186 0005 sren__bit equ 5 187 ; bind cren rcsta @ 4 188 0018 cren equ rcsta+0 189 0018 cren__byte equ rcsta+0 190 0004 cren__bit equ 4 191 ; bind aden rcsta @ 3 192 0018 aden equ rcsta+0 193 0018 aden__byte equ rcsta+0 194 0003 aden__bit equ 3 195 ; bind ferr rcsta @ 2 196 0018 ferr equ rcsta+0 197 0018 ferr__byte equ rcsta+0 198 0002 ferr__bit equ 2 199 ; bind oerr rcsta @ 1 200 0018 oerr equ rcsta+0 201 0018 oerr__byte equ rcsta+0 202 0001 oerr__bit equ 1 203 ; bind rx9d rcsta @ 0 204 0018 rx9d equ rcsta+0 205 0018 rx9d__byte equ rcsta+0 206 0000 rx9d__bit equ 0 207 0019 txreg equ 25 208 001a rcreg equ 26 209 ; comment {Comparator module control :} 210 001f cmcon equ 31 211 ; bind c2out cmcon @ 7 212 001f c2out equ cmcon+0 213 001f c2out__byte equ cmcon+0 214 0007 c2out__bit equ 7 215 ; bind c1out cmcon @ 6 216 001f c1out equ cmcon+0 217 001f c1out__byte equ cmcon+0 218 0006 c1out__bit equ 6 219 ; bind c2inv cmcon @ 5 220 001f c2inv equ cmcon+0 221 001f c2inv__byte equ cmcon+0 222 0005 c2inv__bit equ 5 223 ; bind c1inv cmcon @ 4 224 001f c1inv equ cmcon+0 225 001f c1inv__byte equ cmcon+0 226 0004 c1inv__bit equ 4 227 ; bind cis cmcon @ 3 228 001f cis equ cmcon+0 229 001f cis__byte equ cmcon+0 230 0003 cis__bit equ 3 231 ; bind cm2 cmcon @ 2 232 001f cm2 equ cmcon+0 233 001f cm2__byte equ cmcon+0 234 0002 cm2__bit equ 2 235 ; bind cm1 cmcon @ 1 236 001f cm1 equ cmcon+0 237 001f cm1__byte equ cmcon+0 238 0001 cm1__bit equ 1 239 ; bind cm0 cmcon @ 0 240 001f cm0 equ cmcon+0 241 001f cm0__byte equ cmcon+0 242 0000 cm0__bit equ 0 243 0081 option equ 129 244 ; bind t0cs option @ 5 245 0081 t0cs equ option+0 246 0081 t0cs__byte equ option+0 247 0005 t0cs__bit equ 5 248 ; bind t0se option @ 4 249 0081 t0se equ option+0 250 0081 t0se__byte equ option+0 251 0004 t0se__bit equ 4 252 ; bind psa option @ 3 253 0081 psa equ option+0 254 0081 psa__byte equ option+0 255 0003 psa__bit equ 3 256 ; bind ps2 option @ 2 257 0081 ps2 equ option+0 258 0081 ps2__byte equ option+0 259 0002 ps2__bit equ 2 260 ; bind ps1 option @ 1 261 0081 ps1 equ option+0 262 0081 ps1__byte equ option+0 263 0001 ps1__bit equ 1 264 ; bind ps0 option @ 0 265 0081 ps0 equ option+0 266 0081 ps0__byte equ option+0 267 0000 ps0__bit equ 0 268 008c pie1 equ 140 269 ; bind eeie pie1 @ 7 270 008c eeie equ pie1+0 271 008c eeie__byte equ pie1+0 272 0007 eeie__bit equ 7 273 ; bind cmie pie1 @ 6 274 008c cmie equ pie1+0 275 008c cmie__byte equ pie1+0 276 0006 cmie__bit equ 6 277 ; bind rcie pie1 @ 5 278 008c rcie equ pie1+0 279 008c rcie__byte equ pie1+0 280 0005 rcie__bit equ 5 281 ; bind txie pie1 @ 4 282 008c txie equ pie1+0 283 008c txie__byte equ pie1+0 284 0004 txie__bit equ 4 285 ; bind ccp1ie pie1 @ 2 286 008c ccp1ie equ pie1+0 287 008c ccp1ie__byte equ pie1+0 288 0002 ccp1ie__bit equ 2 289 ; bind tmr2ie pie1 @ 1 290 008c tmr2ie equ pie1+0 291 008c tmr2ie__byte equ pie1+0 292 0001 tmr2ie__bit equ 1 293 ; bind tmr1ie pie1 @ 0 294 008c tmr1ie equ pie1+0 295 008c tmr1ie__byte equ pie1+0 296 0000 tmr1ie__bit equ 0 297 0098 txsta equ 152 298 ; bind tx9 txsta @ 6 299 0098 tx9 equ txsta+0 300 0098 tx9__byte equ txsta+0 301 0006 tx9__bit equ 6 302 ; bind txen txsta @ 5 303 0098 txen equ txsta+0 304 0098 txen__byte equ txsta+0 305 0005 txen__bit equ 5 306 ; bind sync txsta @ 4 307 0098 sync equ txsta+0 308 0098 sync__byte equ txsta+0 309 0004 sync__bit equ 4 310 ; bind brgh txsta @ 2 311 0098 brgh equ txsta+0 312 0098 brgh__byte equ txsta+0 313 0002 brgh__bit equ 2 314 ; bind trmt txsta @ 1 315 0098 trmt equ txsta+0 316 0098 trmt__byte equ txsta+0 317 0001 trmt__bit equ 1 318 ; bind tx9d txsta @ 0 319 0098 tx9d equ txsta+0 320 0098 tx9d__byte equ txsta+0 321 0000 tx9d__bit equ 0 322 0099 spbrg equ 153 323 ; comment {Some port , bit , and pin definitions :} 324 ; comment {Port A pin assignments :} 325 ; comment {RA0 : Encoder 0} 326 ; comment {RA1 : Encoder 1} 327 ; comment {RA2 : DAC Chip Select} 328 ; comment {RA3 : Home Out} 329 ; comment {RA4 : Home} 330 ; comment {RA5 : Home In} 331 ; comment {RA6 : Serial Data} 332 ; comment {RA7 : Oscillator In} 333 ; constant encoder0_bit 0 334 0000 encoder0_bit equ 0 335 ; constant encoder1_bit 1 336 0001 encoder1_bit equ 1 337 ; constant dac_select_bit 2 338 0002 dac_select_bit equ 2 339 ; constant home_out_bit 3 340 0003 home_out_bit equ 3 341 ; constant home_bit 4 342 0004 home_bit equ 4 343 ; constant home_in_bit 5 344 0005 home_in_bit equ 5 345 ; constant serial_data_bit 6 346 0006 serial_data_bit equ 6 347 ; constant osc_in_bit 7 348 0007 osc_in_bit equ 7 349 0005 porta equ 5 350 0005 encoder0__byte equ 5 351 0000 encoder0__bit equ 0 352 0005 encoder1__byte equ 5 353 0001 encoder1__bit equ 1 354 0005 dac_select__byte equ 5 355 0002 dac_select__bit equ 2 356 0005 home_out_bit__byte equ 5 357 0003 home_out_bit__bit equ 3 358 0005 home_bit__byte equ 5 359 0004 home_bit__bit equ 4 360 0005 home_in__byte equ 5 361 0005 home_in__bit equ 5 362 0005 serial_data__byte equ 5 363 0006 serial_data__bit equ 6 364 0005 osc_in__byte equ 5 365 0007 osc_in__bit equ 7 366 ; comment {Port B pin assignments :} 367 ; comment {RB0 : Step} 368 ; comment {RB1 : Serial Input < RX >} 369 ; comment {RB2 : Serial Output < TX >} 370 ; comment {RB3 : Direction} 371 ; comment {RB4 : Phase 1} 372 ; comment {RB5 : Phase 2} 373 ; comment {RB6 : Phase 0} 374 ; comment {RB7 : Serial Clock} 375 ; constant step_bit 0 376 0000 step_bit equ 0 377 ; constant rx_bit 1 378 0001 rx_bit equ 1 379 ; constant tx_bit 2 380 0002 tx_bit equ 2 381 ; constant direction_bit 3 382 0003 direction_bit equ 3 383 ; constant phase1_bit 4 384 0004 phase1_bit equ 4 385 ; constant phase2_bit 5 386 0005 phase2_bit equ 5 387 ; constant phase0_bit 6 388 0006 phase0_bit equ 6 389 ; constant serial_clock_bit 7 390 0007 serial_clock_bit equ 7 391 0006 portb equ 6 392 0006 step__byte equ 6 393 0000 step__bit equ 0 394 ; comment {When using the USART , both the TX and RX pins must be set to input :} 395 0006 tx_pin__byte equ 6 396 0002 tx_pin__bit equ 2 397 0006 rx_pin__byte equ 6 398 0001 rx_pin__bit equ 1 399 0006 direction__byte equ 6 400 0003 direction__bit equ 3 401 0006 phase1__byte equ 6 402 0004 phase1__bit equ 4 403 0006 phase2__byte equ 6 404 0005 phase2__bit equ 5 405 0006 phase0__byte equ 6 406 0006 phase0__bit equ 6 407 0006 serial_clock__byte equ 6 408 0007 serial_clock__bit equ 7 409 ; string_constants Start 410 string___fetch: 411 00f 0082 movwf pcl___register 412 ; hello_string = 0s'Ctrl' 413 0000 hello_string___string equ 0 414 hello_string: 415 010 0782 addwf pcl___register,f 416 ; Length = 4 417 011 3404 retlw 4 418 ; `Ctrl' 419 012 3443 retlw 67 420 013 3474 retlw 116 421 014 3472 retlw 114 422 015 346c retlw 108 423 ; string__constants End 424 0020 send_in_index equ global__variables__bank0+0 425 0021 send_out_index equ global__variables__bank0+1 426 ; constant send_buffer_size 10 427 000a send_buffer_size equ 10 428 0022 send_buffer equ global__variables__bank0+2 429 430 ; procedure main start 431 main: 432 002c main__variables__base equ global__variables__bank0+12 433 002c main__bytes__base equ main__variables__base+0 434 0032 main__bits__base equ main__variables__base+6 435 0006 main__total__bytes equ 6 436 0031 main__287byte0 equ main__bytes__base+5 437 ; arguments_none 438 002c main__char equ main__bytes__base+0 439 002d main__coil_a equ main__bytes__base+1 440 002e main__coil_b equ main__bytes__base+2 441 002f main__number equ main__bytes__base+3 442 0030 main__phase equ main__bytes__base+4 443 ; Get all interrupts turned off : 444 ; intcon := 0 445 016 018b clrf intcon 446 ; pie1 := 0 447 ; Switch from register bank 0 to register bank 1 (which contains pie1) 448 017 1683 bsf rp0___byte,rp0___bit 449 ; Register bank is now 1 450 018 018c clrf pie1 451 ; pir1 := 0 452 ; Switch from register bank 1 to register bank 0 (which contains pir1) 453 019 1283 bcf rp0___byte,rp0___bit 454 ; Register bank is now 0 455 01a 018c clrf pir1 456 ; Initialize UART : 457 ; Prescaler = low : 458 ; brgh := 0 459 ; Prescaler = high 460 ; brgh := 1 461 ; Switch from register bank 0 to register bank 1 (which contains brgh__byte) 462 01b 1683 bsf rp0___byte,rp0___bit 463 ; Register bank is now 1 464 01c 1518 bsf brgh__byte,brgh__bit 465 ; Baud rate = 2400 baud : 466 ; spbrg := 129 467 ; Baud rate = 115200 baud : 468 ; spbrg := 10 469 01d 300a movlw 10 470 01e 0099 movwf spbrg 471 ; Asynchronous mode : 472 ; sync := 0 473 01f 1218 bcf sync__byte,sync__bit 474 ; 8 - bit mode : 475 ; tx9 := 0 476 020 1318 bcf tx9__byte,tx9__bit 477 ; Serial Port Enable : 478 ; spen := 1 479 ; Switch from register bank 1 to register bank 0 (which contains spen__byte) 480 021 1283 bcf rp0___byte,rp0___bit 481 ; Register bank is now 0 482 022 1798 bsf spen__byte,spen__bit 483 ; Keep interrupts off : 484 ; txie := 0 485 ; Switch from register bank 0 to register bank 1 (which contains txie__byte) 486 023 1683 bsf rp0___byte,rp0___bit 487 ; Register bank is now 1 488 024 120c bcf txie__byte,txie__bit 489 ; Clear out an previous character . 490 ; txif := 0 491 ; Switch from register bank 1 to register bank 0 (which contains txif__byte) 492 025 1283 bcf rp0___byte,rp0___bit 493 ; Register bank is now 0 494 026 120c bcf txif__byte,txif__bit 495 ; Enable the transmitter : 496 ; txen := 1 497 ; Switch from register bank 0 to register bank 1 (which contains txen__byte) 498 027 1683 bsf rp0___byte,rp0___bit 499 ; Register bank is now 1 500 028 1698 bsf txen__byte,txen__bit 501 ; Enable the receiver : 502 ; Keep inerrupts off : 503 ; rcie := 0 504 029 128c bcf rcie__byte,rcie__bit 505 ; Enable continuous reception : 506 ; cren := 1 507 ; Switch from register bank 1 to register bank 0 (which contains cren__byte) 508 02a 1283 bcf rp0___byte,rp0___bit 509 ; Register bank is now 0 510 02b 1618 bsf cren__byte,cren__bit 511 ; Enable single receptions : 512 ; sren := 1 513 02c 1698 bsf sren__byte,sren__bit 514 ; Disable address 515 ; aden := 0 516 02d 1198 bcf aden__byte,aden__bit 517 ; Initialize the comparator module : 518 ; Two independent comparators : 519 ; cmcon := 4 520 ; Initialize the timer module : 521 ; t0cs := 0 522 ; Switch from register bank 0 to register bank 1 (which contains t0cs__byte) 523 02e 1683 bsf rp0___byte,rp0___bit 524 ; Register bank is now 1 525 02f 1281 bcf t0cs__byte,t0cs__bit 526 ; psa := 0 527 030 1181 bcf psa__byte,psa__bit 528 ; ps2 := 1 529 031 1501 bsf ps2__byte,ps2__bit 530 ; ps1 := 1 531 032 1481 bsf ps1__byte,ps1__bit 532 ; ps0 := 1 533 033 1401 bsf ps0__byte,ps0__bit 534 ; Initialize ring buffer : 535 ; send_in_index := 0 536 ; Switch from register bank 1 to register bank 0 (which contains send_in_index) 537 034 1283 bcf rp0___byte,rp0___bit 538 ; Register bank is now 0 539 035 01a0 clrf send_in_index 540 ; send_out_index := 0 541 036 01a1 clrf send_out_index 542 ; A little initialization : 543 ; number := 0 544 037 01af clrf main__number 545 ; phase := 0 546 038 01b0 clrf main__phase 547 ; dac_select := 1 548 039 1505 bsf dac_select__byte,dac_select__bit 549 ; serial_clock := 0 550 03a 1386 bcf serial_clock__byte,serial_clock__bit 551 ; serial_data := 0 552 03b 1305 bcf serial_data__byte,serial_data__bit 553 ; call send_dac {{ 9 , 127 }} 554 03c 3009 movlw 9 555 03d 00b2 movwf send_dac__byte0 556 03e 307f movlw 127 557 03f 00b3 movwf send_dac__byte1 558 040 20a3 call send_dac 559 ; call send_dac {{ 10 , 127 }} 560 041 300a movlw 10 561 042 00b2 movwf send_dac__byte0 562 043 307f movlw 127 563 044 00b3 movwf send_dac__byte1 564 045 20a3 call send_dac 565 ; Main loop 566 ; loop_forever ... start 567 main__273loop__forever: 568 ; See whether we can transmit a character : 569 ; if { send_in_index != send_out_index && txif } start 570 046 0820 movf send_in_index,w 571 047 0221 subwf send_out_index,w 572 ; expression=`send_in_index != send_out_index' exp_delay=2 true_delay=-1 false_delay=2 true_size=13 false_size=1 573 048 1903 btfsc z___byte,z___bit 574 049 2857 goto and275__0false 575 ; expression=`txif' exp_delay=0 true_delay=11 false_delay=0 true_size=11 false_size=0 576 04a 1e0c btfss txif__byte,txif__bit 577 04b 2857 goto label275__1end 578 and275__0true: 579 ; if { send_in_index != send_out_index && txif } body start 580 ; txreg := send_buffer ~~ {{ send_out_index }} 581 04c 3022 movlw LOW send_buffer 582 04d 0721 addwf send_out_index,w 583 04e 0084 movwf fsr___register 584 04f 1383 bcf irp___register,irp___bit 585 050 0800 movf indf___register,w 586 051 0099 movwf txreg 587 ; send_out_index := send_out_index + 1 588 052 0aa1 incf send_out_index,f 589 ; if { send_out_index >= send_buffer_size } start 590 053 300a movlw 10 591 054 0221 subwf send_out_index,w 592 ; expression=`{ send_out_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 593 055 1803 btfsc c___byte,c___bit 594 ; if { send_out_index >= send_buffer_size } body start 595 ; send_out_index := 0 596 056 01a1 clrf send_out_index 597 ; if { send_out_index >= send_buffer_size } body end 598 ; if exp=` send_out_index >= send_buffer_size ' false skip delay=4 599 ; Other expression=`{ send_out_index >= send_buffer_size }' delay=4 600 ; if { send_out_index >= send_buffer_size } end 601 ; if { send_in_index != send_out_index && txif } body end 602 label275__1end: 603 ; if exp=`txif' empty false 604 ; Other expression=`txif' delay=-1 605 ; if exp=`send_in_index != send_out_index' false goto 606 ; Other expression=`send_in_index != send_out_index' delay=-1 607 and275__0false: 608 and275__0end: 609 ; if { send_in_index != send_out_index && txif } end 610 ; See whether we ' ve got a character : 611 ; if { rcif } start 612 ; expression=`{ rcif }' exp_delay=0 true_delay=-1 false_delay=0 true_size=61 false_size=0 613 057 1e8c btfss rcif__byte,rcif__bit 614 058 2896 goto label284__0end 615 ; if { rcif } body start 616 ; char := rcreg 617 059 081a movf rcreg,w 618 05a 00ac movwf main__char 619 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } start 620 05b 3030 movlw 48 621 05c 022c subwf main__char,w 622 ; expression=`0c'0' <= char' exp_delay=2 true_delay=-1 false_delay=1 true_size=55 false_size=1 623 05d 1c03 btfss c___byte,c___bit 624 05e 286c goto and286__0false 625 05f 3038 movlw 56 626 060 022c subwf main__char,w 627 ; expression=`char <= 0c'7'' exp_delay=2 true_delay=8 false_delay=-1 true_size=8 false_size=42 628 061 1803 btfsc c___byte,c___bit 629 062 286c goto label286__1false 630 label286__1true: 631 and286__0true: 632 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body start 633 ; number := {{ number << 3 }} + char - 0c'0' 634 063 0d2f rlf main__number,w 635 064 00b1 movwf main__287byte0 636 065 0db1 rlf main__287byte0,f 637 066 0d31 rlf main__287byte0,w 638 067 39f8 andlw 248 639 068 072c addwf main__char,w 640 069 3ed0 addlw 208 641 06a 00af movwf main__number 642 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body end 643 06b 2896 goto label286__1end 644 label286__1false: 645 and286__0false: 646 ; else body start 647 ; if { char = 0c'Z' } start 648 06c 305a movlw 90 649 06d 022c subwf main__char,w 650 ; expression=`{ char = 0c'Z' }' exp_delay=2 true_delay=2 false_delay=-1 true_size=4 false_size=32 651 06e 1903 btfsc z___byte,z___bit 652 06f 2891 goto label289__0true 653 label289__0false: 654 070 307a movlw 122 655 071 022c subwf main__char,w 656 ; expression=`{ char = 0c'z' }' exp_delay=2 true_delay=2 false_delay=-1 true_size=4 false_size=23 657 072 1903 btfsc z___byte,z___bit 658 073 288c goto label292__0true 659 label292__0false: 660 074 3061 movlw 97 661 075 022c subwf main__char,w 662 ; expression=`{ char = 0c'a' }' exp_delay=2 true_delay=5 false_delay=-1 true_size=7 false_size=11 663 076 1903 btfsc z___byte,z___bit 664 077 2884 goto label295__0true 665 label295__0false: 666 078 3062 movlw 98 667 079 022c subwf main__char,w 668 ; expression=`{ char = 0c'b' }' exp_delay=2 true_delay=5 false_delay=0 true_size=7 false_size=0 669 07a 1d03 btfss z___byte,z___bit 670 07b 2883 goto label298__0end 671 ; else_if { char = 0c'b' } body start 672 ; coil_b := number 673 07c 082f movf main__number,w 674 07d 00ae movwf main__coil_b 675 ; call send_dac {{ 10 , coil_b }} 676 07e 300a movlw 10 677 07f 00b2 movwf send_dac__byte0 678 080 082e movf main__coil_b,w 679 081 00b3 movwf send_dac__byte1 680 082 20a3 call send_dac 681 ; else_if { char = 0c'b' } body end 682 label298__0end: 683 ; if exp=` char = 0c'b' ' empty false 684 ; Other expression=`{ char = 0c'b' }' delay=-1 685 083 288b goto label295__0end 686 label295__0true: 687 ; else_if { char = 0c'a' } body start 688 ; coil_a := number 689 084 082f movf main__number,w 690 085 00ad movwf main__coil_a 691 ; call send_dac {{ 9 , coil_a }} 692 086 3009 movlw 9 693 087 00b2 movwf send_dac__byte0 694 088 082d movf main__coil_a,w 695 089 00b3 movwf send_dac__byte1 696 08a 20a3 call send_dac 697 ; else_if { char = 0c'a' } body end 698 ; if exp=` char = 0c'a' ' generic 699 label295__0end: 700 ; Other expression=`{ char = 0c'a' }' delay=-1 701 08b 2890 goto label292__0end 702 label292__0true: 703 ; else_if { char = 0c'z' } body start 704 ; phase := phase + 1 705 08c 0ab0 incf main__phase,f 706 ; call send_byte {{ char }} 707 08d 082c movf main__char,w 708 08e 00b6 movwf send_byte__character 709 08f 20b9 call send_byte 710 ; else_if { char = 0c'z' } body end 711 ; if exp=` char = 0c'z' ' generic 712 label292__0end: 713 ; Other expression=`{ char = 0c'z' }' delay=-1 714 090 2895 goto label289__0end 715 label289__0true: 716 ; if { char = 0c'Z' } body start 717 ; phase := phase - 1 718 091 03b0 decf main__phase,f 719 ; call send_byte {{ char }} 720 092 082c movf main__char,w 721 093 00b6 movwf send_byte__character 722 094 20b9 call send_byte 723 ; if { char = 0c'Z' } body end 724 ; if exp=` char = 0c'Z' ' generic 725 label289__0end: 726 ; Other expression=`{ char = 0c'Z' }' delay=-1 727 ; if { char = 0c'Z' } end 728 ; number := 0 729 095 01af clrf main__number 730 ; else body end 731 ; if exp=`char <= 0c'7'' generic 732 label286__1end: 733 ; Other expression=`char <= 0c'7'' delay=-1 734 ; if exp=`0c'0' <= char' false goto 735 ; Other expression=`0c'0' <= char' delay=-1 736 and286__0end: 737 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } end 738 ; if { rcif } body end 739 label284__0end: 740 ; if exp=`rcif' empty false 741 ; Other expression=`{ rcif }' delay=-1 742 ; if { rcif } end 743 ; Output the phase : 744 ; if { phase @ 2 } start 745 ; Alias variable for select phase @ 2 746 0030 main__phase__307select0 equ main__phase+0 747 0030 main__phase__307select0__byte equ main__phase+0 748 0002 main__phase__307select0__bit equ 2 749 ; expression=`{ phase @ 2 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 750 096 1930 btfsc main__phase__307select0__byte,main__phase__307select0__bit 751 ; if { phase @ 2 } body start 752 ; phase2 := 1 753 097 1686 bsf phase2__byte,phase2__bit 754 ; if { phase @ 2 } body end 755 098 1d30 btfss main__phase__307select0__byte,main__phase__307select0__bit 756 ; else body start 757 ; phase2 := 0 758 099 1286 bcf phase2__byte,phase2__bit 759 ; else body end 760 ; if exp=` phase @ 2 ' single true and false skip delay=4 761 ; Other expression=`{ phase @ 2 }' delay=4 762 ; if { phase @ 2 } end 763 ; if { phase @ 1 } start 764 ; Alias variable for select phase @ 1 765 0030 main__phase__312select0 equ main__phase+0 766 0030 main__phase__312select0__byte equ main__phase+0 767 0001 main__phase__312select0__bit equ 1 768 ; expression=`{ phase @ 1 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 769 09a 18b0 btfsc main__phase__312select0__byte,main__phase__312select0__bit 770 ; if { phase @ 1 } body start 771 ; phase1 := 1 772 09b 1606 bsf phase1__byte,phase1__bit 773 ; if { phase @ 1 } body end 774 09c 1cb0 btfss main__phase__312select0__byte,main__phase__312select0__bit 775 ; else body start 776 ; phase1 := 0 777 09d 1206 bcf phase1__byte,phase1__bit 778 ; else body end 779 ; if exp=` phase @ 1 ' single true and false skip delay=4 780 ; Other expression=`{ phase @ 1 }' delay=4 781 ; if { phase @ 1 } end 782 ; if { phase @ 0 } start 783 ; Alias variable for select phase @ 0 784 0030 main__phase__317select0 equ main__phase+0 785 0030 main__phase__317select0__byte equ main__phase+0 786 0000 main__phase__317select0__bit equ 0 787 ; expression=`{ phase @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 788 09e 1830 btfsc main__phase__317select0__byte,main__phase__317select0__bit 789 ; if { phase @ 0 } body start 790 ; phase0 := 1 791 09f 1706 bsf phase0__byte,phase0__bit 792 ; if { phase @ 0 } body end 793 0a0 1c30 btfss main__phase__317select0__byte,main__phase__317select0__bit 794 ; else body start 795 ; phase0 := 0 796 0a1 1306 bcf phase0__byte,phase0__bit 797 ; else body end 798 ; if exp=` phase @ 0 ' single true and false skip delay=4 799 ; Other expression=`{ phase @ 0 }' delay=4 800 ; if { phase @ 0 } end 801 0a2 2846 goto main__273loop__forever 802 ; loop_forever ... end 803 ; procedure main end 804 ; comment {DAC routines :} 805 806 ; procedure send_dac start 807 send_dac: 808 0032 send_dac__variables__base equ global__variables__bank0+18 809 0032 send_dac__bytes__base equ send_dac__variables__base+0 810 0034 send_dac__bits__base equ send_dac__variables__base+2 811 0002 send_dac__total__bytes equ 2 812 0032 send_dac__byte0 equ send_dac__bytes__base+0 813 0033 send_dac__byte1 equ send_dac__bytes__base+1 814 ; This procedure will output < byte0 > followed by < byte1 > to the 815 ; Digital to Analog converter . 816 ; dac_select := 0 817 0a3 1105 bcf dac_select__byte,dac_select__bit 818 ; call send_dac_byte {{ byte0 }} 819 0a4 0832 movf send_dac__byte0,w 820 0a5 00b4 movwf send_dac_byte__dac 821 0a6 20ac call send_dac_byte 822 ; call send_dac_byte {{ byte1 }} 823 0a7 0833 movf send_dac__byte1,w 824 0a8 00b4 movwf send_dac_byte__dac 825 0a9 20ac call send_dac_byte 826 ; dac_select := 1 827 0aa 1505 bsf dac_select__byte,dac_select__bit 828 ; procedure send_dac end 829 0ab 3400 retlw 0 830 831 ; procedure send_dac_byte start 832 send_dac_byte: 833 0034 send_dac_byte__variables__base equ global__variables__bank0+20 834 0034 send_dac_byte__bytes__base equ send_dac_byte__variables__base+0 835 0036 send_dac_byte__bits__base equ send_dac_byte__variables__base+2 836 0002 send_dac_byte__total__bytes equ 2 837 0034 send_dac_byte__dac equ send_dac_byte__bytes__base+0 838 0035 send_dac_byte__count equ send_dac_byte__bytes__base+1 839 ; `count_down count 8 ...' start 840 0ac 3008 movlw 8 841 0ad 00b5 movwf send_dac_byte__count 842 send_dac_byte__347_loop: 843 ; serial_data := dac @ 7 844 ; Alias variable for select dac @ 7 845 0034 send_dac_byte__dac__348select0 equ send_dac_byte__dac+0 846 0034 send_dac_byte__dac__348select0__byte equ send_dac_byte__dac+0 847 0007 send_dac_byte__dac__348select0__bit equ 7 848 0ae 1fb4 btfss send_dac_byte__dac__348select0__byte,send_dac_byte__dac__348select0__bit 849 0af 1305 bcf serial_data__byte,serial_data__bit 850 0b0 1bb4 btfsc send_dac_byte__dac__348select0__byte,send_dac_byte__dac__348select0__bit 851 0b1 1705 bsf serial_data__byte,serial_data__bit 852 ; serial_clock := 1 853 0b2 1786 bsf serial_clock__byte,serial_clock__bit 854 ; dac := dac << 1 855 0b3 1003 bcf c___byte,c___bit 856 0b4 0db4 rlf send_dac_byte__dac,f 857 ; serial_clock := 0 858 0b5 1386 bcf serial_clock__byte,serial_clock__bit 859 0b6 0bb5 decfsz send_dac_byte__count,f 860 0b7 28ae goto send_dac_byte__347_loop 861 send_dac_byte__347_done: 862 ; `count_down count 8 ...' end 863 ; procedure send_dac_byte end 864 0b8 3400 retlw 0 865 ; comment {The following procedures are used to send data back to the master :} 866 867 ; procedure send_byte start 868 send_byte: 869 0036 send_byte__variables__base equ global__variables__bank0+22 870 0036 send_byte__bytes__base equ send_byte__variables__base+0 871 0038 send_byte__bits__base equ send_byte__variables__base+2 872 0002 send_byte__total__bytes equ 2 873 0037 send_byte__364byte0 equ send_byte__bytes__base+1 874 0036 send_byte__character equ send_byte__bytes__base+0 875 ; This procedure will cause < character > to placed into 876 ; a ring buffer for transmission . 877 ; send_buffer ~~ {{ send_in_index }} := character 878 0b9 0836 movf send_byte__character,w 879 0ba 00b7 movwf send_byte__364byte0 880 0bb 3022 movlw LOW send_buffer 881 0bc 0720 addwf send_in_index,w 882 0bd 0084 movwf fsr___register 883 0be 0837 movf send_byte__364byte0,w 884 0bf 1383 bcf irp___register,irp___bit 885 0c0 0080 movwf indf___register 886 ; send_in_index := send_in_index + 1 887 0c1 0aa0 incf send_in_index,f 888 ; if { send_in_index >= send_buffer_size } start 889 0c2 300a movlw 10 890 0c3 0220 subwf send_in_index,w 891 ; expression=`{ send_in_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 892 0c4 1803 btfsc c___byte,c___bit 893 ; if { send_in_index >= send_buffer_size } body start 894 ; send_in_index := 0 895 0c5 01a0 clrf send_in_index 896 ; if { send_in_index >= send_buffer_size } body end 897 ; if exp=` send_in_index >= send_buffer_size ' false skip delay=4 898 ; Other expression=`{ send_in_index >= send_buffer_size }' delay=4 899 ; if { send_in_index >= send_buffer_size } end 900 ; procedure send_byte end 901 0c6 3400 retlw 0 902 903 ; procedure send_crlf start 904 send_crlf: 905 0038 send_crlf__variables__base equ global__variables__bank0+24 906 0038 send_crlf__bytes__base equ send_crlf__variables__base+0 907 0038 send_crlf__bits__base equ send_crlf__variables__base+0 908 0000 send_crlf__total__bytes equ 0 909 ; arguments_none 910 ; This procedure will output a carriage - return line - feed 911 ; to the master . 912 ; call send_byte {{ cr }} 913 0c7 300d movlw 13 914 0c8 00b6 movwf send_byte__character 915 0c9 20b9 call send_byte 916 ; call send_byte {{ lf }} 917 0ca 300a movlw 10 918 0cb 00b6 movwf send_byte__character 919 0cc 20b9 call send_byte 920 ; procedure send_crlf end 921 0cd 3400 retlw 0 922 923 ; procedure send_octal start 924 send_octal: 925 0038 send_octal__variables__base equ global__variables__bank0+24 926 0038 send_octal__bytes__base equ send_octal__variables__base+0 927 003a send_octal__bits__base equ send_octal__variables__base+2 928 0002 send_octal__total__bytes equ 2 929 0039 send_octal__390byte0 equ send_octal__bytes__base+1 930 0039 send_octal__389byte0 equ send_octal__bytes__base+1 931 0038 send_octal__number equ send_octal__bytes__base+0 932 ; This procedure will output < number > in octal to the tx port . 933 ; Output the character in octal : 934 ; call send_byte {{ {{ number >> 6 }} + 0c'0' }} 935 0ce 0e38 swapf send_octal__number,w 936 0cf 00b9 movwf send_octal__389byte0 937 0d0 0cb9 rrf send_octal__389byte0,f 938 0d1 0c39 rrf send_octal__389byte0,w 939 0d2 3903 andlw 3 940 0d3 3e30 addlw 48 941 0d4 00b6 movwf send_byte__character 942 0d5 20b9 call send_byte 943 ; call send_byte {{ {{ {{ number >> 3 }} & 7 }} + 0c'0' }} 944 0d6 0c38 rrf send_octal__number,w 945 0d7 00b9 movwf send_octal__390byte0 946 0d8 0cb9 rrf send_octal__390byte0,f 947 0d9 0c39 rrf send_octal__390byte0,w 948 0da 3907 andlw 7 949 0db 3e30 addlw 48 950 0dc 00b6 movwf send_byte__character 951 0dd 20b9 call send_byte 952 ; call send_byte {{ {{ number & 7 }} + 0c'0' }} 953 0de 3007 movlw 7 954 0df 0538 andwf send_octal__number,w 955 0e0 3e30 addlw 48 956 0e1 00b6 movwf send_byte__character 957 0e2 20b9 call send_byte 958 ; call send_byte {{ sp }} 959 0e3 3020 movlw 32 960 0e4 00b6 movwf send_byte__character 961 0e5 20b9 call send_byte 962 ; procedure send_octal end 963 0e6 3400 retlw 0 964 965 ; procedure send_string start 966 send_string: 967 003a send_string__variables__base equ global__variables__bank0+26 968 003a send_string__bytes__base equ send_string__variables__base+0 969 003d send_string__bits__base equ send_string__variables__base+3 970 0003 send_string__total__bytes equ 3 971 003a send_string__message equ send_string__bytes__base+0 972 ; This procedure will output < message > . 973 003b send_string__size equ send_string__bytes__base+1 974 003c send_string__index equ send_string__bytes__base+2 975 ; index := 0 976 0e7 01bc clrf send_string__index 977 ; `while index < message . size ...' start 978 send_string__405while__continue: 979 0e8 018a clrf pclath___register 980 0e9 083a movf send_string__message,w 981 0ea 200f call string___fetch 982 0eb 023c subwf send_string__index,w 983 ; expression=` index < message . size ' exp_delay=4 true_delay=7 false_delay=2 true_size=8 false_size=1 984 0ec 1803 btfsc c___byte,c___bit 985 0ed 28f6 goto send_string__405while__break 986 ; call send_byte {{ message ~~ {{ index }} }} 987 0ee 0a3c incf send_string__index,w 988 0ef 073a addwf send_string__message,w 989 0f0 018a clrf pclath___register 990 0f1 200f call string___fetch 991 0f2 00b6 movwf send_byte__character 992 0f3 20b9 call send_byte 993 ; index := index + 1 994 0f4 0abc incf send_string__index,f 995 0f5 28e8 goto send_string__405while__continue 996 ; if exp=` index < message . size ' false goto 997 ; Other expression=` index < message . size ' delay=-1 998 send_string__405while__break: 999 ; `while index < message . size ...' end 1000 ; call send_byte {{ sp }} 1001 0f6 3020 movlw 32 1002 0f7 00b6 movwf send_byte__character 1003 0f8 20b9 call send_byte 1004 ; procedure send_string end 1005 0f9 3400 retlw 0 1006 1007 ; Register bank 0 used 29 bytes of 96 available bytes 1008 ; Register bank 1 used 0 bytes of 80 available bytes 1009 ; Register bank 2 used 0 bytes of 48 available bytes 1010 ; Register bank 3 used 0 bytes of 0 available bytes 1011 1012 end