1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0120 global__variables__bank2 equ 288 5 01f0 global__variables__bank3 equ 496 6 003d global__bit__variables__bank0 equ 61 7 00a0 global__bit__variables__bank1 equ 160 8 0120 global__bit__variables__bank2 equ 288 9 01f0 global__bit__variables__bank3 equ 496 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 0003 rp0___byte equ 3 17 0005 rp0___bit equ 5 18 0003 rp1___byte equ 3 19 0006 rp1___bit equ 6 20 0003 irp___byte equ 3 21 0007 irp___bit equ 7 22 0085 trisa___register equ 0x85 23 0086 trisb___register equ 0x86 24 0004 fsr___register equ 4 25 000a pclath___register equ 10 26 org 0 27 start: 28 000 0000 nop 29 001 0000 nop 30 002 0000 nop 31 003 2805 goto skip___interrupt 32 interrupt___vector: 33 004 0009 retfie 34 skip___interrupt: 35 ; Initialize A/D system to allow digital I/O 36 005 3003 movlw 3 37 006 009f movwf 31 38 ; Initialize TRIS registers 39 007 3083 movlw 131 40 ; Switch from register bank 0 to register bank 1 (which contains trisa___register) 41 008 1683 bsf rp0___byte,rp0___bit 42 ; Register bank is now 1 43 009 0085 movwf trisa___register 44 00a 300f movlw 15 45 00b 0086 movwf trisb___register 46 00c 018a clrf pclath___register 47 ; Switch from register bank 1 to register bank 0 48 00d 1283 bcf rp0___byte,rp0___bit 49 ; Register bank is now 0 50 00e 2816 goto main 51 ; comment ############################################################################# 52 ; comment {} 53 ; comment {Copyright < c > 2002 by Wayne C . Gramlich .} 54 ; comment {All rights reserved .} 55 ; comment {} 56 ; comment {Permission to use , copy , modify , distribute , and sell this software} 57 ; comment {for any purpose is hereby granted without fee provided that the above} 58 ; comment {copyright notice and this permission are retained . The author makes} 59 ; comment {no representations about the suitability of this software for any purpose .} 60 ; comment {It is provided { as is } without express or implied warranty .} 61 ; comment {} 62 ; comment {This is control microcode for Wayne ' s motion CNC board at :} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / cnc / motion / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment {Some pin assignments :} 69 ; comment {} 70 ; comment {No Name Kind Description} 71 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 72 ; comment {1 RA2 / AN2 / VREF Digital Out DAC Chip Select} 73 ; comment {2 RA3 / AN3 / CMP1 Digital Out Home Out *} 74 ; comment {3 RA4 / TOCKI / CMP2 Digital In Home} 75 ; comment {4 RA5 / MCLR * / THV Digital In Home In *} 76 ; comment {5 VSS Ground Ground} 77 ; comment {6 RB0 / INT Digital In Step} 78 ; comment {7 RB1 / RX / DT Digital In Receive} 79 ; comment {8 RB2 / TX / CK Digital Out Transmit} 80 ; comment {9 RB3 / CCP1 Digital In Direction} 81 ; comment {10 RB4 / PGM Digital Out Phase 1} 82 ; comment {11 RB5 Digital Out Phase 2} 83 ; comment {12 RB6 / T1OSO / TICK1 Digital Out Phase 0} 84 ; comment {13 RB7 / T1OSI Digital Out Serial Clock} 85 ; comment {14 VDD Power + 5 Volts} 86 ; comment {15 RA6 / OSC2 / CLKOUT Digital Out Serial Data} 87 ; comment {16 RA7 / OSC1 / CLKIN Digital In Oscillator} 88 ; comment {17 RA0 / AN0 Digital In Encoder 0} 89 ; comment {18 RA1 / AN1 Digital In Encoder 1} 90 ; comment {} 91 ; comment ############################################################################# 92 ; processor pic16f628 cp = off cpd = off lvp = off bowden = off mclre = off pwrte = off wdte = off fosc = ec 93 ; 16139=0x3f0b 8199=0x2007 94 __config 16139 95 2007 configuration___address equ 8199 96 ; constant clock_rate 20000000 97 1312d00 clock_rate equ 20000000 98 ; comment {Some character constants :} 99 ; constant sp 32 100 0020 sp equ 32 101 ; constant cr 13 102 000d cr equ 13 103 ; constant lf 10 104 000a lf equ 10 105 ; comment {Some register definitions :} 106 0001 tmr0 equ 1 107 0003 status equ 3 108 ; bind c status @ 0 109 0003 c equ status+0 110 0003 c__byte equ status+0 111 0000 c__bit equ 0 112 ; bind z status @ 2 113 0003 z equ status+0 114 0003 z__byte equ status+0 115 0002 z__bit equ 2 116 000b intcon equ 11 117 ; bind gie intcon @ 7 118 000b gie equ intcon+0 119 000b gie__byte equ intcon+0 120 0007 gie__bit equ 7 121 ; bind t0ie intcon @ 5 122 000b t0ie equ intcon+0 123 000b t0ie__byte equ intcon+0 124 0005 t0ie__bit equ 5 125 ; bind inte intcon @ 4 126 000b inte equ intcon+0 127 000b inte__byte equ intcon+0 128 0004 inte__bit equ 4 129 ; bind rbie intcon @ 3 130 000b rbie equ intcon+0 131 000b rbie__byte equ intcon+0 132 0003 rbie__bit equ 3 133 ; bind t0if intcon @ 2 134 000b t0if equ intcon+0 135 000b t0if__byte equ intcon+0 136 0002 t0if__bit equ 2 137 ; bind intf intcon @ 1 138 000b intf equ intcon+0 139 000b intf__byte equ intcon+0 140 0001 intf__bit equ 1 141 ; bind rbif intcon @ 0 142 000b rbif equ intcon+0 143 000b rbif__byte equ intcon+0 144 0000 rbif__bit equ 0 145 000c pir1 equ 12 146 ; bind eeif pir1 @ 7 147 000c eeif equ pir1+0 148 000c eeif__byte equ pir1+0 149 0007 eeif__bit equ 7 150 ; bind cmif pir1 @ 6 151 000c cmif equ pir1+0 152 000c cmif__byte equ pir1+0 153 0006 cmif__bit equ 6 154 ; bind rcif pir1 @ 5 155 000c rcif equ pir1+0 156 000c rcif__byte equ pir1+0 157 0005 rcif__bit equ 5 158 ; bind txif pir1 @ 4 159 000c txif equ pir1+0 160 000c txif__byte equ pir1+0 161 0004 txif__bit equ 4 162 ; bind ccp1if pir1 @ 2 163 000c ccp1if equ pir1+0 164 000c ccp1if__byte equ pir1+0 165 0002 ccp1if__bit equ 2 166 ; bind tmr2if pir1 @ 1 167 000c tmr2if equ pir1+0 168 000c tmr2if__byte equ pir1+0 169 0001 tmr2if__bit equ 1 170 ; bind tmr1if pir1 @ 0 171 000c tmr1if equ pir1+0 172 000c tmr1if__byte equ pir1+0 173 0000 tmr1if__bit equ 0 174 0018 rcsta equ 24 175 ; bind spen rcsta @ 7 176 0018 spen equ rcsta+0 177 0018 spen__byte equ rcsta+0 178 0007 spen__bit equ 7 179 ; bind rx9 rcsta @ 6 180 0018 rx9 equ rcsta+0 181 0018 rx9__byte equ rcsta+0 182 0006 rx9__bit equ 6 183 ; bind sren rcsta @ 5 184 0018 sren equ rcsta+0 185 0018 sren__byte equ rcsta+0 186 0005 sren__bit equ 5 187 ; bind cren rcsta @ 4 188 0018 cren equ rcsta+0 189 0018 cren__byte equ rcsta+0 190 0004 cren__bit equ 4 191 ; bind aden rcsta @ 3 192 0018 aden equ rcsta+0 193 0018 aden__byte equ rcsta+0 194 0003 aden__bit equ 3 195 ; bind ferr rcsta @ 2 196 0018 ferr equ rcsta+0 197 0018 ferr__byte equ rcsta+0 198 0002 ferr__bit equ 2 199 ; bind oerr rcsta @ 1 200 0018 oerr equ rcsta+0 201 0018 oerr__byte equ rcsta+0 202 0001 oerr__bit equ 1 203 ; bind rx9d rcsta @ 0 204 0018 rx9d equ rcsta+0 205 0018 rx9d__byte equ rcsta+0 206 0000 rx9d__bit equ 0 207 0019 txreg equ 25 208 001a rcreg equ 26 209 ; comment {Comparator module control :} 210 001f cmcon equ 31 211 ; bind c2out cmcon @ 7 212 001f c2out equ cmcon+0 213 001f c2out__byte equ cmcon+0 214 0007 c2out__bit equ 7 215 ; bind c1out cmcon @ 6 216 001f c1out equ cmcon+0 217 001f c1out__byte equ cmcon+0 218 0006 c1out__bit equ 6 219 ; bind c2inv cmcon @ 5 220 001f c2inv equ cmcon+0 221 001f c2inv__byte equ cmcon+0 222 0005 c2inv__bit equ 5 223 ; bind c1inv cmcon @ 4 224 001f c1inv equ cmcon+0 225 001f c1inv__byte equ cmcon+0 226 0004 c1inv__bit equ 4 227 ; bind cis cmcon @ 3 228 001f cis equ cmcon+0 229 001f cis__byte equ cmcon+0 230 0003 cis__bit equ 3 231 ; bind cm2 cmcon @ 2 232 001f cm2 equ cmcon+0 233 001f cm2__byte equ cmcon+0 234 0002 cm2__bit equ 2 235 ; bind cm1 cmcon @ 1 236 001f cm1 equ cmcon+0 237 001f cm1__byte equ cmcon+0 238 0001 cm1__bit equ 1 239 ; bind cm0 cmcon @ 0 240 001f cm0 equ cmcon+0 241 001f cm0__byte equ cmcon+0 242 0000 cm0__bit equ 0 243 0081 option equ 129 244 ; bind t0cs option @ 5 245 0081 t0cs equ option+0 246 0081 t0cs__byte equ option+0 247 0005 t0cs__bit equ 5 248 ; bind t0se option @ 4 249 0081 t0se equ option+0 250 0081 t0se__byte equ option+0 251 0004 t0se__bit equ 4 252 ; bind psa option @ 3 253 0081 psa equ option+0 254 0081 psa__byte equ option+0 255 0003 psa__bit equ 3 256 ; bind ps2 option @ 2 257 0081 ps2 equ option+0 258 0081 ps2__byte equ option+0 259 0002 ps2__bit equ 2 260 ; bind ps1 option @ 1 261 0081 ps1 equ option+0 262 0081 ps1__byte equ option+0 263 0001 ps1__bit equ 1 264 ; bind ps0 option @ 0 265 0081 ps0 equ option+0 266 0081 ps0__byte equ option+0 267 0000 ps0__bit equ 0 268 008c pie1 equ 140 269 ; bind eeie pie1 @ 7 270 008c eeie equ pie1+0 271 008c eeie__byte equ pie1+0 272 0007 eeie__bit equ 7 273 ; bind cmie pie1 @ 6 274 008c cmie equ pie1+0 275 008c cmie__byte equ pie1+0 276 0006 cmie__bit equ 6 277 ; bind rcie pie1 @ 5 278 008c rcie equ pie1+0 279 008c rcie__byte equ pie1+0 280 0005 rcie__bit equ 5 281 ; bind txie pie1 @ 4 282 008c txie equ pie1+0 283 008c txie__byte equ pie1+0 284 0004 txie__bit equ 4 285 ; bind ccp1ie pie1 @ 2 286 008c ccp1ie equ pie1+0 287 008c ccp1ie__byte equ pie1+0 288 0002 ccp1ie__bit equ 2 289 ; bind tmr2ie pie1 @ 1 290 008c tmr2ie equ pie1+0 291 008c tmr2ie__byte equ pie1+0 292 0001 tmr2ie__bit equ 1 293 ; bind tmr1ie pie1 @ 0 294 008c tmr1ie equ pie1+0 295 008c tmr1ie__byte equ pie1+0 296 0000 tmr1ie__bit equ 0 297 0098 txsta equ 152 298 ; bind tx9 txsta @ 6 299 0098 tx9 equ txsta+0 300 0098 tx9__byte equ txsta+0 301 0006 tx9__bit equ 6 302 ; bind txen txsta @ 5 303 0098 txen equ txsta+0 304 0098 txen__byte equ txsta+0 305 0005 txen__bit equ 5 306 ; bind sync txsta @ 4 307 0098 sync equ txsta+0 308 0098 sync__byte equ txsta+0 309 0004 sync__bit equ 4 310 ; bind brgh txsta @ 2 311 0098 brgh equ txsta+0 312 0098 brgh__byte equ txsta+0 313 0002 brgh__bit equ 2 314 ; bind trmt txsta @ 1 315 0098 trmt equ txsta+0 316 0098 trmt__byte equ txsta+0 317 0001 trmt__bit equ 1 318 ; bind tx9d txsta @ 0 319 0098 tx9d equ txsta+0 320 0098 tx9d__byte equ txsta+0 321 0000 tx9d__bit equ 0 322 0099 spbrg equ 153 323 ; comment {Some port , bit , and pin definitions :} 324 ; comment {Port A pin assignments :} 325 ; comment {RA0 : Encoder 0} 326 ; comment {RA1 : Encoder 1} 327 ; comment {RA2 : DAC Chip Select} 328 ; comment {RA3 : Home Out} 329 ; comment {RA4 : Home} 330 ; comment {RA5 : Home In} 331 ; comment {RA6 : Serial Data} 332 ; comment {RA7 : Oscillator In} 333 ; constant encoder0_bit 0 334 0000 encoder0_bit equ 0 335 ; constant encoder1_bit 1 336 0001 encoder1_bit equ 1 337 ; constant dac_select_bit 2 338 0002 dac_select_bit equ 2 339 ; constant home_out_bit 3 340 0003 home_out_bit equ 3 341 ; constant home_bit 4 342 0004 home_bit equ 4 343 ; constant home_in_bit 5 344 0005 home_in_bit equ 5 345 ; constant serial_data_bit 6 346 0006 serial_data_bit equ 6 347 ; constant osc_in_bit 7 348 0007 osc_in_bit equ 7 349 0005 porta equ 5 350 0005 encoder0__byte equ 5 351 0000 encoder0__bit equ 0 352 0005 encoder1__byte equ 5 353 0001 encoder1__bit equ 1 354 0005 dac_select__byte equ 5 355 0002 dac_select__bit equ 2 356 0005 home_out_bit__byte equ 5 357 0003 home_out_bit__bit equ 3 358 0005 home_bit__byte equ 5 359 0004 home_bit__bit equ 4 360 0005 home_in__byte equ 5 361 0005 home_in__bit equ 5 362 0005 serial_data__byte equ 5 363 0006 serial_data__bit equ 6 364 0005 osc_in__byte equ 5 365 0007 osc_in__bit equ 7 366 ; comment {Port B pin assignments :} 367 ; comment {RB0 : Step} 368 ; comment {RB1 : Serial Input < RX >} 369 ; comment {RB2 : Serial Output < TX >} 370 ; comment {RB3 : Direction} 371 ; comment {RB4 : Phase 1} 372 ; comment {RB5 : Phase 2} 373 ; comment {RB6 : Phase 0} 374 ; comment {RB7 : Serial Clock} 375 ; constant step_bit 0 376 0000 step_bit equ 0 377 ; constant rx_bit 1 378 0001 rx_bit equ 1 379 ; constant tx_bit 2 380 0002 tx_bit equ 2 381 ; constant direction_bit 3 382 0003 direction_bit equ 3 383 ; constant phase1_bit 4 384 0004 phase1_bit equ 4 385 ; constant phase2_bit 5 386 0005 phase2_bit equ 5 387 ; constant phase0_bit 6 388 0006 phase0_bit equ 6 389 ; constant serial_clock_bit 7 390 0007 serial_clock_bit equ 7 391 0006 portb equ 6 392 0006 step__byte equ 6 393 0000 step__bit equ 0 394 ; comment {When using the USART , both the TX and RX pins must be set to input :} 395 0006 tx_pin__byte equ 6 396 0002 tx_pin__bit equ 2 397 0006 rx_pin__byte equ 6 398 0001 rx_pin__bit equ 1 399 0006 direction__byte equ 6 400 0003 direction__bit equ 3 401 0006 phase1__byte equ 6 402 0004 phase1__bit equ 4 403 0006 phase2__byte equ 6 404 0005 phase2__bit equ 5 405 0006 phase0__byte equ 6 406 0006 phase0__bit equ 6 407 0006 serial_clock__byte equ 6 408 0007 serial_clock__bit equ 7 409 ; string_constants Start 410 string___fetch: 411 00f 0082 movwf pcl___register 412 ; hello_string = 0s'Ctrl' 413 0000 hello_string___string equ 0 414 hello_string: 415 010 0782 addwf pcl___register,f 416 ; Length = 4 417 011 3404 retlw 4 418 ; `Ctrl' 419 012 3443 retlw 67 420 013 3474 retlw 116 421 014 3472 retlw 114 422 015 346c retlw 108 423 ; string__constants End 424 0020 send_in_index equ global__variables__bank0+0 425 0021 send_out_index equ global__variables__bank0+1 426 ; constant send_buffer_size 10 427 000a send_buffer_size equ 10 428 0022 send_buffer equ global__variables__bank0+2 429 430 ; procedure main start 431 main: 432 002c main__variables__base equ global__variables__bank0+12 433 002c main__bytes__base equ main__variables__base+0 434 0032 main__bits__base equ main__variables__base+6 435 0006 main__total__bytes equ 6 436 0031 main__292byte0 equ main__bytes__base+5 437 ; arguments_none 438 002c main__char equ main__bytes__base+0 439 002d main__coil_a equ main__bytes__base+1 440 002e main__coil_b equ main__bytes__base+2 441 002f main__number equ main__bytes__base+3 442 0030 main__phase equ main__bytes__base+4 443 ; Get all interrupts turned off : 444 ; intcon := 0 445 016 018b clrf intcon 446 ; pie1 := 0 447 ; Switch from register bank 0 to register bank 1 (which contains pie1) 448 017 1683 bsf rp0___byte,rp0___bit 449 ; Register bank is now 1 450 018 018c clrf pie1 451 ; pir1 := 0 452 ; Switch from register bank 1 to register bank 0 (which contains pir1) 453 019 1283 bcf rp0___byte,rp0___bit 454 ; Register bank is now 0 455 01a 018c clrf pir1 456 ; Initialize UART : 457 ; Prescaler = low : 458 ; brgh := 0 459 ; Prescaler = high 460 ; brgh := 1 461 ; Switch from register bank 0 to register bank 1 (which contains brgh__byte) 462 01b 1683 bsf rp0___byte,rp0___bit 463 ; Register bank is now 1 464 01c 1518 bsf brgh__byte,brgh__bit 465 ; Baud rate = 2400 baud : 466 ; spbrg := 129 467 ; Baud rate = 115200 baud : 468 ; spbrg := 10 469 01d 300a movlw 10 470 01e 0099 movwf spbrg 471 ; Asynchronous mode : 472 ; sync := 0 473 01f 1218 bcf sync__byte,sync__bit 474 ; 8 - bit mode : 475 ; tx9 := 0 476 020 1318 bcf tx9__byte,tx9__bit 477 ; Serial Port Enable : 478 ; spen := 1 479 ; Switch from register bank 1 to register bank 0 (which contains spen__byte) 480 021 1283 bcf rp0___byte,rp0___bit 481 ; Register bank is now 0 482 022 1798 bsf spen__byte,spen__bit 483 ; Keep interrupts off : 484 ; txie := 0 485 ; Switch from register bank 0 to register bank 1 (which contains txie__byte) 486 023 1683 bsf rp0___byte,rp0___bit 487 ; Register bank is now 1 488 024 120c bcf txie__byte,txie__bit 489 ; Clear out an previous character . 490 ; txif := 0 491 ; Switch from register bank 1 to register bank 0 (which contains txif__byte) 492 025 1283 bcf rp0___byte,rp0___bit 493 ; Register bank is now 0 494 026 120c bcf txif__byte,txif__bit 495 ; Enable the transmitter : 496 ; txen := 1 497 ; Switch from register bank 0 to register bank 1 (which contains txen__byte) 498 027 1683 bsf rp0___byte,rp0___bit 499 ; Register bank is now 1 500 028 1698 bsf txen__byte,txen__bit 501 ; Enable the receiver : 502 ; Keep inerrupts off : 503 ; rcie := 0 504 029 128c bcf rcie__byte,rcie__bit 505 ; Enable continuous reception : 506 ; cren := 1 507 ; Switch from register bank 1 to register bank 0 (which contains cren__byte) 508 02a 1283 bcf rp0___byte,rp0___bit 509 ; Register bank is now 0 510 02b 1618 bsf cren__byte,cren__bit 511 ; Enable single receptions : 512 ; sren := 1 513 02c 1698 bsf sren__byte,sren__bit 514 ; Disable address 515 ; aden := 0 516 02d 1198 bcf aden__byte,aden__bit 517 ; Initialize the comparator module : 518 ; Two independent comparators : 519 ; cmcon := 4 520 ; Initialize the timer module : 521 ; t0cs := 0 522 ; Switch from register bank 0 to register bank 1 (which contains t0cs__byte) 523 02e 1683 bsf rp0___byte,rp0___bit 524 ; Register bank is now 1 525 02f 1281 bcf t0cs__byte,t0cs__bit 526 ; psa := 0 527 030 1181 bcf psa__byte,psa__bit 528 ; ps2 := 1 529 031 1501 bsf ps2__byte,ps2__bit 530 ; ps1 := 1 531 032 1481 bsf ps1__byte,ps1__bit 532 ; ps0 := 1 533 033 1401 bsf ps0__byte,ps0__bit 534 ; Initialize ring buffer : 535 ; send_in_index := 0 536 ; Switch from register bank 1 to register bank 0 (which contains send_in_index) 537 034 1283 bcf rp0___byte,rp0___bit 538 ; Register bank is now 0 539 035 01a0 clrf send_in_index 540 ; send_out_index := 0 541 036 01a1 clrf send_out_index 542 ; Print out a welcome message : 543 ; call send_string {{ hello_string }} 544 037 3011 movlw LOW hello_string+1 545 038 00ba movwf send_string__message 546 039 2117 call send_string 547 ; call send_crlf {{ }} 548 03a 20f7 call send_crlf 549 ; A little initialization : 550 ; number := 0 551 03b 01af clrf main__number 552 ; phase := 0 553 03c 01b0 clrf main__phase 554 ; dac_select := 1 555 03d 1505 bsf dac_select__byte,dac_select__bit 556 ; serial_clock := 0 557 03e 1386 bcf serial_clock__byte,serial_clock__bit 558 ; serial_data := 0 559 03f 1305 bcf serial_data__byte,serial_data__bit 560 ; call send_dac {{ 9 , 127 }} 561 040 3009 movlw 9 562 041 00b2 movwf send_dac__byte0 563 042 307f movlw 127 564 043 00b3 movwf send_dac__byte1 565 044 20d3 call send_dac 566 ; call send_dac {{ 10 , 127 }} 567 045 300a movlw 10 568 046 00b2 movwf send_dac__byte0 569 047 307f movlw 127 570 048 00b3 movwf send_dac__byte1 571 049 20d3 call send_dac 572 ; Main loop 573 ; loop_forever ... start 574 main__277loop__forever: 575 ; See whether we can transmit a character : 576 ; if { send_in_index != send_out_index && txif } start 577 04a 0820 movf send_in_index,w 578 04b 0221 subwf send_out_index,w 579 ; expression=`send_in_index != send_out_index' exp_delay=2 true_delay=-1 false_delay=2 true_size=13 false_size=1 580 04c 1903 btfsc z___byte,z___bit 581 04d 285b goto and279__0false 582 ; expression=`txif' exp_delay=0 true_delay=11 false_delay=0 true_size=11 false_size=0 583 04e 1e0c btfss txif__byte,txif__bit 584 04f 285b goto label279__1end 585 and279__0true: 586 ; if { send_in_index != send_out_index && txif } body start 587 ; txreg := send_buffer ~~ {{ send_out_index }} 588 050 3022 movlw LOW send_buffer 589 051 0721 addwf send_out_index,w 590 052 0084 movwf fsr___register 591 053 1383 bcf irp___register,irp___bit 592 054 0800 movf indf___register,w 593 055 0099 movwf txreg 594 ; send_out_index := send_out_index + 1 595 056 0aa1 incf send_out_index,f 596 ; if { send_out_index >= send_buffer_size } start 597 057 300a movlw 10 598 058 0221 subwf send_out_index,w 599 ; expression=`{ send_out_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 600 059 1803 btfsc c___byte,c___bit 601 ; if { send_out_index >= send_buffer_size } body start 602 ; send_out_index := 0 603 05a 01a1 clrf send_out_index 604 ; if { send_out_index >= send_buffer_size } body end 605 ; if exp=` send_out_index >= send_buffer_size ' false skip delay=4 606 ; Other expression=`{ send_out_index >= send_buffer_size }' delay=4 607 ; if { send_out_index >= send_buffer_size } end 608 ; if { send_in_index != send_out_index && txif } body end 609 label279__1end: 610 ; if exp=`txif' empty false 611 ; Other expression=`txif' delay=-1 612 ; if exp=`send_in_index != send_out_index' false goto 613 ; Other expression=`send_in_index != send_out_index' delay=-1 614 and279__0false: 615 and279__0end: 616 ; if { send_in_index != send_out_index && txif } end 617 ; See whether we ' ve got a character : 618 ; if { rcif } start 619 ; expression=`{ rcif }' exp_delay=0 true_delay=-1 false_delay=0 true_size=107 false_size=0 620 05b 1e8c btfss rcif__byte,rcif__bit 621 05c 28c6 goto label288__0end 622 ; if { rcif } body start 623 ; char := rcreg 624 05d 081a movf rcreg,w 625 05e 00ac movwf main__char 626 ; call send_byte {{ char }} 627 05f 00b6 movwf send_byte__character 628 060 20e9 call send_byte 629 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } start 630 061 3030 movlw 48 631 062 022c subwf main__char,w 632 ; expression=`0c'0' <= char' exp_delay=2 true_delay=-1 false_delay=1 true_size=98 false_size=1 633 063 1c03 btfss c___byte,c___bit 634 064 2872 goto and291__0false 635 065 3038 movlw 56 636 066 022c subwf main__char,w 637 ; expression=`char <= 0c'7'' exp_delay=2 true_delay=8 false_delay=-1 true_size=8 false_size=85 638 067 1803 btfsc c___byte,c___bit 639 068 2872 goto label291__1false 640 label291__1true: 641 and291__0true: 642 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body start 643 ; number := {{ number << 3 }} + char - 0c'0' 644 069 0d2f rlf main__number,w 645 06a 00b1 movwf main__292byte0 646 06b 0db1 rlf main__292byte0,f 647 06c 0d31 rlf main__292byte0,w 648 06d 39f8 andlw 248 649 06e 072c addwf main__char,w 650 06f 3ed0 addlw 208 651 070 00af movwf main__number 652 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body end 653 071 28c6 goto label291__1end 654 label291__1false: 655 and291__0false: 656 072 3061 movlw 97 657 073 022c subwf main__char,w 658 ; expression=`{ char = 0c'a' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=12 false_size=68 659 074 1d03 btfss z___byte,z___bit 660 075 2883 goto label293__0false 661 label293__0true: 662 ; else_if { char = 0c'a' } body start 663 ; coil_a := number 664 076 082f movf main__number,w 665 077 00ad movwf main__coil_a 666 ; call send_dac {{ 9 , coil_a }} 667 078 3009 movlw 9 668 079 00b2 movwf send_dac__byte0 669 07a 082d movf main__coil_a,w 670 07b 00b3 movwf send_dac__byte1 671 07c 20d3 call send_dac 672 ; call send_octal {{ coil_a }} 673 07d 082d movf main__coil_a,w 674 07e 00b8 movwf send_octal__number 675 07f 20fe call send_octal 676 ; call send_crlf {{ }} 677 080 20f7 call send_crlf 678 ; number := 0 679 081 01af clrf main__number 680 ; else_if { char = 0c'a' } body end 681 082 28c6 goto label293__0end 682 label293__0false: 683 083 3062 movlw 98 684 084 022c subwf main__char,w 685 ; expression=`{ char = 0c'b' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=12 false_size=51 686 085 1d03 btfss z___byte,z___bit 687 086 2894 goto label299__0false 688 label299__0true: 689 ; else_if { char = 0c'b' } body start 690 ; coil_b := number 691 087 082f movf main__number,w 692 088 00ae movwf main__coil_b 693 ; call send_dac {{ 10 , coil_b }} 694 089 300a movlw 10 695 08a 00b2 movwf send_dac__byte0 696 08b 082e movf main__coil_b,w 697 08c 00b3 movwf send_dac__byte1 698 08d 20d3 call send_dac 699 ; call send_octal {{ coil_b }} 700 08e 082e movf main__coil_b,w 701 08f 00b8 movwf send_octal__number 702 090 20fe call send_octal 703 ; call send_crlf {{ }} 704 091 20f7 call send_crlf 705 ; number := 0 706 092 01af clrf main__number 707 ; else_if { char = 0c'b' } body end 708 093 28c6 goto label299__0end 709 label299__0false: 710 094 3063 movlw 99 711 095 022c subwf main__char,w 712 ; expression=`{ char = 0c'c' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=2 false_size=44 713 096 1d03 btfss z___byte,z___bit 714 097 289b goto label305__0false 715 label305__0true: 716 ; else_if { char = 0c'c' } body start 717 ; call send_crlf {{ }} 718 098 20f7 call send_crlf 719 ; number := 0 720 099 01af clrf main__number 721 ; else_if { char = 0c'c' } body end 722 09a 28c6 goto label305__0end 723 label305__0false: 724 09b 3064 movlw 100 725 09c 022c subwf main__char,w 726 ; expression=`{ char = 0c'd' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=6 false_size=33 727 09d 1d03 btfss z___byte,z___bit 728 09e 28a6 goto label308__0false 729 label308__0true: 730 ; else_if { char = 0c'd' } body start 731 ; phase := phase - 1 732 09f 03b0 decf main__phase,f 733 ; call send_octal {{ phase }} 734 0a0 0830 movf main__phase,w 735 0a1 00b8 movwf send_octal__number 736 0a2 20fe call send_octal 737 ; call send_crlf {{ }} 738 0a3 20f7 call send_crlf 739 ; number := 0 740 0a4 01af clrf main__number 741 ; else_if { char = 0c'd' } body end 742 0a5 28c6 goto label308__0end 743 label308__0false: 744 0a6 3069 movlw 105 745 0a7 022c subwf main__char,w 746 ; expression=`{ char = 0c'i' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=6 false_size=22 747 0a8 1d03 btfss z___byte,z___bit 748 0a9 28b1 goto label313__0false 749 label313__0true: 750 ; else_if { char = 0c'i' } body start 751 ; phase := phase + 1 752 0aa 0ab0 incf main__phase,f 753 ; call send_octal {{ phase }} 754 0ab 0830 movf main__phase,w 755 0ac 00b8 movwf send_octal__number 756 0ad 20fe call send_octal 757 ; call send_crlf {{ }} 758 0ae 20f7 call send_crlf 759 ; number := 0 760 0af 01af clrf main__number 761 ; else_if { char = 0c'i' } body end 762 0b0 28c6 goto label313__0end 763 label313__0false: 764 0b1 3070 movlw 112 765 0b2 022c subwf main__char,w 766 ; expression=`{ char = 0c'p' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=7 false_size=10 767 0b3 1d03 btfss z___byte,z___bit 768 0b4 28bc goto label318__0false 769 label318__0true: 770 ; else_if { char = 0c'p' } body start 771 ; phase := number 772 0b5 082f movf main__number,w 773 0b6 00b0 movwf main__phase 774 ; call send_octal {{ phase }} 775 0b7 00b8 movwf send_octal__number 776 0b8 20fe call send_octal 777 ; call send_crlf {{ }} 778 0b9 20f7 call send_crlf 779 ; number := 0 780 0ba 01af clrf main__number 781 ; else_if { char = 0c'p' } body end 782 0bb 28c6 goto label318__0end 783 label318__0false: 784 0bc 3050 movlw 80 785 0bd 022c subwf main__char,w 786 ; expression=`{ char = 0c'P' }' exp_delay=2 true_delay=1 false_delay=-1 true_size=1 false_size=4 787 0be 1903 btfsc z___byte,z___bit 788 0bf 28c5 goto label323__0true 789 label323__0false: 790 ; else body start 791 ; call send_byte {{ 0c'?' }} 792 0c0 303f movlw 63 793 0c1 00b6 movwf send_byte__character 794 0c2 20e9 call send_byte 795 ; call send_crlf {{ }} 796 0c3 20f7 call send_crlf 797 ; else body end 798 0c4 28c6 goto label323__0end 799 label323__0true: 800 ; else_if { char = 0c'P' } body start 801 ; number := 0 802 0c5 01af clrf main__number 803 ; else_if { char = 0c'P' } body end 804 ; if exp=` char = 0c'P' ' generic 805 label323__0end: 806 ; Other expression=`{ char = 0c'P' }' delay=-1 807 ; if exp=` char = 0c'p' ' generic 808 label318__0end: 809 ; Other expression=`{ char = 0c'p' }' delay=-1 810 ; if exp=` char = 0c'i' ' generic 811 label313__0end: 812 ; Other expression=`{ char = 0c'i' }' delay=-1 813 ; if exp=` char = 0c'd' ' generic 814 label308__0end: 815 ; Other expression=`{ char = 0c'd' }' delay=-1 816 ; if exp=` char = 0c'c' ' generic 817 label305__0end: 818 ; Other expression=`{ char = 0c'c' }' delay=-1 819 ; if exp=` char = 0c'b' ' generic 820 label299__0end: 821 ; Other expression=`{ char = 0c'b' }' delay=-1 822 ; if exp=` char = 0c'a' ' generic 823 label293__0end: 824 ; Other expression=`{ char = 0c'a' }' delay=-1 825 ; if exp=`char <= 0c'7'' generic 826 label291__1end: 827 ; Other expression=`char <= 0c'7'' delay=-1 828 ; if exp=`0c'0' <= char' false goto 829 ; Other expression=`0c'0' <= char' delay=-1 830 and291__0end: 831 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } end 832 ; if { rcif } body end 833 label288__0end: 834 ; if exp=`rcif' empty false 835 ; Other expression=`{ rcif }' delay=-1 836 ; if { rcif } end 837 ; Output the phase : 838 ; if { phase @ 2 } start 839 ; Alias variable for select phase @ 2 840 0030 main__phase__332select0 equ main__phase+0 841 0030 main__phase__332select0__byte equ main__phase+0 842 0002 main__phase__332select0__bit equ 2 843 ; expression=`{ phase @ 2 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 844 0c6 1930 btfsc main__phase__332select0__byte,main__phase__332select0__bit 845 ; if { phase @ 2 } body start 846 ; phase2 := 1 847 0c7 1686 bsf phase2__byte,phase2__bit 848 ; if { phase @ 2 } body end 849 0c8 1d30 btfss main__phase__332select0__byte,main__phase__332select0__bit 850 ; else body start 851 ; phase2 := 0 852 0c9 1286 bcf phase2__byte,phase2__bit 853 ; else body end 854 ; if exp=` phase @ 2 ' single true and false skip delay=4 855 ; Other expression=`{ phase @ 2 }' delay=4 856 ; if { phase @ 2 } end 857 ; if { phase @ 1 } start 858 ; Alias variable for select phase @ 1 859 0030 main__phase__337select0 equ main__phase+0 860 0030 main__phase__337select0__byte equ main__phase+0 861 0001 main__phase__337select0__bit equ 1 862 ; expression=`{ phase @ 1 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 863 0ca 18b0 btfsc main__phase__337select0__byte,main__phase__337select0__bit 864 ; if { phase @ 1 } body start 865 ; phase1 := 1 866 0cb 1606 bsf phase1__byte,phase1__bit 867 ; if { phase @ 1 } body end 868 0cc 1cb0 btfss main__phase__337select0__byte,main__phase__337select0__bit 869 ; else body start 870 ; phase1 := 0 871 0cd 1206 bcf phase1__byte,phase1__bit 872 ; else body end 873 ; if exp=` phase @ 1 ' single true and false skip delay=4 874 ; Other expression=`{ phase @ 1 }' delay=4 875 ; if { phase @ 1 } end 876 ; if { phase @ 0 } start 877 ; Alias variable for select phase @ 0 878 0030 main__phase__342select0 equ main__phase+0 879 0030 main__phase__342select0__byte equ main__phase+0 880 0000 main__phase__342select0__bit equ 0 881 ; expression=`{ phase @ 0 }' exp_delay=0 true_delay=1 false_delay=1 true_size=1 false_size=1 882 0ce 1830 btfsc main__phase__342select0__byte,main__phase__342select0__bit 883 ; if { phase @ 0 } body start 884 ; phase0 := 1 885 0cf 1706 bsf phase0__byte,phase0__bit 886 ; if { phase @ 0 } body end 887 0d0 1c30 btfss main__phase__342select0__byte,main__phase__342select0__bit 888 ; else body start 889 ; phase0 := 0 890 0d1 1306 bcf phase0__byte,phase0__bit 891 ; else body end 892 ; if exp=` phase @ 0 ' single true and false skip delay=4 893 ; Other expression=`{ phase @ 0 }' delay=4 894 ; if { phase @ 0 } end 895 0d2 284a goto main__277loop__forever 896 ; loop_forever ... end 897 ; procedure main end 898 ; comment {DAC routines :} 899 900 ; procedure send_dac start 901 send_dac: 902 0032 send_dac__variables__base equ global__variables__bank0+18 903 0032 send_dac__bytes__base equ send_dac__variables__base+0 904 0034 send_dac__bits__base equ send_dac__variables__base+2 905 0002 send_dac__total__bytes equ 2 906 0032 send_dac__byte0 equ send_dac__bytes__base+0 907 0033 send_dac__byte1 equ send_dac__bytes__base+1 908 ; This procedure will output < byte0 > followed by < byte1 > to the 909 ; Digital to Analog converter . 910 ; dac_select := 0 911 0d3 1105 bcf dac_select__byte,dac_select__bit 912 ; call send_dac_byte {{ byte0 }} 913 0d4 0832 movf send_dac__byte0,w 914 0d5 00b4 movwf send_dac_byte__dac 915 0d6 20dc call send_dac_byte 916 ; call send_dac_byte {{ byte1 }} 917 0d7 0833 movf send_dac__byte1,w 918 0d8 00b4 movwf send_dac_byte__dac 919 0d9 20dc call send_dac_byte 920 ; dac_select := 1 921 0da 1505 bsf dac_select__byte,dac_select__bit 922 ; procedure send_dac end 923 0db 3400 retlw 0 924 925 ; procedure send_dac_byte start 926 send_dac_byte: 927 0034 send_dac_byte__variables__base equ global__variables__bank0+20 928 0034 send_dac_byte__bytes__base equ send_dac_byte__variables__base+0 929 0036 send_dac_byte__bits__base equ send_dac_byte__variables__base+2 930 0002 send_dac_byte__total__bytes equ 2 931 0034 send_dac_byte__dac equ send_dac_byte__bytes__base+0 932 0035 send_dac_byte__count equ send_dac_byte__bytes__base+1 933 ; `count_down count 8 ...' start 934 0dc 3008 movlw 8 935 0dd 00b5 movwf send_dac_byte__count 936 send_dac_byte__372_loop: 937 ; serial_data := dac @ 7 938 ; Alias variable for select dac @ 7 939 0034 send_dac_byte__dac__373select0 equ send_dac_byte__dac+0 940 0034 send_dac_byte__dac__373select0__byte equ send_dac_byte__dac+0 941 0007 send_dac_byte__dac__373select0__bit equ 7 942 0de 1fb4 btfss send_dac_byte__dac__373select0__byte,send_dac_byte__dac__373select0__bit 943 0df 1305 bcf serial_data__byte,serial_data__bit 944 0e0 1bb4 btfsc send_dac_byte__dac__373select0__byte,send_dac_byte__dac__373select0__bit 945 0e1 1705 bsf serial_data__byte,serial_data__bit 946 ; serial_clock := 1 947 0e2 1786 bsf serial_clock__byte,serial_clock__bit 948 ; dac := dac << 1 949 0e3 1003 bcf c___byte,c___bit 950 0e4 0db4 rlf send_dac_byte__dac,f 951 ; serial_clock := 0 952 0e5 1386 bcf serial_clock__byte,serial_clock__bit 953 0e6 0bb5 decfsz send_dac_byte__count,f 954 0e7 28de goto send_dac_byte__372_loop 955 send_dac_byte__372_done: 956 ; `count_down count 8 ...' end 957 ; procedure send_dac_byte end 958 0e8 3400 retlw 0 959 ; comment {The following procedures are used to send data back to the master :} 960 961 ; procedure send_byte start 962 send_byte: 963 0036 send_byte__variables__base equ global__variables__bank0+22 964 0036 send_byte__bytes__base equ send_byte__variables__base+0 965 0038 send_byte__bits__base equ send_byte__variables__base+2 966 0002 send_byte__total__bytes equ 2 967 0037 send_byte__389byte0 equ send_byte__bytes__base+1 968 0036 send_byte__character equ send_byte__bytes__base+0 969 ; This procedure will cause < character > to placed into 970 ; a ring buffer for transmission . 971 ; send_buffer ~~ {{ send_in_index }} := character 972 0e9 0836 movf send_byte__character,w 973 0ea 00b7 movwf send_byte__389byte0 974 0eb 3022 movlw LOW send_buffer 975 0ec 0720 addwf send_in_index,w 976 0ed 0084 movwf fsr___register 977 0ee 0837 movf send_byte__389byte0,w 978 0ef 1383 bcf irp___register,irp___bit 979 0f0 0080 movwf indf___register 980 ; send_in_index := send_in_index + 1 981 0f1 0aa0 incf send_in_index,f 982 ; if { send_in_index >= send_buffer_size } start 983 0f2 300a movlw 10 984 0f3 0220 subwf send_in_index,w 985 ; expression=`{ send_in_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 986 0f4 1803 btfsc c___byte,c___bit 987 ; if { send_in_index >= send_buffer_size } body start 988 ; send_in_index := 0 989 0f5 01a0 clrf send_in_index 990 ; if { send_in_index >= send_buffer_size } body end 991 ; if exp=` send_in_index >= send_buffer_size ' false skip delay=4 992 ; Other expression=`{ send_in_index >= send_buffer_size }' delay=4 993 ; if { send_in_index >= send_buffer_size } end 994 ; procedure send_byte end 995 0f6 3400 retlw 0 996 997 ; procedure send_crlf start 998 send_crlf: 999 0038 send_crlf__variables__base equ global__variables__bank0+24 1000 0038 send_crlf__bytes__base equ send_crlf__variables__base+0 1001 0038 send_crlf__bits__base equ send_crlf__variables__base+0 1002 0000 send_crlf__total__bytes equ 0 1003 ; arguments_none 1004 ; This procedure will output a carriage - return line - feed 1005 ; to the master . 1006 ; call send_byte {{ cr }} 1007 0f7 300d movlw 13 1008 0f8 00b6 movwf send_byte__character 1009 0f9 20e9 call send_byte 1010 ; call send_byte {{ lf }} 1011 0fa 300a movlw 10 1012 0fb 00b6 movwf send_byte__character 1013 0fc 20e9 call send_byte 1014 ; procedure send_crlf end 1015 0fd 3400 retlw 0 1016 1017 ; procedure send_octal start 1018 send_octal: 1019 0038 send_octal__variables__base equ global__variables__bank0+24 1020 0038 send_octal__bytes__base equ send_octal__variables__base+0 1021 003a send_octal__bits__base equ send_octal__variables__base+2 1022 0002 send_octal__total__bytes equ 2 1023 0039 send_octal__415byte0 equ send_octal__bytes__base+1 1024 0039 send_octal__414byte0 equ send_octal__bytes__base+1 1025 0038 send_octal__number equ send_octal__bytes__base+0 1026 ; This procedure will output < number > in octal to the tx port . 1027 ; Output the character in octal : 1028 ; call send_byte {{ {{ number >> 6 }} + 0c'0' }} 1029 0fe 0e38 swapf send_octal__number,w 1030 0ff 00b9 movwf send_octal__414byte0 1031 100 0cb9 rrf send_octal__414byte0,f 1032 101 0c39 rrf send_octal__414byte0,w 1033 102 3903 andlw 3 1034 103 3e30 addlw 48 1035 104 00b6 movwf send_byte__character 1036 105 20e9 call send_byte 1037 ; call send_byte {{ {{ {{ number >> 3 }} & 7 }} + 0c'0' }} 1038 106 0c38 rrf send_octal__number,w 1039 107 00b9 movwf send_octal__415byte0 1040 108 0cb9 rrf send_octal__415byte0,f 1041 109 0c39 rrf send_octal__415byte0,w 1042 10a 3907 andlw 7 1043 10b 3e30 addlw 48 1044 10c 00b6 movwf send_byte__character 1045 10d 20e9 call send_byte 1046 ; call send_byte {{ {{ number & 7 }} + 0c'0' }} 1047 10e 3007 movlw 7 1048 10f 0538 andwf send_octal__number,w 1049 110 3e30 addlw 48 1050 111 00b6 movwf send_byte__character 1051 112 20e9 call send_byte 1052 ; call send_byte {{ sp }} 1053 113 3020 movlw 32 1054 114 00b6 movwf send_byte__character 1055 115 20e9 call send_byte 1056 ; procedure send_octal end 1057 116 3400 retlw 0 1058 1059 ; procedure send_string start 1060 send_string: 1061 003a send_string__variables__base equ global__variables__bank0+26 1062 003a send_string__bytes__base equ send_string__variables__base+0 1063 003d send_string__bits__base equ send_string__variables__base+3 1064 0003 send_string__total__bytes equ 3 1065 003a send_string__message equ send_string__bytes__base+0 1066 ; This procedure will output < message > . 1067 003b send_string__size equ send_string__bytes__base+1 1068 003c send_string__index equ send_string__bytes__base+2 1069 ; index := 0 1070 117 01bc clrf send_string__index 1071 ; `while index < message . size ...' start 1072 send_string__430while__continue: 1073 118 018a clrf pclath___register 1074 119 083a movf send_string__message,w 1075 11a 200f call string___fetch 1076 11b 023c subwf send_string__index,w 1077 ; expression=` index < message . size ' exp_delay=4 true_delay=7 false_delay=2 true_size=8 false_size=1 1078 11c 1803 btfsc c___byte,c___bit 1079 11d 2926 goto send_string__430while__break 1080 ; call send_byte {{ message ~~ {{ index }} }} 1081 11e 0a3c incf send_string__index,w 1082 11f 073a addwf send_string__message,w 1083 120 018a clrf pclath___register 1084 121 200f call string___fetch 1085 122 00b6 movwf send_byte__character 1086 123 20e9 call send_byte 1087 ; index := index + 1 1088 124 0abc incf send_string__index,f 1089 125 2918 goto send_string__430while__continue 1090 ; if exp=` index < message . size ' false goto 1091 ; Other expression=` index < message . size ' delay=-1 1092 send_string__430while__break: 1093 ; `while index < message . size ...' end 1094 ; call send_byte {{ sp }} 1095 126 3020 movlw 32 1096 127 00b6 movwf send_byte__character 1097 128 20e9 call send_byte 1098 ; procedure send_string end 1099 129 3400 retlw 0 1100 1101 ; Register bank 0 used 29 bytes of 96 available bytes 1102 ; Register bank 1 used 0 bytes of 80 available bytes 1103 ; Register bank 2 used 0 bytes of 48 available bytes 1104 ; Register bank 3 used 0 bytes of 0 available bytes 1105 1106 end