1 radix dec 2 0020 global__variables__bank0 equ 32 3 00a0 global__variables__bank1 equ 160 4 0120 global__variables__bank2 equ 288 5 01f0 global__variables__bank3 equ 496 6 003d global__bit__variables__bank0 equ 61 7 00a0 global__bit__variables__bank1 equ 160 8 0120 global__bit__variables__bank2 equ 288 9 01f0 global__bit__variables__bank3 equ 496 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 0003 rp0___byte equ 3 17 0005 rp0___bit equ 5 18 0003 rp1___byte equ 3 19 0006 rp1___bit equ 6 20 0003 irp___byte equ 3 21 0007 irp___bit equ 7 22 0085 trisa___register equ 0x85 23 0086 trisb___register equ 0x86 24 0004 fsr___register equ 4 25 000a pclath___register equ 10 26 org 0 27 start: 28 000 0000 nop 29 001 0000 nop 30 002 0000 nop 31 003 2805 goto skip___interrupt 32 interrupt___vector: 33 004 0009 retfie 34 skip___interrupt: 35 ; Initialize A/D system to allow digital I/O 36 005 3003 movlw 3 37 006 009f movwf 31 38 ; Initialize TRIS registers 39 007 30af movlw 175 40 ; Switch from register bank 0 to register bank 1 (which contains trisa___register) 41 008 1683 bsf rp0___byte,rp0___bit 42 ; Register bank is now 1 43 009 0085 movwf trisa___register 44 00a 301e movlw 30 45 00b 0086 movwf trisb___register 46 00c 018a clrf pclath___register 47 ; Switch from register bank 1 to register bank 0 48 00d 1283 bcf rp0___byte,rp0___bit 49 ; Register bank is now 0 50 00e 2817 goto main 51 ; comment ############################################################################# 52 ; comment {} 53 ; comment {Copyright < c > 2002 by Wayne C . Gramlich .} 54 ; comment {All rights reserved .} 55 ; comment {} 56 ; comment {Permission to use , copy , modify , distribute , and sell this software} 57 ; comment {for any purpose is hereby granted without fee provided that the above} 58 ; comment {copyright notice and this permission are retained . The author makes} 59 ; comment {no representations about the suitability of this software for any purpose .} 60 ; comment {It is provided { as is } without express or implied warranty .} 61 ; comment {} 62 ; comment {This is chopper microcode for Wayne ' s motion CNC board at :} 63 ; comment {} 64 ; comment {http : / / web . gramlich . net / projects / cnc / motion / index . html} 65 ; comment {} 66 ; comment {for more details .} 67 ; comment {} 68 ; comment {Some pin assignments :} 69 ; comment {} 70 ; comment {No Name Kind Description} 71 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 72 ; comment {1 RA2 / AN2 / VREF Analog In Comparator2 Vin +} 73 ; comment {2 RA3 / AN3 / CMP1 Analog In Comparator1 Vin +} 74 ; comment {3 RA4 / TOCKI / CMP2 Digital Out Motor1B} 75 ; comment {4 RA5 / MCLR * / THV Digital In Motor1 Enable} 76 ; comment {4 ' RA5 / MCLR * / THV Digital Out Phase 0} 77 ; comment {5 VSS Ground Ground} 78 ; comment {6 RB0 / INT Digital In Phase 0} 79 ; comment {6 ' RB0 / INT Digital Out Motor1 Enable} 80 ; comment {7 RB1 / RX / DT Digital In Serial Input} 81 ; comment {8 RB2 / TX / CK Digital Out Serial Output} 82 ; comment {9 RB3 / CCP1 Digital In Phase 1} 83 ; comment {10 RB4 / PGM Digital In Phase 2} 84 ; comment {11 RB5 Digital Out Motor0A} 85 ; comment {12 RB6 / T1OSO / TICK1 Digital Out Motor0 Enable} 86 ; comment {13 RB7 / T1OSI Digital Out Motor0B} 87 ; comment {14 VDD Power + 5 Volts} 88 ; comment {15 RA6 / OSC2 / CLKOUT Digital Out Motor1A} 89 ; comment {16 RA7 / OSC1 / CLKIN Digital In Oscillator In} 90 ; comment {17 RA0 / AN0 Analog In Comparator1 Vin -} 91 ; comment {18 RA1 / AN1 Analog In Comparator2 Vin -} 92 ; comment {} 93 ; comment {The concept here is to implement most of an L297 in microcode} 94 ; comment {for a PIC16F628 . There is a slight difference in that the L297} 95 ; comment {uses a step and direction strategy whereas the code here uses a} 96 ; comment {` phase ' strategy using a half - stepping wave table .} 97 ; comment {} 98 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 99 ; comment {Inputs | Outputs} 100 ; comment {Phase2 Phase1 Phase0 | Motor0A Motor1A Motor0B Motor1B} 101 ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =} 102 ; comment {0 0 0 | 1 0 0 0} 103 ; comment {0 0 1 | 1 1 0 0} 104 ; comment {0 1 0 | 0 1 0 0} 105 ; comment {0 1 1 | 0 1 1 0} 106 ; comment {1 0 0 | 0 0 1 0} 107 ; comment {1 0 1 | 0 0 1 1} 108 ; comment {1 1 0 | 0 0 0 1} 109 ; comment {1 1 1 | 1 0 0 1} 110 ; comment {} 111 ; comment ############################################################################# 112 ; processor pic16f628 cp = off cpd = off lvp = off bowden = off mclre = off pwrte = off wdte = off fosc = ec 113 ; 16139=0x3f0b 8199=0x2007 114 __config 16139 115 2007 configuration___address equ 8199 116 ; constant clock_rate 20000000 117 1312d00 clock_rate equ 20000000 118 ; comment {Some character constants :} 119 ; constant sp 32 120 0020 sp equ 32 121 ; constant cr 13 122 000d cr equ 13 123 ; constant lf 10 124 000a lf equ 10 125 ; comment {Some register definitions :} 126 0001 tmr0 equ 1 127 0003 status equ 3 128 ; bind c status @ 0 129 0003 c equ status+0 130 0003 c__byte equ status+0 131 0000 c__bit equ 0 132 ; bind z status @ 2 133 0003 z equ status+0 134 0003 z__byte equ status+0 135 0002 z__bit equ 2 136 000b intcon equ 11 137 ; bind gie intcon @ 7 138 000b gie equ intcon+0 139 000b gie__byte equ intcon+0 140 0007 gie__bit equ 7 141 ; bind t0ie intcon @ 5 142 000b t0ie equ intcon+0 143 000b t0ie__byte equ intcon+0 144 0005 t0ie__bit equ 5 145 ; bind inte intcon @ 4 146 000b inte equ intcon+0 147 000b inte__byte equ intcon+0 148 0004 inte__bit equ 4 149 ; bind rbie intcon @ 3 150 000b rbie equ intcon+0 151 000b rbie__byte equ intcon+0 152 0003 rbie__bit equ 3 153 ; bind t0if intcon @ 2 154 000b t0if equ intcon+0 155 000b t0if__byte equ intcon+0 156 0002 t0if__bit equ 2 157 ; bind intf intcon @ 1 158 000b intf equ intcon+0 159 000b intf__byte equ intcon+0 160 0001 intf__bit equ 1 161 ; bind rbif intcon @ 0 162 000b rbif equ intcon+0 163 000b rbif__byte equ intcon+0 164 0000 rbif__bit equ 0 165 000c pir1 equ 12 166 ; bind eeif pir1 @ 7 167 000c eeif equ pir1+0 168 000c eeif__byte equ pir1+0 169 0007 eeif__bit equ 7 170 ; bind cmif pir1 @ 6 171 000c cmif equ pir1+0 172 000c cmif__byte equ pir1+0 173 0006 cmif__bit equ 6 174 ; bind rcif pir1 @ 5 175 000c rcif equ pir1+0 176 000c rcif__byte equ pir1+0 177 0005 rcif__bit equ 5 178 ; bind txif pir1 @ 4 179 000c txif equ pir1+0 180 000c txif__byte equ pir1+0 181 0004 txif__bit equ 4 182 ; bind ccp1if pir1 @ 2 183 000c ccp1if equ pir1+0 184 000c ccp1if__byte equ pir1+0 185 0002 ccp1if__bit equ 2 186 ; bind tmr2if pir1 @ 1 187 000c tmr2if equ pir1+0 188 000c tmr2if__byte equ pir1+0 189 0001 tmr2if__bit equ 1 190 ; bind tmr1if pir1 @ 0 191 000c tmr1if equ pir1+0 192 000c tmr1if__byte equ pir1+0 193 0000 tmr1if__bit equ 0 194 0018 rcsta equ 24 195 ; bind spen rcsta @ 7 196 0018 spen equ rcsta+0 197 0018 spen__byte equ rcsta+0 198 0007 spen__bit equ 7 199 ; bind rx9 rcsta @ 6 200 0018 rx9 equ rcsta+0 201 0018 rx9__byte equ rcsta+0 202 0006 rx9__bit equ 6 203 ; bind sren rcsta @ 5 204 0018 sren equ rcsta+0 205 0018 sren__byte equ rcsta+0 206 0005 sren__bit equ 5 207 ; bind cren rcsta @ 4 208 0018 cren equ rcsta+0 209 0018 cren__byte equ rcsta+0 210 0004 cren__bit equ 4 211 ; bind aden rcsta @ 3 212 0018 aden equ rcsta+0 213 0018 aden__byte equ rcsta+0 214 0003 aden__bit equ 3 215 ; bind ferr rcsta @ 2 216 0018 ferr equ rcsta+0 217 0018 ferr__byte equ rcsta+0 218 0002 ferr__bit equ 2 219 ; bind oerr rcsta @ 1 220 0018 oerr equ rcsta+0 221 0018 oerr__byte equ rcsta+0 222 0001 oerr__bit equ 1 223 ; bind rx9d rcsta @ 0 224 0018 rx9d equ rcsta+0 225 0018 rx9d__byte equ rcsta+0 226 0000 rx9d__bit equ 0 227 0019 txreg equ 25 228 001a rcreg equ 26 229 ; comment {Comparator module control :} 230 001f cmcon equ 31 231 ; bind c2out cmcon @ 7 232 001f c2out equ cmcon+0 233 001f c2out__byte equ cmcon+0 234 0007 c2out__bit equ 7 235 ; bind c1out cmcon @ 6 236 001f c1out equ cmcon+0 237 001f c1out__byte equ cmcon+0 238 0006 c1out__bit equ 6 239 ; bind c2inv cmcon @ 5 240 001f c2inv equ cmcon+0 241 001f c2inv__byte equ cmcon+0 242 0005 c2inv__bit equ 5 243 ; bind c1inv cmcon @ 4 244 001f c1inv equ cmcon+0 245 001f c1inv__byte equ cmcon+0 246 0004 c1inv__bit equ 4 247 ; bind cis cmcon @ 3 248 001f cis equ cmcon+0 249 001f cis__byte equ cmcon+0 250 0003 cis__bit equ 3 251 ; bind cm2 cmcon @ 2 252 001f cm2 equ cmcon+0 253 001f cm2__byte equ cmcon+0 254 0002 cm2__bit equ 2 255 ; bind cm1 cmcon @ 1 256 001f cm1 equ cmcon+0 257 001f cm1__byte equ cmcon+0 258 0001 cm1__bit equ 1 259 ; bind cm0 cmcon @ 0 260 001f cm0 equ cmcon+0 261 001f cm0__byte equ cmcon+0 262 0000 cm0__bit equ 0 263 0081 option equ 129 264 ; bind t0cs option @ 5 265 0081 t0cs equ option+0 266 0081 t0cs__byte equ option+0 267 0005 t0cs__bit equ 5 268 ; bind t0se option @ 4 269 0081 t0se equ option+0 270 0081 t0se__byte equ option+0 271 0004 t0se__bit equ 4 272 ; bind psa option @ 3 273 0081 psa equ option+0 274 0081 psa__byte equ option+0 275 0003 psa__bit equ 3 276 ; bind ps2 option @ 2 277 0081 ps2 equ option+0 278 0081 ps2__byte equ option+0 279 0002 ps2__bit equ 2 280 ; bind ps1 option @ 1 281 0081 ps1 equ option+0 282 0081 ps1__byte equ option+0 283 0001 ps1__bit equ 1 284 ; bind ps0 option @ 0 285 0081 ps0 equ option+0 286 0081 ps0__byte equ option+0 287 0000 ps0__bit equ 0 288 008c pie1 equ 140 289 ; bind eeie pie1 @ 7 290 008c eeie equ pie1+0 291 008c eeie__byte equ pie1+0 292 0007 eeie__bit equ 7 293 ; bind cmie pie1 @ 6 294 008c cmie equ pie1+0 295 008c cmie__byte equ pie1+0 296 0006 cmie__bit equ 6 297 ; bind rcie pie1 @ 5 298 008c rcie equ pie1+0 299 008c rcie__byte equ pie1+0 300 0005 rcie__bit equ 5 301 ; bind txie pie1 @ 4 302 008c txie equ pie1+0 303 008c txie__byte equ pie1+0 304 0004 txie__bit equ 4 305 ; bind ccp1ie pie1 @ 2 306 008c ccp1ie equ pie1+0 307 008c ccp1ie__byte equ pie1+0 308 0002 ccp1ie__bit equ 2 309 ; bind tmr2ie pie1 @ 1 310 008c tmr2ie equ pie1+0 311 008c tmr2ie__byte equ pie1+0 312 0001 tmr2ie__bit equ 1 313 ; bind tmr1ie pie1 @ 0 314 008c tmr1ie equ pie1+0 315 008c tmr1ie__byte equ pie1+0 316 0000 tmr1ie__bit equ 0 317 0098 txsta equ 152 318 ; bind tx9 txsta @ 6 319 0098 tx9 equ txsta+0 320 0098 tx9__byte equ txsta+0 321 0006 tx9__bit equ 6 322 ; bind txen txsta @ 5 323 0098 txen equ txsta+0 324 0098 txen__byte equ txsta+0 325 0005 txen__bit equ 5 326 ; bind sync txsta @ 4 327 0098 sync equ txsta+0 328 0098 sync__byte equ txsta+0 329 0004 sync__bit equ 4 330 ; bind brgh txsta @ 2 331 0098 brgh equ txsta+0 332 0098 brgh__byte equ txsta+0 333 0002 brgh__bit equ 2 334 ; bind trmt txsta @ 1 335 0098 trmt equ txsta+0 336 0098 trmt__byte equ txsta+0 337 0001 trmt__bit equ 1 338 ; bind tx9d txsta @ 0 339 0098 tx9d equ txsta+0 340 0098 tx9d__byte equ txsta+0 341 0000 tx9d__bit equ 0 342 0099 spbrg equ 153 343 ; comment {Some port , bit , and pin definitions :} 344 ; comment {Port A pin assignments :} 345 ; comment {RA0 : Comparator1 Vin -} 346 ; comment {RA1 : Comparator2 Vin -} 347 ; comment {RA2 : Comparator2 Vin +} 348 ; comment {RA3 : Comparator1 Vin +} 349 ; comment {RA4 : Motor1B} 350 ; comment {RA5 : Phase 0} 351 ; comment {RA6 : Motor1A} 352 ; comment {RA7 : Oscillator In} 353 ; constant comp1m_bit 0 354 0000 comp1m_bit equ 0 355 ; constant comp2m_bit 1 356 0001 comp2m_bit equ 1 357 ; constant comp2p_bit 2 358 0002 comp2p_bit equ 2 359 ; constant comp1p_bit 3 360 0003 comp1p_bit equ 3 361 ; constant motor1b_bit 4 362 0004 motor1b_bit equ 4 363 ; constant phase0_bit 5 364 0005 phase0_bit equ 5 365 ; constant motor1a_bit 6 366 0006 motor1a_bit equ 6 367 ; constant osc_in_bit 7 368 0007 osc_in_bit equ 7 369 0005 porta equ 5 370 0005 comp1m__byte equ 5 371 0000 comp1m__bit equ 0 372 0005 comp2m__byte equ 5 373 0001 comp2m__bit equ 1 374 0005 comp2p__byte equ 5 375 0002 comp2p__bit equ 2 376 0005 comp1p__byte equ 5 377 0003 comp1p__bit equ 3 378 0005 motor1b__byte equ 5 379 0004 motor1b__bit equ 4 380 0005 phase0__byte equ 5 381 0005 phase0__bit equ 5 382 0005 motor1a__byte equ 5 383 0006 motor1a__bit equ 6 384 0005 osc_in__byte equ 5 385 0007 osc_in__bit equ 7 386 ; comment {Port B pin assignments :} 387 ; comment {RB0 : Motor1 Enable} 388 ; comment {RB1 : Serial Input < RX >} 389 ; comment {RB2 : Serial Output < TX >} 390 ; comment {RB3 : Phase 1} 391 ; comment {RB4 : Phase 2} 392 ; comment {RB5 : Motor0A} 393 ; comment {RB6 : Motor0 Enable} 394 ; comment {RB7 : Motor0B} 395 ; constant motor1e_bit 0 396 0000 motor1e_bit equ 0 397 ; constant rx_bit 1 398 0001 rx_bit equ 1 399 ; constant tx_bit 2 400 0002 tx_bit equ 2 401 ; constant phase1_bit 3 402 0003 phase1_bit equ 3 403 ; constant phase2_bit 4 404 0004 phase2_bit equ 4 405 ; constant motor0a_bit 5 406 0005 motor0a_bit equ 5 407 ; constant motor0e_bit 6 408 0006 motor0e_bit equ 6 409 ; constant motor0b_bit 7 410 0007 motor0b_bit equ 7 411 0006 portb equ 6 412 0006 motor1e__byte equ 6 413 0000 motor1e__bit equ 0 414 ; comment {When using the USART , both the TX and RX pins must be set to input :} 415 0006 tx_pin__byte equ 6 416 0002 tx_pin__bit equ 2 417 0006 rx_pin__byte equ 6 418 0001 rx_pin__bit equ 1 419 0006 phase1__byte equ 6 420 0003 phase1__bit equ 3 421 0006 phase2__byte equ 6 422 0004 phase2__bit equ 4 423 0006 motor0a__byte equ 6 424 0005 motor0a__bit equ 5 425 0006 motor0e__byte equ 6 426 0006 motor0e__bit equ 6 427 0006 motor0b__byte equ 6 428 0007 motor0b__bit equ 7 429 0020 porta_shadow equ global__variables__bank0+0 430 0021 portb_shadow equ global__variables__bank0+1 431 ; string_constants Start 432 string___fetch: 433 00f 0082 movwf pcl___register 434 ; hello_string = 0s'Hello' 435 0000 hello_string___string equ 0 436 hello_string: 437 010 0782 addwf pcl___register,f 438 ; Length = 5 439 011 3405 retlw 5 440 ; `Hello' 441 012 3448 retlw 72 442 013 3465 retlw 101 443 014 346c retlw 108 444 015 346c retlw 108 445 016 346f retlw 111 446 ; string__constants End 447 0022 send_in_index equ global__variables__bank0+2 448 0023 send_out_index equ global__variables__bank0+3 449 ; constant send_buffer_size 10 450 000a send_buffer_size equ 10 451 0024 send_buffer equ global__variables__bank0+4 452 453 ; procedure main start 454 main: 455 002e main__variables__base equ global__variables__bank0+14 456 002e main__bytes__base equ main__variables__base+0 457 0033 main__bits__base equ main__variables__base+5 458 0005 main__total__bytes equ 5 459 0032 main__343byte0 equ main__bytes__base+4 460 ; arguments_none 461 002e main__char equ main__bytes__base+0 462 002f main__number equ main__bytes__base+1 463 0030 main__new_phase equ main__bytes__base+2 464 0031 main__phase equ main__bytes__base+3 465 ; Get all interrupts turned off : 466 ; intcon := 0 467 017 018b clrf intcon 468 ; pie1 := 0 469 ; Switch from register bank 0 to register bank 1 (which contains pie1) 470 018 1683 bsf rp0___byte,rp0___bit 471 ; Register bank is now 1 472 019 018c clrf pie1 473 ; pir1 := 0 474 ; Switch from register bank 1 to register bank 0 (which contains pir1) 475 01a 1283 bcf rp0___byte,rp0___bit 476 ; Register bank is now 0 477 01b 018c clrf pir1 478 ; Initialize UART : 479 ; Prescaler = low : 480 ; brgh := 0 481 ; Prescaler = high 482 ; brgh := 1 483 ; Switch from register bank 0 to register bank 1 (which contains brgh__byte) 484 01c 1683 bsf rp0___byte,rp0___bit 485 ; Register bank is now 1 486 01d 1518 bsf brgh__byte,brgh__bit 487 ; Baud rate = 2400 baud : 488 ; spbrg := 129 489 ; Baud rate = 115200 baud : 490 ; spbrg := 10 491 01e 300a movlw 10 492 01f 0099 movwf spbrg 493 ; Asynchronous mode : 494 ; sync := 0 495 020 1218 bcf sync__byte,sync__bit 496 ; 8 - bit mode : 497 ; tx9 := 0 498 021 1318 bcf tx9__byte,tx9__bit 499 ; Serial Port Enable : 500 ; spen := 1 501 ; Switch from register bank 1 to register bank 0 (which contains spen__byte) 502 022 1283 bcf rp0___byte,rp0___bit 503 ; Register bank is now 0 504 023 1798 bsf spen__byte,spen__bit 505 ; Keep interrupts off : 506 ; txie := 0 507 ; Switch from register bank 0 to register bank 1 (which contains txie__byte) 508 024 1683 bsf rp0___byte,rp0___bit 509 ; Register bank is now 1 510 025 120c bcf txie__byte,txie__bit 511 ; Clear out an previous character . 512 ; txif := 0 513 ; Switch from register bank 1 to register bank 0 (which contains txif__byte) 514 026 1283 bcf rp0___byte,rp0___bit 515 ; Register bank is now 0 516 027 120c bcf txif__byte,txif__bit 517 ; Enable the transmitter : 518 ; txen := 1 519 ; Switch from register bank 0 to register bank 1 (which contains txen__byte) 520 028 1683 bsf rp0___byte,rp0___bit 521 ; Register bank is now 1 522 029 1698 bsf txen__byte,txen__bit 523 ; Enable the receiver : 524 ; Keep inerrupts off : 525 ; rcie := 0 526 02a 128c bcf rcie__byte,rcie__bit 527 ; Enable continuous reception : 528 ; cren := 1 529 ; Switch from register bank 1 to register bank 0 (which contains cren__byte) 530 02b 1283 bcf rp0___byte,rp0___bit 531 ; Register bank is now 0 532 02c 1618 bsf cren__byte,cren__bit 533 ; Enable single receptions : 534 ; sren := 1 535 02d 1698 bsf sren__byte,sren__bit 536 ; Disable address 537 ; aden := 0 538 02e 1198 bcf aden__byte,aden__bit 539 ; Initialize the comparator module : 540 ; Two independent comparators : 541 ; cmcon := 4 542 02f 3004 movlw 4 543 030 009f movwf cmcon 544 ; Initialize the timer module : 545 ; t0cs := 0 546 ; Switch from register bank 0 to register bank 1 (which contains t0cs__byte) 547 031 1683 bsf rp0___byte,rp0___bit 548 ; Register bank is now 1 549 032 1281 bcf t0cs__byte,t0cs__bit 550 ; psa := 0 551 033 1181 bcf psa__byte,psa__bit 552 ; ps2 := 1 553 034 1501 bsf ps2__byte,ps2__bit 554 ; ps1 := 1 555 035 1481 bsf ps1__byte,ps1__bit 556 ; ps0 := 1 557 036 1401 bsf ps0__byte,ps0__bit 558 ; Initialize ring buffer : 559 ; send_in_index := 0 560 ; Switch from register bank 1 to register bank 0 (which contains send_in_index) 561 037 1283 bcf rp0___byte,rp0___bit 562 ; Register bank is now 0 563 038 01a2 clrf send_in_index 564 ; send_out_index := 0 565 039 01a3 clrf send_out_index 566 ; Print out a welcome message : 567 ; call send_string < hello_string > 568 ; call send_crlf < > 569 ; A little initialization : 570 ; number := 0 571 03a 01af clrf main__number 572 ; phase := 0 573 03b 01b1 clrf main__phase 574 ; call set_prescale {{ 3 }} 575 03c 3003 movlw 3 576 03d 00b3 movwf set_prescale__prescale 577 03e 2098 call set_prescale 578 ; call set_phase {{ 0 }} 579 03f 01b5 clrf set_phase__phase 580 040 20a4 call set_phase 581 ; Main loop 582 ; loop_forever ... start 583 main__297loop__forever: 584 ; Do the chopping : 585 ; if { t0if } start 586 ; expression=`{ t0if }' exp_delay=0 true_delay=5 false_delay=0 true_size=5 false_size=0 587 041 1d0b btfss t0if__byte,t0if__bit 588 042 2848 goto label299__0end 589 ; if { t0if } body start 590 ; t0if := 0 591 043 110b bcf t0if__byte,t0if__bit 592 ; porta := porta_shadow 593 044 0820 movf porta_shadow,w 594 045 0085 movwf porta 595 ; portb := portb_shadow 596 046 0821 movf portb_shadow,w 597 047 0086 movwf portb 598 ; if { t0if } body end 599 label299__0end: 600 ; if exp=`t0if' empty false 601 ; Other expression=`{ t0if }' delay=-1 602 ; if { t0if } end 603 ; if { ! c1out } start 604 ; expression=`c1out' exp_delay=0 true_delay=0 false_delay=2 true_size=0 false_size=2 605 048 1b1f btfsc c1out__byte,c1out__bit 606 049 284c goto label304__0end 607 ; if { ! c1out } body start 608 ; motor0a := 0 609 04a 1286 bcf motor0a__byte,motor0a__bit 610 ; motor0b := 0 611 04b 1386 bcf motor0b__byte,motor0b__bit 612 ; if { ! c1out } body end 613 label304__0end: 614 ; if exp=`c1out' empty true 615 ; Other expression=`c1out' delay=-1 616 ; if { ! c1out } end 617 ; if { ! c2out } start 618 ; expression=`c2out' exp_delay=0 true_delay=0 false_delay=2 true_size=0 false_size=2 619 04c 1b9f btfsc c2out__byte,c2out__bit 620 04d 2850 goto label308__0end 621 ; if { ! c2out } body start 622 ; motor1a := 0 623 04e 1305 bcf motor1a__byte,motor1a__bit 624 ; motor1b := 0 625 04f 1205 bcf motor1b__byte,motor1b__bit 626 ; if { ! c2out } body end 627 label308__0end: 628 ; if exp=`c2out' empty true 629 ; Other expression=`c2out' delay=-1 630 ; if { ! c2out } end 631 ; See whether we can transmit a character : 632 ; if { send_in_index != send_out_index && txif } start 633 050 0822 movf send_in_index,w 634 051 0223 subwf send_out_index,w 635 ; expression=`send_in_index != send_out_index' exp_delay=2 true_delay=-1 false_delay=2 true_size=13 false_size=1 636 052 1903 btfsc z___byte,z___bit 637 053 2861 goto and314__0false 638 ; expression=`txif' exp_delay=0 true_delay=11 false_delay=0 true_size=11 false_size=0 639 054 1e0c btfss txif__byte,txif__bit 640 055 2861 goto label314__1end 641 and314__0true: 642 ; if { send_in_index != send_out_index && txif } body start 643 ; txreg := send_buffer ~~ {{ send_out_index }} 644 056 3024 movlw LOW send_buffer 645 057 0723 addwf send_out_index,w 646 058 0084 movwf fsr___register 647 059 1383 bcf irp___register,irp___bit 648 05a 0800 movf indf___register,w 649 05b 0099 movwf txreg 650 ; send_out_index := send_out_index + 1 651 05c 0aa3 incf send_out_index,f 652 ; if { send_out_index >= send_buffer_size } start 653 05d 300a movlw 10 654 05e 0223 subwf send_out_index,w 655 ; expression=`{ send_out_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 656 05f 1803 btfsc c___byte,c___bit 657 ; if { send_out_index >= send_buffer_size } body start 658 ; send_out_index := 0 659 060 01a3 clrf send_out_index 660 ; if { send_out_index >= send_buffer_size } body end 661 ; if exp=` send_out_index >= send_buffer_size ' false skip delay=4 662 ; Other expression=`{ send_out_index >= send_buffer_size }' delay=4 663 ; if { send_out_index >= send_buffer_size } end 664 ; if { send_in_index != send_out_index && txif } body end 665 label314__1end: 666 ; if exp=`txif' empty false 667 ; Other expression=`txif' delay=-1 668 ; if exp=`send_in_index != send_out_index' false goto 669 ; Other expression=`send_in_index != send_out_index' delay=-1 670 and314__0false: 671 and314__0end: 672 ; if { send_in_index != send_out_index && txif } end 673 ; Read the phase : 674 ; new_phase := 0 675 061 01b0 clrf main__new_phase 676 ; if { phase2 } start 677 ; expression=`{ phase2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 678 062 1a06 btfsc phase2__byte,phase2__bit 679 ; if { phase2 } body start 680 ; new_phase @ 2 := 1 681 ; Select new_phase @ 2 682 0030 main__new_phase__325select0 equ main__new_phase+0 683 0030 main__new_phase__325select0__byte equ main__new_phase+0 684 0002 main__new_phase__325select0__bit equ 2 685 063 1530 bsf main__new_phase__325select0__byte,main__new_phase__325select0__bit 686 ; if { phase2 } body end 687 ; if exp=`phase2' false skip delay=2 688 ; Other expression=`{ phase2 }' delay=2 689 ; if { phase2 } end 690 ; if { phase1 } start 691 ; expression=`{ phase1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 692 064 1986 btfsc phase1__byte,phase1__bit 693 ; if { phase1 } body start 694 ; new_phase @ 1 := 1 695 ; Select new_phase @ 1 696 0030 main__new_phase__328select0 equ main__new_phase+0 697 0030 main__new_phase__328select0__byte equ main__new_phase+0 698 0001 main__new_phase__328select0__bit equ 1 699 065 14b0 bsf main__new_phase__328select0__byte,main__new_phase__328select0__bit 700 ; if { phase1 } body end 701 ; if exp=`phase1' false skip delay=2 702 ; Other expression=`{ phase1 }' delay=2 703 ; if { phase1 } end 704 ; if { phase0 } start 705 ; expression=`{ phase0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 706 066 1a85 btfsc phase0__byte,phase0__bit 707 ; if { phase0 } body start 708 ; new_phase @ 0 := 1 709 ; Select new_phase @ 0 710 0030 main__new_phase__331select0 equ main__new_phase+0 711 0030 main__new_phase__331select0__byte equ main__new_phase+0 712 0000 main__new_phase__331select0__bit equ 0 713 067 1430 bsf main__new_phase__331select0__byte,main__new_phase__331select0__bit 714 ; if { phase0 } body end 715 ; if exp=`phase0' false skip delay=2 716 ; Other expression=`{ phase0 }' delay=2 717 ; if { phase0 } end 718 ; if { phase != new_phase } start 719 068 0831 movf main__phase,w 720 069 0230 subwf main__new_phase,w 721 ; expression=`{ phase != new_phase }' exp_delay=2 true_delay=3 false_delay=0 true_size=5 false_size=0 722 06a 1903 btfsc z___byte,z___bit 723 06b 2871 goto label333__0end 724 ; if { phase != new_phase } body start 725 ; call set_phase {{ new_phase }} 726 06c 0830 movf main__new_phase,w 727 06d 00b5 movwf set_phase__phase 728 06e 20a4 call set_phase 729 ; phase := new_phase 730 06f 0830 movf main__new_phase,w 731 070 00b1 movwf main__phase 732 ; if { phase != new_phase } body end 733 label333__0end: 734 ; if exp=` phase != new_phase ' empty false 735 ; Other expression=`{ phase != new_phase }' delay=-1 736 ; if { phase != new_phase } end 737 ; See whether we ' ve got a character : 738 ; if { rcif } start 739 ; expression=`{ rcif }' exp_delay=0 true_delay=-1 false_delay=0 true_size=36 false_size=0 740 071 1e8c btfss rcif__byte,rcif__bit 741 072 2897 goto label339__0end 742 ; if { rcif } body start 743 ; char := rcreg 744 073 081a movf rcreg,w 745 074 00ae movwf main__char 746 ; call send_byte < char > 747 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } start 748 075 3030 movlw 48 749 076 022e subwf main__char,w 750 ; expression=`0c'0' <= char' exp_delay=2 true_delay=-1 false_delay=1 true_size=30 false_size=1 751 077 1c03 btfss c___byte,c___bit 752 078 2886 goto and342__0false 753 079 3038 movlw 56 754 07a 022e subwf main__char,w 755 ; expression=`char <= 0c'7'' exp_delay=2 true_delay=8 false_delay=-1 true_size=8 false_size=17 756 07b 1803 btfsc c___byte,c___bit 757 07c 2886 goto label342__1false 758 label342__1true: 759 and342__0true: 760 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body start 761 ; number := {{ number << 3 }} + char - 0c'0' 762 07d 0d2f rlf main__number,w 763 07e 00b2 movwf main__343byte0 764 07f 0db2 rlf main__343byte0,f 765 080 0d32 rlf main__343byte0,w 766 081 39f8 andlw 248 767 082 072e addwf main__char,w 768 083 3ed0 addlw 208 769 084 00af movwf main__number 770 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } body end 771 085 2897 goto label342__1end 772 label342__1false: 773 and342__0false: 774 086 3050 movlw 80 775 087 022e subwf main__char,w 776 ; expression=`{ char = 0c'P' }' exp_delay=2 true_delay=-1 false_delay=-1 true_size=4 false_size=8 777 088 1d03 btfss z___byte,z___bit 778 089 288f goto label344__0false 779 label344__0true: 780 ; else_if { char = 0c'P' } body start 781 ; call send_octal {{ phase }} 782 08a 0831 movf main__phase,w 783 08b 00b8 movwf send_octal__number 784 08c 20f4 call send_octal 785 ; call send_crlf {{ }} 786 08d 20ed call send_crlf 787 ; else_if { char = 0c'P' } body end 788 08e 2897 goto label344__0end 789 label344__0false: 790 08f 3063 movlw 99 791 090 022e subwf main__char,w 792 ; expression=`{ char = 0c'c' }' exp_delay=2 true_delay=1 false_delay=0 true_size=3 false_size=0 793 091 1d03 btfss z___byte,z___bit 794 092 2896 goto label347__0end 795 ; else_if { char = 0c'c' } body start 796 ; call set_prescale {{ number }} 797 093 082f movf main__number,w 798 094 00b3 movwf set_prescale__prescale 799 095 2098 call set_prescale 800 ; call send_crlf < > 801 ; number := 0 802 ; 1 instructions found for sharing 803 label347__0end: 804 ; if exp=` char = 0c'c' ' empty false 805 ; Other expression=`{ char = 0c'c' }' delay=-1 806 ; 1 shared instructions follow 807 096 01af clrf main__number 808 ; if exp=` char = 0c'P' ' generic 809 label344__0end: 810 ; Other expression=`{ char = 0c'P' }' delay=-1 811 ; if exp=`char <= 0c'7'' generic 812 label342__1end: 813 ; Other expression=`char <= 0c'7'' delay=-1 814 ; if exp=`0c'0' <= char' false goto 815 ; Other expression=`0c'0' <= char' delay=-1 816 and342__0end: 817 ; if { {{ 0c'0' <= char && char <= 0c'7' }} } end 818 ; if { rcif } body end 819 label339__0end: 820 ; if exp=`rcif' empty false 821 ; Other expression=`{ rcif }' delay=-1 822 ; if { rcif } end 823 097 2841 goto main__297loop__forever 824 ; loop_forever ... end 825 ; procedure main end 826 827 ; procedure set_prescale start 828 set_prescale: 829 0033 set_prescale__variables__base equ global__variables__bank0+19 830 0033 set_prescale__bytes__base equ set_prescale__variables__base+0 831 0035 set_prescale__bits__base equ set_prescale__variables__base+2 832 0002 set_prescale__total__bytes equ 2 833 0034 set_prescale__364byte0 equ set_prescale__bytes__base+1 834 0033 set_prescale__prescale equ set_prescale__bytes__base+0 835 ; option := {{ option & 0xf8 }} | {{ prescale & 7 }} 836 098 30f8 movlw 248 837 ; Switch from register bank 0 to register bank 1 (which contains option) 838 099 1683 bsf rp0___byte,rp0___bit 839 ; Register bank is now 1 840 09a 0501 andwf option,w 841 ; Switch from register bank 1 to register bank 0 (which contains set_prescale__364byte0) 842 09b 1283 bcf rp0___byte,rp0___bit 843 ; Register bank is now 0 844 09c 00b4 movwf set_prescale__364byte0 845 09d 3007 movlw 7 846 09e 0533 andwf set_prescale__prescale,w 847 09f 0434 iorwf set_prescale__364byte0,w 848 ; Switch from register bank 0 to register bank 1 (which contains option) 849 0a0 1683 bsf rp0___byte,rp0___bit 850 ; Register bank is now 1 851 0a1 0081 movwf option 852 ; procedure set_prescale end 853 ; Switch from register bank 1 to register bank 0 854 0a2 1283 bcf rp0___byte,rp0___bit 855 ; Register bank is now 0 856 0a3 3400 retlw 0 857 858 ; procedure set_phase start 859 set_phase: 860 0035 set_phase__variables__base equ global__variables__bank0+21 861 0035 set_phase__bytes__base equ set_phase__variables__base+0 862 0036 set_phase__bits__base equ set_phase__variables__base+1 863 0001 set_phase__total__bytes equ 1 864 0035 set_phase__phase equ set_phase__bytes__base+0 865 ; This procedure will set the phase of the : 866 ; switch { phase & 7 } 867 0a4 3000 movlw HIGH switch__372block_start 868 0a5 008a movwf pclath___register 869 0a6 3007 movlw 7 870 0a7 0535 andwf set_phase__phase,w 871 ; case 0 872 ; case 1 873 ; case 2 874 ; case 3 875 ; case 4 876 ; case 5 877 ; case 6 878 ; case 7 879 switch__372block_start: 880 0a8 0782 addwf pcl___register,f 881 0a9 28b1 goto switch__372block373 882 0aa 28b6 goto switch__372block379 883 0ab 28bb goto switch__372block385 884 0ac 28c0 goto switch__372block391 885 0ad 28c5 goto switch__372block397 886 0ae 28ca goto switch__372block403 887 0af 28cf goto switch__372block409 888 0b0 28d4 goto switch__372block415 889 switch__372block_end: 890 ; switch_check 372 switch__372block_start switch__372block_end 891 switch__372block373: 892 ; motor0a := 1 893 0b1 1686 bsf motor0a__byte,motor0a__bit 894 ; motor1a := 0 895 0b2 1305 bcf motor1a__byte,motor1a__bit 896 ; motor0b := 0 897 0b3 1386 bcf motor0b__byte,motor0b__bit 898 ; motor1b := 0 899 0b4 1205 bcf motor1b__byte,motor1b__bit 900 0b5 28d8 goto switch__372end 901 switch__372block379: 902 ; motor0a := 1 903 0b6 1686 bsf motor0a__byte,motor0a__bit 904 ; motor1a := 1 905 0b7 1705 bsf motor1a__byte,motor1a__bit 906 ; motor0b := 0 907 0b8 1386 bcf motor0b__byte,motor0b__bit 908 ; motor1b := 0 909 0b9 1205 bcf motor1b__byte,motor1b__bit 910 0ba 28d8 goto switch__372end 911 switch__372block385: 912 ; motor0a := 0 913 0bb 1286 bcf motor0a__byte,motor0a__bit 914 ; motor1a := 1 915 0bc 1705 bsf motor1a__byte,motor1a__bit 916 ; motor0b := 0 917 0bd 1386 bcf motor0b__byte,motor0b__bit 918 ; motor1b := 0 919 0be 1205 bcf motor1b__byte,motor1b__bit 920 0bf 28d8 goto switch__372end 921 switch__372block391: 922 ; motor0a := 0 923 0c0 1286 bcf motor0a__byte,motor0a__bit 924 ; motor1a := 1 925 0c1 1705 bsf motor1a__byte,motor1a__bit 926 ; motor0b := 1 927 0c2 1786 bsf motor0b__byte,motor0b__bit 928 ; motor1b := 0 929 0c3 1205 bcf motor1b__byte,motor1b__bit 930 0c4 28d8 goto switch__372end 931 switch__372block397: 932 ; motor0a := 0 933 0c5 1286 bcf motor0a__byte,motor0a__bit 934 ; motor1a := 0 935 0c6 1305 bcf motor1a__byte,motor1a__bit 936 ; motor0b := 1 937 0c7 1786 bsf motor0b__byte,motor0b__bit 938 ; motor1b := 0 939 0c8 1205 bcf motor1b__byte,motor1b__bit 940 0c9 28d8 goto switch__372end 941 switch__372block403: 942 ; motor0a := 0 943 0ca 1286 bcf motor0a__byte,motor0a__bit 944 ; motor1a := 0 945 0cb 1305 bcf motor1a__byte,motor1a__bit 946 ; motor0b := 1 947 0cc 1786 bsf motor0b__byte,motor0b__bit 948 ; motor1b := 1 949 0cd 1605 bsf motor1b__byte,motor1b__bit 950 0ce 28d8 goto switch__372end 951 switch__372block409: 952 ; motor0a := 0 953 0cf 1286 bcf motor0a__byte,motor0a__bit 954 ; motor1a := 0 955 0d0 1305 bcf motor1a__byte,motor1a__bit 956 ; motor0b := 0 957 0d1 1386 bcf motor0b__byte,motor0b__bit 958 ; motor1b := 1 959 0d2 1605 bsf motor1b__byte,motor1b__bit 960 0d3 28d8 goto switch__372end 961 switch__372block415: 962 ; motor0a := 1 963 0d4 1686 bsf motor0a__byte,motor0a__bit 964 ; motor1a := 0 965 0d5 1305 bcf motor1a__byte,motor1a__bit 966 ; motor0b := 0 967 0d6 1386 bcf motor0b__byte,motor0b__bit 968 ; motor1b := 1 969 0d7 1605 bsf motor1b__byte,motor1b__bit 970 switch__372end: 971 ; motor0e := 1 972 0d8 1706 bsf motor0e__byte,motor0e__bit 973 ; motor1e := 1 974 0d9 1406 bsf motor1e__byte,motor1e__bit 975 ; porta_shadow := porta 976 0da 0805 movf porta,w 977 0db 00a0 movwf porta_shadow 978 ; portb_shadow := portb 979 0dc 0806 movf portb,w 980 0dd 00a1 movwf portb_shadow 981 ; procedure set_phase end 982 0de 3400 retlw 0 983 ; comment {The following procedures are used to send data back to the master :} 984 985 ; procedure send_byte start 986 send_byte: 987 0036 send_byte__variables__base equ global__variables__bank0+22 988 0036 send_byte__bytes__base equ send_byte__variables__base+0 989 0038 send_byte__bits__base equ send_byte__variables__base+2 990 0002 send_byte__total__bytes equ 2 991 0037 send_byte__437byte0 equ send_byte__bytes__base+1 992 0036 send_byte__character equ send_byte__bytes__base+0 993 ; This procedure will cause < character > to placed into 994 ; a ring buffer for transmission . 995 ; send_buffer ~~ {{ send_in_index }} := character 996 0df 0836 movf send_byte__character,w 997 0e0 00b7 movwf send_byte__437byte0 998 0e1 3024 movlw LOW send_buffer 999 0e2 0722 addwf send_in_index,w 1000 0e3 0084 movwf fsr___register 1001 0e4 0837 movf send_byte__437byte0,w 1002 0e5 1383 bcf irp___register,irp___bit 1003 0e6 0080 movwf indf___register 1004 ; send_in_index := send_in_index + 1 1005 0e7 0aa2 incf send_in_index,f 1006 ; if { send_in_index >= send_buffer_size } start 1007 0e8 300a movlw 10 1008 0e9 0222 subwf send_in_index,w 1009 ; expression=`{ send_in_index >= send_buffer_size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1010 0ea 1803 btfsc c___byte,c___bit 1011 ; if { send_in_index >= send_buffer_size } body start 1012 ; send_in_index := 0 1013 0eb 01a2 clrf send_in_index 1014 ; if { send_in_index >= send_buffer_size } body end 1015 ; if exp=` send_in_index >= send_buffer_size ' false skip delay=4 1016 ; Other expression=`{ send_in_index >= send_buffer_size }' delay=4 1017 ; if { send_in_index >= send_buffer_size } end 1018 ; procedure send_byte end 1019 0ec 3400 retlw 0 1020 1021 ; procedure send_crlf start 1022 send_crlf: 1023 0038 send_crlf__variables__base equ global__variables__bank0+24 1024 0038 send_crlf__bytes__base equ send_crlf__variables__base+0 1025 0038 send_crlf__bits__base equ send_crlf__variables__base+0 1026 0000 send_crlf__total__bytes equ 0 1027 ; arguments_none 1028 ; This procedure will output a carriage - return line - feed 1029 ; to the master . 1030 ; call send_byte {{ cr }} 1031 0ed 300d movlw 13 1032 0ee 00b6 movwf send_byte__character 1033 0ef 20df call send_byte 1034 ; call send_byte {{ lf }} 1035 0f0 300a movlw 10 1036 0f1 00b6 movwf send_byte__character 1037 0f2 20df call send_byte 1038 ; procedure send_crlf end 1039 0f3 3400 retlw 0 1040 1041 ; procedure send_octal start 1042 send_octal: 1043 0038 send_octal__variables__base equ global__variables__bank0+24 1044 0038 send_octal__bytes__base equ send_octal__variables__base+0 1045 003a send_octal__bits__base equ send_octal__variables__base+2 1046 0002 send_octal__total__bytes equ 2 1047 0039 send_octal__462byte0 equ send_octal__bytes__base+1 1048 0039 send_octal__463byte0 equ send_octal__bytes__base+1 1049 0038 send_octal__number equ send_octal__bytes__base+0 1050 ; This procedure will output < number > in octal to the tx port . 1051 ; Output the character in octal : 1052 ; call send_byte {{ {{ number >> 6 }} + 0c'0' }} 1053 0f4 0e38 swapf send_octal__number,w 1054 0f5 00b9 movwf send_octal__462byte0 1055 0f6 0cb9 rrf send_octal__462byte0,f 1056 0f7 0c39 rrf send_octal__462byte0,w 1057 0f8 3903 andlw 3 1058 0f9 3e30 addlw 48 1059 0fa 00b6 movwf send_byte__character 1060 0fb 20df call send_byte 1061 ; call send_byte {{ {{ {{ number >> 3 }} & 7 }} + 0c'0' }} 1062 0fc 0c38 rrf send_octal__number,w 1063 0fd 00b9 movwf send_octal__463byte0 1064 0fe 0cb9 rrf send_octal__463byte0,f 1065 0ff 0c39 rrf send_octal__463byte0,w 1066 100 3907 andlw 7 1067 101 3e30 addlw 48 1068 102 00b6 movwf send_byte__character 1069 103 20df call send_byte 1070 ; call send_byte {{ {{ number & 7 }} + 0c'0' }} 1071 104 3007 movlw 7 1072 105 0538 andwf send_octal__number,w 1073 106 3e30 addlw 48 1074 107 00b6 movwf send_byte__character 1075 108 20df call send_byte 1076 ; call send_byte {{ sp }} 1077 109 3020 movlw 32 1078 10a 00b6 movwf send_byte__character 1079 10b 20df call send_byte 1080 ; procedure send_octal end 1081 10c 3400 retlw 0 1082 1083 ; procedure send_string start 1084 send_string: 1085 003a send_string__variables__base equ global__variables__bank0+26 1086 003a send_string__bytes__base equ send_string__variables__base+0 1087 003d send_string__bits__base equ send_string__variables__base+3 1088 0003 send_string__total__bytes equ 3 1089 003a send_string__message equ send_string__bytes__base+0 1090 ; This procedure will output < message > . 1091 003b send_string__size equ send_string__bytes__base+1 1092 003c send_string__index equ send_string__bytes__base+2 1093 ; index := 0 1094 10d 01bc clrf send_string__index 1095 ; `while index < message . size ...' start 1096 send_string__478while__continue: 1097 10e 018a clrf pclath___register 1098 10f 083a movf send_string__message,w 1099 110 200f call string___fetch 1100 111 023c subwf send_string__index,w 1101 ; expression=` index < message . size ' exp_delay=4 true_delay=7 false_delay=2 true_size=8 false_size=1 1102 112 1803 btfsc c___byte,c___bit 1103 113 291c goto send_string__478while__break 1104 ; call send_byte {{ message ~~ {{ index }} }} 1105 114 0a3c incf send_string__index,w 1106 115 073a addwf send_string__message,w 1107 116 018a clrf pclath___register 1108 117 200f call string___fetch 1109 118 00b6 movwf send_byte__character 1110 119 20df call send_byte 1111 ; index := index + 1 1112 11a 0abc incf send_string__index,f 1113 11b 290e goto send_string__478while__continue 1114 ; if exp=` index < message . size ' false goto 1115 ; Other expression=` index < message . size ' delay=-1 1116 send_string__478while__break: 1117 ; `while index < message . size ...' end 1118 ; call send_byte {{ sp }} 1119 11c 3020 movlw 32 1120 11d 00b6 movwf send_byte__character 1121 11e 20df call send_byte 1122 ; procedure send_string end 1123 11f 3400 retlw 0 1124 1125 ; Register bank 0 used 29 bytes of 96 available bytes 1126 ; Register bank 1 used 0 bytes of 80 available bytes 1127 ; Register bank 2 used 0 bytes of 48 available bytes 1128 ; Register bank 3 used 0 bytes of 0 available bytes 1129 1130 end